////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbddrsdram.v
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// Filename: wbddrsdram.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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// Possible commands to the DDR3 memory. These consist of settings for the
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// Possible commands to the DDR3 memory. These consist of settings for the
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// bits: o_wb_cs_n, o_wb_ras_n, o_wb_cas_n, and o_wb_we_n, respectively.
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// bits: o_wb_cs_n, o_wb_ras_n, o_wb_cas_n, and o_wb_we_n, respectively.
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`define DDR_MRSET 4'b0000
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`define DDR_MRSET 4'b0000
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`define DDR_REFRESH 4'b0001
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`define DDR_REFRESH 4'b0001
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`define DDR_PRECHARGE 4'b0010
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`define DDR_PRECHARGE 4'b0010
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`define DDR_ACTIVATE 4'b0011
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`define DDR_ACTIVATE 4'b0011
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`define DDR_WRITE 4'b0100
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`define DDR_WRITE 4'b0100
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`define DDR_READ 4'b0101
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`define DDR_READ 4'b0101
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`define DDR_ZQS 4'b0110
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`define DDR_NOOP 4'b0111
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`define DDR_NOOP 4'b0111
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//`define DDR_DESELECT 4'b1???
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//`define DDR_DESELECT 4'b1???
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//
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//
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// In this controller, 24-bit commands tend to be passed around. These
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// In this controller, 24-bit commands tend to be passed around. These
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// 'commands' are bit fields. Here we specify the bits associated with
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// 'commands' are bit fields. Here we specify the bits associated with
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// the bit fields.
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// the bit fields.
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`define DDR_RSTDONE 26 // End the reset sequence?
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`define DDR_RSTDONE 26 // End the reset sequence?
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`define DDR_RSTTIMER 25 // Does this reset command take multiple clocks?
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`define DDR_RSTTIMER 25 // Does this reset command take multiple clocks?
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`define DDR_RSTBIT 24 // Value to place on reset_n
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`define DDR_RSTBIT 24 // Value to place on reset_n
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`define DDR_CKEBIT 23 // Should this reset command set CKE?
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`define DDR_CKEBIT 23 // Should this reset command set CKE?
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`define DDR_CMDLEN 23
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`define DDR_CMDLEN 23
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`define DDR_CSBIT 22
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`define DDR_CSBIT 22
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`define DDR_RASBIT 21
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`define DDR_RASBIT 21
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`define DDR_CASBIT 20
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`define DDR_CASBIT 20
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`define DDR_WEBIT 19
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`define DDR_WEBIT 19
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`define DDR_NOPTIMER 18 // Steal this from BA bits
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`define DDR_NOPTIMER 18 // Steal this from BA bits
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`define DDR_BABITS 3 // BABITS are really from 18:16, they are 3 bits
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`define DDR_BABITS 3 // BABITS are really from 18:16, they are 3 bits
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`define DDR_ADDR_BITS 14
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`define DDR_ADDR_BITS 14
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module wbddrsdram(i_clk, i_reset,
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module wbddrsdram(i_clk, i_reset,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_dir,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data,
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o_cmd_accepted);
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parameter CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
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parameter CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
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CKRFC = 140;
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CKRFC = 140,
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CKXPR = CKRFC+5+2; // Clocks per tXPR timeout
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input i_clk, i_reset;
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input i_clk, i_reset;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [25:0] i_wb_addr;
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input [25:0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_ack;
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output reg o_wb_ack;
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output reg o_wb_stall;
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output reg o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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// DDR3 RAM Controller
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// DDR3 RAM Controller
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output wire o_ddr_reset_n, o_ddr_cke;
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output wire o_ddr_reset_n, o_ddr_cke;
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// Control outputs
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// Control outputs
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output reg o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
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output reg o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
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// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
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// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
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output wire o_ddr_dqs;
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output wire o_ddr_dqs;
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output reg o_ddr_dm, o_ddr_odt, o_ddr_bus_dir;
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output reg o_ddr_dm, o_ddr_odt, o_ddr_bus_oe;
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// Address outputs
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// Address outputs
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output reg [13:0] o_ddr_addr;
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output reg [13:0] o_ddr_addr;
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output reg [2:0] o_ddr_ba;
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output reg [2:0] o_ddr_ba;
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// And the data inputs and outputs
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// And the data inputs and outputs
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output reg [31:0] o_ddr_data;
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output reg [31:0] o_ddr_data;
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input i_ddr_data;
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input i_ddr_data;
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// And just for the test bench
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output reg o_cmd_accepted;
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always @(posedge i_clk)
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o_cmd_accepted <= (i_wb_stb)&&(~o_wb_stall);
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reg drive_dqs;
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reg drive_dqs;
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// The pending transaction
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// The pending transaction
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reg [31:0] r_data;
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reg [31:0] r_data;
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reg r_pending, r_we;
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reg r_pending, r_we;
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reg [25:0] r_addr;
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reg [25:0] r_addr;
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reg [14:0] r_row;
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reg [14:0] r_row;
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reg [2:0] r_bank;
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reg [2:0] r_bank;
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reg [9:0] r_col;
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reg [9:0] r_col;
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reg [1:0] r_sub;
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reg [1:0] r_sub;
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reg r_move; // It was accepted, and can move to next stage
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reg r_move; // It was accepted, and can move to next stage
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// Can the pending transaction be satisfied with the current (ongoing)
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// Can the pending transaction be satisfied with the current (ongoing)
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// transaction?
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// transaction?
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reg m_move, m_match, m_continue, m_pending, m_we;
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reg m_move, m_match, m_continue, m_pending, m_we;
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reg [25:0] m_addr;
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reg [25:0] m_addr;
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reg [14:0] m_row;
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reg [14:0] m_row;
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reg [2:0] m_bank;
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reg [2:0] m_bank;
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reg [9:0] m_col;
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reg [9:0] m_col;
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reg [1:0] m_sub;
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reg [1:0] m_sub;
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// Can we preload the next bank?
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// Can we preload the next bank?
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reg [14:0] r_nxt_row;
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reg [14:0] r_nxt_row;
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reg [2:0] r_nxt_bank;
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reg [2:0] r_nxt_bank;
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//
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//
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// tWTR = 7.5
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// tWTR = 7.5
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// tRRD = 7.5
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// tRRD = 7.5
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// tREFI= 7.8
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// tREFI= 7.8
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// tFAW = 45
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// tFAW = 45
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// tRTP = 7.5
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// tRTP = 7.5
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// tCKE = 5.625
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// tCKE = 5.625
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// tRFC = 160
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// tRFC = 160
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// tRP = 13.5
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// tRP = 13.5
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// tRAS = 36
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// tRAS = 36
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// tRCD = 13.5
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// tRCD = 13.5
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//
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//
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// RESET:
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// RESET:
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// 1. Hold o_reset_n = 1'b0; for 200 us, or 40,000 clocks (65536 perhaps?)
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// 1. Hold o_reset_n = 1'b0; for 200 us, or 40,000 clocks (65536 perhaps?)
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// Hold cke low during this time as well
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// Hold cke low during this time as well
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// The clock should be free running into the chip during this time
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// The clock should be free running into the chip during this time
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// Leave command in NOOP state: {cs,ras,cas,we} = 4'h7;
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// Leave command in NOOP state: {cs,ras,cas,we} = 4'h7;
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// ODT must be held low
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// ODT must be held low
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// 2. Hold cke low for another 500us, or 100,000 clocks
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// 2. Hold cke low for another 500us, or 100,000 clocks
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// 3. Raise CKE, continue outputting a NOOP for
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// 3. Raise CKE, continue outputting a NOOP for
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// tXPR, tDLLk, and tZQInit
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// tXPR, tDLLk, and tZQInit
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// 4. Load MRS2, wait tMRD
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// 4. Load MRS2, wait tMRD
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// 4. Load MRS3, wait tMRD
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// 4. Load MRS3, wait tMRD
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// 4. Load MRS1, wait tMOD
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// 4. Load MRS1, wait tMOD
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// Before using the SDRAM, we'll need to program at least 3 of the mode
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// Before using the SDRAM, we'll need to program at least 3 of the mode
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// registers, if not all 4.
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// registers, if not all 4.
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// tMOD clocks are required to program the mode registers, during which
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// tMOD clocks are required to program the mode registers, during which
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// time the RAM must be idle.
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// time the RAM must be idle.
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//
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//
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// NOOP: CS low, RAS, CAS, and WE high
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// NOOP: CS low, RAS, CAS, and WE high
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//
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//
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// Reset logic should be simple, and is given as follows:
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// Reset logic should be simple, and is given as follows:
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// note that it depends upon a ROM memory, reset_mem, and an address into that
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// note that it depends upon a ROM memory, reset_mem, and an address into that
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// memory: reset_address. Each memory location provides either a "command" to
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// memory: reset_address. Each memory location provides either a "command" to
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// the DDR3 SDRAM, or a timer to wait until the next command. Further, the
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// the DDR3 SDRAM, or a timer to wait until the next command. Further, the
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// timer commands indicate whether or not the command during the timer is to
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// timer commands indicate whether or not the command during the timer is to
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// be set to idle, or whether the command is instead left as it was.
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// be set to idle, or whether the command is instead left as it was.
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reg reset_override, reset_ztimer;
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reg reset_override, reset_ztimer;
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reg [3:0] reset_address;
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reg [3:0] reset_address;
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reg [(`DDR_CMDLEN-1):0] reset_cmd, cmd, refresh_cmd;
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reg [(`DDR_CMDLEN-1):0] reset_cmd, cmd, refresh_cmd;
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reg [26:0] reset_instruction;
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reg [26:0] reset_instruction;
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reg [16:0] reset_timer;
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reg [16:0] reset_timer;
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initial reset_override = 1'b1;
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initial reset_override = 1'b1;
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initial reset_address = 4'h0;
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initial reset_address = 4'h0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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begin
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begin
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reset_override <= 1'b1;
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reset_override <= 1'b1;
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reset_cmd <= { `DDR_NOOP, reset_instruction[18:0]};
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reset_cmd <= { `DDR_NOOP, reset_instruction[18:0]};
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end else if (!reset_ztimer)
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end else if (!reset_ztimer)
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;
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;
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else if (reset_instruction[`DDR_RSTDONE])
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else if (reset_instruction[`DDR_RSTDONE])
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reset_override <= 1'b0;
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reset_override <= 1'b0;
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else if (reset_instruction[`DDR_RSTTIMER])
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else
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begin
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if (reset_instruction[`DDR_NOPTIMER])
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reset_cmd <= { `DDR_NOOP, reset_instruction[18:0]};
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end else begin
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reset_cmd <= reset_instruction[22:0];
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reset_cmd <= reset_instruction[22:0];
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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o_ddr_cke <= 1'b0;
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o_ddr_cke <= 1'b0;
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else if ((reset_override)&&(reset_ztimer))
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else if ((reset_override)&&(reset_ztimer))
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o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
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o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
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initial reset_ztimer = 1'b1; // Is the timer zero?
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initial reset_ztimer = 1'b0; // Is the timer zero?
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initial reset_timer = 17'h00;
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initial reset_timer = 17'h01;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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begin
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begin
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reset_ztimer <= 1'b0;
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reset_ztimer <= 1'b0;
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reset_timer <= 17'h00;
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reset_timer <= 17'd1;
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end else if (!reset_ztimer)
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end else if (!reset_ztimer)
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begin
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begin
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reset_ztimer <= (reset_timer == 17'h01);
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reset_ztimer <= (reset_timer == 17'h01);
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reset_timer <= reset_timer - 17'h01;
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reset_timer <= reset_timer - 17'h01;
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end else if (reset_instruction[`DDR_RSTTIMER])
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end else if (reset_instruction[`DDR_RSTTIMER])
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begin
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begin
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reset_ztimer <= 1'b0;
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reset_ztimer <= 1'b0;
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reset_timer <= reset_instruction[16:0];
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reset_timer <= reset_instruction[16:0];
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end
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end
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wire [18:0] w_ckXPR = CKXPR, w_ckRST = 4, w_ckRP = 3,
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w_ckRFC = CKRFC;
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(reset_address) // RSTDONE, TIMER, CKE, ??
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if (i_reset)
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reset_instruction <= { 4'h4, `DDR_NOOP, 19'd40_000 };
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else case(reset_address) // RSTDONE, TIMER, CKE, ??
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// 1. Reset asserted (active low) for 200 us. (@200MHz)
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4'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 19'd40_000 };
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4'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 19'd40_000 };
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// 2. Reset de-asserted, wait 500 us before asserting CKE
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4'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 19'd100_000 };
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4'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 19'd100_000 };
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4'h2: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
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// 3. Assert CKE, wait minimum of Reset CKE Exit time
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4'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0, 3'h0, 1'b0, 3'h1, 1'b0, 1'b0, 3'h1, 1'b0, 1'b0, 2'b00 }; // MRS
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4'h2: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckXPR };
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4'h4: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
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// 4. Look MR2. (1CK, no TIMER)
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4'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2, 5'h0, 2'b00, 1'b0, 1'b0, 1'b1, 3'b0, 3'b0 }; // MRS2
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4'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2,
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4'h6: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
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5'h0, 2'b00, 1'b0, 1'b0, 1'b1, 3'b0, 3'b0 }; // MRS2
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4'h7: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1, 3'h0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 2'b0, 1'b1, 1'b0, 2'b0, 1'b1, 1'b1, 1'b0 }; // MRS1
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// 3. Wait 4 clocks (tMRD)
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4'h4: reset_instruction <= { 4'h7, `DDR_NOOP, 19'h04 };
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// 5. Set MR1
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4'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1,
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3'h0, // Reserved for Future Use (RFU)
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1'b0, // Qoff - output buffer enabled
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1'b1, // TDQS ... enabled
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1'b0, // RFU
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1'b0, // High order bit, Rtt_Nom (3'b011)
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1'b0, // RFU
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//
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1'b0, // Disable write-leveling
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1'b1, // Mid order bit of Rtt_Nom
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1'b0, // High order bit of Output Drvr Impedence Ctrl
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2'b0, // Additive latency = 0
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1'b1, // Low order bit of Rtt_Nom
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1'b1, // DIC set to 2'b01
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1'b1 }; // MRS1, DLL enable
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// 7. Wait another 4 clocks
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4'h6: reset_instruction <= { 4'h7, `DDR_NOOP, 19'h04 };
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// 8. Send MRS0
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4'h7: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0,
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3'b0, // Reserved for future use
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1'b0, // PPD control, (slow exit(DLL off))
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3'b1, // Write recovery for auto precharge
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1'b0, // DLL Reset (No)
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//
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1'b0, // TM mode normal
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3'b01, // High 3-bits, CAS latency (=4'b0010 = 4'd5)
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1'b0, // Read burst type = nibble sequential
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1'b0, // Low bit of cas latency
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2'b0 }; // Burst length = 8 (Fixed)
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// 9. Wait tMOD, is max(12 clocks, 15ns)
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4'h8: reset_instruction <= { 4'h7, `DDR_NOOP, 19'h0c };
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// 10. Issue a ZQCL command to start ZQ calibration, A10 is high
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4'h9: reset_instruction <= { 4'h7, `DDR_ZQS, 8'h0, 1'b1, 10'h0};
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//11.Wait for both tDLLK and tZQinit completed, both are 512 cks
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4'ha: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd512 };
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// 12. Precharge all command
|
|
4'hb: reset_instruction <= { 4'h7, `DDR_PRECHARGE, 8'h0, 1'b1, 10'h0 };
|
|
// 13. Wait for the precharge to complete
|
|
4'hc: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRP };
|
|
// 14. A single Auto Refresh commands
|
|
4'hd: reset_instruction <= { 4'h7, `DDR_REFRESH, 19'h00 };
|
|
// 15. Wait for the auto refresh to complete
|
|
4'he: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRFC };
|
|
// Two Auto Refresh commands
|
default:
|
default:
|
reset_instruction <={4'hb, `DDR_NOOP, 19'd00_000 };
|
reset_instruction <={4'hb, `DDR_NOOP, 19'd00_000 };
|
endcase
|
endcase
|
// reset_instruction <= reset_mem[reset_address];
|
// reset_instruction <= reset_mem[reset_address];
|
|
|
|
initial reset_address = 4'h0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_reset)
|
if (i_reset)
|
reset_address <= 4'h0;
|
reset_address <= 4'h0;
|
else if (reset_ztimer)
|
else if (reset_ztimer)
|
reset_address <= reset_address + 4'h1;
|
reset_address <= reset_address + 4'h1;
|
//
|
//
|
// initial reset_mem =
|
// initial reset_mem =
|
// 0. !DONE, TIMER,RESET_N=0, CKE=0, CMD = NOOP, TIMER = 200us ( 40,000)
|
// 0. !DONE, TIMER,RESET_N=0, CKE=0, CMD = NOOP, TIMER = 200us ( 40,000)
|
// 1. !DONE, TIMER,RESET_N=1, CKE=0, CMD = NOOP, TIMER = 500us (100,000)
|
// 1. !DONE, TIMER,RESET_N=1, CKE=0, CMD = NOOP, TIMER = 500us (100,000)
|
// 2. !DONE, TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = (Look me up)
|
// 2. !DONE, TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = (Look me up)
|
// 3. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS
|
// 3. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS
|
// 4. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
// 4. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
// 5. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS3
|
// 5. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS3
|
// 6. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
// 6. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
// 7. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
|
// 7. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
|
// 8. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
// 8. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
// 9. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
|
// 9. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
|
// 10. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMOD
|
// 10. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMOD
|
// 11. !DONE,!TIMER,RESET_N=1, CKE=1, (Pre-charge all)
|
// 11. !DONE,!TIMER,RESET_N=1, CKE=1, (Pre-charge all)
|
// 12. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
|
// 12. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
|
// 13. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
|
// 13. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
|
// 14. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
|
// 14. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
|
// 15. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
|
// 15. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
|
|
|
|
|
//
|
//
|
//
|
//
|
// Let's keep track of any open banks. There are 8 of them to keep track of.
|
// Let's keep track of any open banks. There are 8 of them to keep track of.
|
//
|
//
|
// A precharge requires 3 clocks at 200MHz to complete, 2 clocks at 100MHz.
|
// A precharge requires 3 clocks at 200MHz to complete, 2 clocks at 100MHz.
|
//
|
//
|
//
|
//
|
//
|
//
|
reg need_refresh;
|
reg need_refresh;
|
|
|
wire w_precharge_all;
|
wire w_precharge_all;
|
reg banks_are_closing, all_banks_closed;
|
reg banks_are_closing, all_banks_closed;
|
reg [2:0] bank_status[7:0];
|
reg [2:0] bank_status[7:0];
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
bank_status[0] = { bank_status[0][1:0], bank_status[0][0] };
|
bank_status[0] = { bank_status[0][1:0], bank_status[0][0] };
|
bank_status[1] = { bank_status[1][1:0], bank_status[1][0] };
|
bank_status[1] = { bank_status[1][1:0], bank_status[1][0] };
|
bank_status[2] = { bank_status[2][1:0], bank_status[2][0] };
|
bank_status[2] = { bank_status[2][1:0], bank_status[2][0] };
|
bank_status[3] = { bank_status[3][1:0], bank_status[3][0] };
|
bank_status[3] = { bank_status[3][1:0], bank_status[3][0] };
|
bank_status[4] = { bank_status[4][1:0], bank_status[4][0] };
|
bank_status[4] = { bank_status[4][1:0], bank_status[4][0] };
|
bank_status[5] = { bank_status[5][1:0], bank_status[5][0] };
|
bank_status[5] = { bank_status[5][1:0], bank_status[5][0] };
|
bank_status[6] = { bank_status[6][1:0], bank_status[6][0] };
|
bank_status[6] = { bank_status[6][1:0], bank_status[6][0] };
|
bank_status[7] = { bank_status[7][1:0], bank_status[7][0] };
|
bank_status[7] = { bank_status[7][1:0], bank_status[7][0] };
|
all_banks_closed <= (bank_status[0][1:0] == 2'b00)
|
all_banks_closed <= (bank_status[0][1:0] == 2'b00)
|
&&(bank_status[1][1:0] == 2'b00)
|
&&(bank_status[1][1:0] == 2'b00)
|
&&(bank_status[2][1:0] == 2'b00)
|
&&(bank_status[2][1:0] == 2'b00)
|
&&(bank_status[3][1:0] == 2'b00)
|
&&(bank_status[3][1:0] == 2'b00)
|
&&(bank_status[4][1:0] == 2'b00)
|
&&(bank_status[4][1:0] == 2'b00)
|
&&(bank_status[5][1:0] == 2'b00)
|
&&(bank_status[5][1:0] == 2'b00)
|
&&(bank_status[6][1:0] == 2'b00)
|
&&(bank_status[6][1:0] == 2'b00)
|
&&(bank_status[7][1:0] == 2'b00);
|
&&(bank_status[7][1:0] == 2'b00);
|
if ((!reset_override)&&(need_refresh)||(w_precharge_all))
|
if ((!reset_override)&&(need_refresh)||(w_precharge_all))
|
begin
|
begin
|
bank_status[0][0] = 1'b0;
|
bank_status[0][0] = 1'b0;
|
bank_status[1][0] = 1'b0;
|
bank_status[1][0] = 1'b0;
|
bank_status[2][0] = 1'b0;
|
bank_status[2][0] = 1'b0;
|
bank_status[3][0] = 1'b0;
|
bank_status[3][0] = 1'b0;
|
bank_status[4][0] = 1'b0;
|
bank_status[4][0] = 1'b0;
|
bank_status[5][0] = 1'b0;
|
bank_status[5][0] = 1'b0;
|
bank_status[6][0] = 1'b0;
|
bank_status[6][0] = 1'b0;
|
bank_status[7][0] = 1'b0;
|
bank_status[7][0] = 1'b0;
|
banks_are_closing <= 1'b1;
|
banks_are_closing <= 1'b1;
|
end else if (need_close_bank)
|
end else if (need_close_bank)
|
begin
|
begin
|
bank_status[r_bank][0] = 1'b0;
|
bank_status[r_bank][0] = 1'b0;
|
end else if (need_open_bank)
|
end else if (need_open_bank)
|
begin
|
begin
|
bank_status[r_bank][0] = 1'b1;
|
bank_status[r_bank][0] = 1'b1;
|
all_banks_closed <= 1'b0;
|
all_banks_closed <= 1'b0;
|
banks_are_closing <= 1'b0;
|
banks_are_closing <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
// if (cmd[22:19] == `DDR_ACTIVATE)
|
// if (cmd[22:19] == `DDR_ACTIVATE)
|
if (need_open_bank)
|
if (need_open_bank)
|
bank_address[activate_bank_cmd[18:16]]
|
bank_address[activate_bank_cmd[18:16]]
|
<= activate_bank_cmd[14:0];
|
<= activate_bank_cmd[14:0];
|
|
|
//
|
//
|
//
|
//
|
// Okay, let's investigate when we need to do a refresh. Our plan will be to
|
// Okay, let's investigate when we need to do a refresh. Our plan will be to
|
// do 4 refreshes every tREFI*4 seconds. tREFI = 7.8us, but its a parameter
|
// do 4 refreshes every tREFI*4 seconds. tREFI = 7.8us, but its a parameter
|
// in the number of clocks so that we can handle both 100MHz and 200MHz clocks.
|
// in the number of clocks so that we can handle both 100MHz and 200MHz clocks.
|
//
|
//
|
// Note that 160ns are needed between refresh commands (JEDEC, p172), or
|
// Note that 160ns are needed between refresh commands (JEDEC, p172), or
|
// 320 clocks @200MHz, or equivalently 160 clocks @100MHz. Thus to issue 4
|
// 320 clocks @200MHz, or equivalently 160 clocks @100MHz. Thus to issue 4
|
// of these refresh cycles will require 4*320=1280 clocks@200 MHz. After this
|
// of these refresh cycles will require 4*320=1280 clocks@200 MHz. After this
|
// time, no more refreshes will be needed for 6240 clocks.
|
// time, no more refreshes will be needed for 6240 clocks.
|
//
|
//
|
// Let's think this through:
|
// Let's think this through:
|
// REFRESH_COST = (n*(320)+24)/(n*1560)
|
// REFRESH_COST = (n*(320)+24)/(n*1560)
|
//
|
//
|
//
|
//
|
//
|
//
|
reg midrefresh, refresh_clear, endrefresh;
|
reg midrefresh, refresh_clear, endrefresh;
|
reg [12:0] refresh_clk;
|
reg [12:0] refresh_clk;
|
reg [2:0] midrefresh_hctr; // How many refresh cycles?
|
reg [2:0] midrefresh_hctr; // How many refresh cycles?
|
reg [8:0] midrefresh_lctr; // How many clks in this refresh cycle
|
reg [8:0] midrefresh_lctr; // How many clks in this refresh cycle
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((reset_override)||(refresh_clear))
|
if ((reset_override)||(refresh_clear))
|
refresh_clk <= CKREFI4;
|
refresh_clk <= CKREFI4;
|
else if (|refresh_clk)
|
else if (|refresh_clk)
|
refresh_clk <= refresh_clk-1;
|
refresh_clk <= refresh_clk-1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
need_refresh <= (refresh_clk == 0)||(midrefresh);
|
need_refresh <= (refresh_clk == 0)||(midrefresh);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (!need_refresh)
|
if (!need_refresh)
|
refresh_cmd <= { `DDR_NOOP, 19'h00 };
|
refresh_cmd <= { `DDR_NOOP, 19'h00 };
|
else if (~banks_are_closing)
|
else if (~banks_are_closing)
|
refresh_cmd <= { `DDR_PRECHARGE, 3'h0, 5'h0, 1'b1, 10'h00 };
|
refresh_cmd <= { `DDR_PRECHARGE, 3'h0, 5'h0, 1'b1, 10'h00 };
|
else if (~all_banks_closed)
|
else if (~all_banks_closed)
|
refresh_cmd <= { `DDR_NOOP, 19'h00 };
|
refresh_cmd <= { `DDR_NOOP, 19'h00 };
|
else
|
else
|
refresh_cmd <= { `DDR_REFRESH, 19'h00 };
|
refresh_cmd <= { `DDR_REFRESH, 19'h00 };
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
midrefresh <= (need_refresh)&&(all_banks_closed)&&(~refresh_clear);
|
midrefresh <= (need_refresh)&&(all_banks_closed)&&(~refresh_clear);
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (!midrefresh)
|
if (!midrefresh)
|
midrefresh_hctr <= 3'h4;
|
midrefresh_hctr <= 3'h4;
|
else if ((midrefresh_lctr == 0)&&(|midrefresh_hctr))
|
else if ((midrefresh_lctr == 0)&&(|midrefresh_hctr))
|
midrefresh_hctr <= midrefresh_hctr - 1;
|
midrefresh_hctr <= midrefresh_hctr - 1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((!need_refresh)||(!midrefresh))
|
if ((!need_refresh)||(!midrefresh))
|
endrefresh <= 1'b0;
|
endrefresh <= 1'b0;
|
else if (midrefresh_hctr == 3'h0)
|
else if (midrefresh_hctr == 3'h0)
|
endrefresh <= 1'b1;
|
endrefresh <= 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (!midrefresh)
|
if (!midrefresh)
|
midrefresh_lctr <= CKRFC;
|
midrefresh_lctr <= CKRFC;
|
else if (midrefresh_lctr == 0)
|
else if (midrefresh_lctr == 0)
|
midrefresh_lctr <= 0;
|
midrefresh_lctr <= 0;
|
else
|
else
|
midrefresh_lctr <= CKRFC;
|
midrefresh_lctr <= CKRFC;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
refresh_clear <= (need_refresh)&&(endrefresh)&&(midrefresh_lctr == 0);
|
refresh_clear <= (need_refresh)&&(endrefresh)&&(midrefresh_lctr == 0);
|
|
|
|
|
//
|
//
|
//
|
//
|
// Let's track: when will our bus be active? When will we be reading or
|
// Let's track: when will our bus be active? When will we be reading or
|
// writing?
|
// writing?
|
//
|
//
|
//
|
//
|
reg [8:0] bus_active, bus_read;
|
reg [8:0] bus_active, bus_read;
|
reg [1:0] bus_subaddr [8:0];
|
reg [1:0] bus_subaddr [8:0];
|
initial bus_active = 0;
|
initial bus_active = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
bus_active[8:0] <= { bus_active[7:0], 1'b0 };
|
bus_active[8:0] <= { bus_active[7:0], 1'b0 };
|
bus_read[8:0] <= { bus_read[7:0], 1'b0 }; // Drive the d-bus?
|
bus_read[8:0] <= { bus_read[7:0], 1'b0 }; // Drive the d-bus?
|
//bus_mask[8:0] <= { bus_mask[7:0], 1'b1 }; // Write this value?
|
//bus_mask[8:0] <= { bus_mask[7:0], 1'b1 }; // Write this value?
|
bus_subaddr[8] <= bus_subaddr[7];
|
bus_subaddr[8] <= bus_subaddr[7];
|
bus_subaddr[7] <= bus_subaddr[6];
|
bus_subaddr[7] <= bus_subaddr[6];
|
bus_subaddr[6] <= bus_subaddr[5];
|
bus_subaddr[6] <= bus_subaddr[5];
|
bus_subaddr[5] <= bus_subaddr[4];
|
bus_subaddr[5] <= bus_subaddr[4];
|
bus_subaddr[4] <= bus_subaddr[3];
|
bus_subaddr[4] <= bus_subaddr[3];
|
bus_subaddr[3] <= bus_subaddr[2];
|
bus_subaddr[3] <= bus_subaddr[2];
|
bus_subaddr[2] <= bus_subaddr[1];
|
bus_subaddr[2] <= bus_subaddr[1];
|
bus_subaddr[1] <= bus_subaddr[0];
|
bus_subaddr[1] <= bus_subaddr[0];
|
bus_subaddr[0] <= 2'h3;
|
bus_subaddr[0] <= 2'h3;
|
if (cmd[22:19] == `DDR_READ)
|
if ((!reset_override)&&(!need_refresh)&&(!need_close_bank)
|
|
&&(!need_open_bank)&&(valid_bank))
|
begin
|
begin
|
bus_active[3:0]<= 4'hf; // Once per clock
|
bus_active[3:0]<= 4'hf; // Once per clock
|
bus_read[3:0] <= 4'hf; // These will be reads
|
bus_read[3:0] <= 4'hf; // These will be reads
|
bus_subaddr[3] <= 2'h0;
|
bus_subaddr[3] <= 2'h0;
|
bus_subaddr[2] <= 2'h1;
|
bus_subaddr[2] <= 2'h1;
|
bus_subaddr[1] <= 2'h2;
|
bus_subaddr[1] <= 2'h2;
|
end else if (cmd == `DDR_WRITE)
|
|
begin
|
bus_read[3:0] <= (r_we)? 4'h0:4'hf;
|
bus_active[3:0] <= 4'hf;
|
|
// bus_read[7:4] = 4'h0;
|
|
bus_subaddr[3] <= 2'h0;
|
|
bus_subaddr[2] <= 2'h1;
|
|
bus_subaddr[1] <= 2'h2;
|
|
end
|
end
|
end
|
end
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
drive_dqs <= (~bus_read[8])&&(|bus_active[8:7]);
|
drive_dqs <= (~bus_read[8])&&(|bus_active[8:7]);
|
|
|
//
|
//
|
//
|
//
|
// Now, let's see, can we issue a read command?
|
// Now, let's see, can we issue a read command?
|
//
|
//
|
//
|
//
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if ((i_wb_stb)&&(~o_wb_stall))
|
if ((i_wb_stb)&&(~o_wb_stall))
|
begin
|
begin
|
r_pending <= 1'b1;
|
r_pending <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end else if ((r_move)||(m_move))
|
end else if ((r_move)||(m_move))
|
begin
|
begin
|
r_pending <= 1'b0;
|
r_pending <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
end
|
end
|
|
|
if (~o_wb_stall)
|
if (~o_wb_stall)
|
begin
|
begin
|
r_we <= i_wb_we;
|
r_we <= i_wb_we;
|
r_addr <= i_wb_addr;
|
r_addr <= i_wb_addr;
|
r_data <= i_wb_data;
|
r_data <= i_wb_data;
|
r_row <= i_wb_addr[25:11];
|
r_row <= i_wb_addr[25:11];
|
r_bank <= i_wb_addr[10:8];
|
r_bank <= i_wb_addr[10:8];
|
r_col <= { i_wb_addr[7:2], 2'b00 }; // 9:2
|
r_col <= { i_wb_addr[7:0], 2'b00 }; // 9:2
|
r_sub <= i_wb_addr[1:0];
|
r_sub <= i_wb_addr[1:0];
|
|
|
// pre-emptive work
|
// pre-emptive work
|
r_nxt_row <= i_wb_addr[25:11]+15'h1;
|
r_nxt_row <= i_wb_addr[25:11]+15'h1;
|
r_nxt_bank <= i_wb_addr[10:8]+3'h1;
|
r_nxt_bank <= i_wb_addr[10:8]+3'h1;
|
end
|
end
|
end
|
end
|
|
|
reg [2:0] bank_active[7:0];
|
reg [2:0] bank_active[7:0];
|
reg [14:0] bank_address[7:0];
|
reg [14:0] bank_address[7:0];
|
|
|
reg [(`DDR_CMDLEN-1):0] close_bank_cmd, activate_bank_cmd, rw_cmd;
|
reg [(`DDR_CMDLEN-1):0] close_bank_cmd, activate_bank_cmd, rw_cmd;
|
reg need_close_bank, need_close_this_bank,
|
reg need_close_bank, need_close_this_bank,
|
last_close_bank, maybe_close_next_bank,
|
last_close_bank, maybe_close_next_bank,
|
need_open_bank, last_open_bank, maybe_open_next_bank,
|
need_open_bank, last_open_bank, maybe_open_next_bank,
|
valid_bank, last_valid_bank;
|
valid_bank, last_valid_bank;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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need_close_bank <= (r_pending)&&(bank_active[r_bank][0])
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need_close_bank <= (r_pending)&&(bank_active[r_bank][0])
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&&(r_row != bank_address[r_bank])&&(!last_close_bank);
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&&(r_row != bank_address[r_bank])&&(!last_close_bank);
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need_close_this_bank <= (r_pending)&&(bank_active[r_bank][0])
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need_close_this_bank <= (r_pending)&&(bank_active[r_bank][0])
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&&(r_row != bank_address[r_bank]);
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&&(r_row != bank_address[r_bank]);
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last_close_bank <= need_close_bank;
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last_close_bank <= need_close_bank;
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|
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maybe_close_next_bank <= (r_pending)
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maybe_close_next_bank <= (r_pending)
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&&(bank_active[r_nxt_bank][0])
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&&(bank_active[r_nxt_bank][0])
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&&(r_nxt_row != bank_address[r_nxt_bank])
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&&(r_nxt_row != bank_address[r_nxt_bank])
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&&(!need_close_this_bank);
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&&(!need_close_this_bank);
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|
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close_bank_cmd <= (maybe_close_next_bank)
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close_bank_cmd <= (maybe_close_next_bank)
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? { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[14:10], 1'b0, r_nxt_row[9:0] }
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? { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[14:10], 1'b0, r_nxt_row[9:0] }
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: { `DDR_PRECHARGE, r_bank, r_row[15:11], 1'b0, r_row[9:0] };
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: { `DDR_PRECHARGE, r_bank, r_row[14:10], 1'b0, r_row[9:0] };
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|
|
|
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need_open_bank <= (r_pending)&&(bank_active[r_bank][1:0]==2'b00)
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need_open_bank <= (r_pending)&&(bank_active[r_bank][1:0]==2'b00)
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&&(!last_open_bank);
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&&(!last_open_bank);
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last_open_bank <= need_open_bank;
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last_open_bank <= need_open_bank;
|
|
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maybe_open_next_bank <= (r_pending)
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maybe_open_next_bank <= (r_pending)
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&&(bank_active[r_nxt_bank][1:0] == 2'b00)
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&&(bank_active[r_nxt_bank][1:0] == 2'b00)
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&&(!need_open_bank)&&(!need_close_bank);
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&&(!need_open_bank)&&(!need_close_bank);
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|
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activate_bank_cmd <= (maybe_open_next_bank)
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activate_bank_cmd <= (maybe_open_next_bank)
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? { `DDR_ACTIVATE,r_nxt_bank,1'b0,r_nxt_row[14:0] }
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? { `DDR_ACTIVATE,r_nxt_bank,1'b0,r_nxt_row[14:0] }
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: { `DDR_ACTIVATE, r_bank, 1'b0,r_row[14:0] };
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: { `DDR_ACTIVATE, r_bank, 1'b0,r_row[14:0] };
|
|
|
|
|
|
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valid_bank <= (r_pending)&&(bank_active[r_bank][1:0]==2'b11)
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valid_bank <= (r_pending)&&(bank_active[r_bank][1:0]==2'b11)
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&&(bank_address[r_bank]==r_row)
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&&(bank_address[r_bank]==r_row)
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&&(!last_valid_bank);
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&&(!last_valid_bank);
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last_valid_bank <= valid_bank;
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last_valid_bank <= valid_bank;
|
|
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rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (~r_pending)?`DDR_NOOP:((r_we)?`DDR_WRITE:`DDR_READ);
|
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (~r_pending)?`DDR_NOOP:((r_we)?`DDR_WRITE:`DDR_READ);
|
rw_cmd[`DDR_WEBIT-1:0] <= { r_bank, 5'h0, 1'b0, r_col };
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rw_cmd[`DDR_WEBIT-1:0] <= { r_bank, 5'h0, 1'b0, r_col };
|
end
|
end
|
|
|
|
|
// Match registers, to see if we can move forward without sending a
|
// Match registers, to see if we can move forward without sending a
|
// new command
|
// new command
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if (r_move)
|
if (r_move)
|
begin
|
begin
|
m_pending <= r_pending;
|
m_pending <= r_pending;
|
m_we <= r_we;
|
m_we <= r_we;
|
m_addr <= r_addr;
|
m_addr <= r_addr;
|
m_row <= r_row;
|
m_row <= r_row;
|
m_bank <= r_bank;
|
m_bank <= r_bank;
|
m_col <= r_col;
|
m_col <= r_col;
|
m_sub <= r_sub;
|
m_sub <= r_sub;
|
end else if (m_match)
|
end else if (m_match)
|
m_sub <= r_sub;
|
m_sub <= r_sub;
|
|
|
m_match <= (m_pending)&&(r_pending)&&(r_we == m_we)
|
m_match <= (m_pending)&&(r_pending)&&(r_we == m_we)
|
&&(r_row == m_row)&&(r_bank == m_bank)
|
&&(r_row == m_row)&&(r_bank == m_bank)
|
&&(r_col == m_col)
|
&&(r_col == m_col)
|
&&(r_sub > m_sub);
|
&&(r_sub > m_sub);
|
m_continue <= (m_pending)&&(r_pending)&&(r_we == m_we)
|
m_continue <= (m_pending)&&(r_pending)&&(r_we == m_we)
|
&&(r_row == m_row)&&(r_bank == m_bank)
|
&&(r_row == m_row)&&(r_bank == m_bank)
|
&&(r_col == m_col+10'h1);
|
&&(r_col == m_col+10'h1);
|
// m_nextbank <= (m_pending)&&(r_pending)&&(r_we == m_we)
|
// m_nextbank <= (m_pending)&&(r_pending)&&(r_we == m_we)
|
// &&(r_row == m_row)&&(r_bank == m_bank);
|
// &&(r_row == m_row)&&(r_bank == m_bank);
|
end
|
end
|
|
|
//
|
//
|
//
|
//
|
// Okay, let's look at the last assignment in our chain. It should look
|
// Okay, let's look at the last assignment in our chain. It should look
|
// something like:
|
// something like:
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_ddr_reset_n <= (~reset_override)||(reset_instruction[`DDR_RSTBIT]);
|
if (i_reset)
|
|
o_ddr_reset_n <= 1'b0;
|
|
else if (reset_ztimer)
|
|
o_ddr_reset_n <= reset_instruction[`DDR_RSTBIT];
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_ddr_cke <= (~reset_override)||(reset_instruction[`DDR_CKEBIT]);
|
if (i_reset)
|
|
o_ddr_cke <= 1'b0;
|
|
else if (reset_ztimer)
|
|
o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
r_move <= 1'b0;
|
r_move <= 1'b0;
|
if (reset_override)
|
if (reset_override)
|
cmd <= reset_cmd[`DDR_CSBIT:0];
|
cmd <= reset_cmd[`DDR_CSBIT:0];
|
else if (need_refresh)
|
else if (need_refresh)
|
begin
|
begin
|
cmd <= refresh_cmd; // The command from the refresh logc
|
cmd <= refresh_cmd; // The command from the refresh logc
|
end else if (need_close_bank)
|
end else if (need_close_bank)
|
cmd <= close_bank_cmd;
|
cmd <= close_bank_cmd;
|
else if (need_open_bank)
|
else if (need_open_bank)
|
cmd <= activate_bank_cmd;
|
cmd <= activate_bank_cmd;
|
else if ((valid_bank)&&(bus_active[2:0]==3'h0))
|
else if ((valid_bank)&&(bus_active[2:0]==3'h0))
|
begin
|
begin
|
cmd <= rw_cmd;
|
cmd <= rw_cmd;
|
r_move <= 1'b1;
|
r_move <= 1'b1;
|
end else
|
end else
|
cmd <= { `DDR_NOOP, rw_cmd[20:0] };
|
cmd <= { `DDR_NOOP, rw_cmd[(`DDR_WEBIT-1):0] };
|
end
|
end
|
|
|
reg [31:0] bus_data[8:0];
|
reg [31:0] bus_data[8:0];
|
|
|
assign o_ddr_cs_n = cmd[`DDR_CSBIT];
|
assign o_ddr_cs_n = cmd[`DDR_CSBIT];
|
assign o_ddr_ras_n = cmd[`DDR_RASBIT];
|
assign o_ddr_ras_n = cmd[`DDR_RASBIT];
|
assign o_ddr_cas_n = cmd[`DDR_CASBIT];
|
assign o_ddr_cas_n = cmd[`DDR_CASBIT];
|
assign o_ddr_we_n = cmd[`DDR_WEBIT];
|
assign o_ddr_we_n = cmd[`DDR_WEBIT];
|
assign o_ddr_dqs = drive_dqs;
|
assign o_ddr_dqs = drive_dqs;
|
assign o_ddr_addr = cmd[(`DDR_ADDR_BITS-1):0];
|
assign o_ddr_addr = cmd[(`DDR_ADDR_BITS-1):0];
|
assign o_ddr_ba = cmd[(`DDR_BABITS+`DDR_ADDR_BITS-1):`DDR_ADDR_BITS];
|
assign o_ddr_ba = cmd[(`DDR_BABITS+`DDR_ADDR_BITS-1):`DDR_ADDR_BITS];
|
assign o_ddr_data = bus_data[8];
|
assign o_ddr_data = bus_data[8];
|
assign w_precharge_all = (cmd[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
|
assign w_precharge_all = (cmd[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
|
&&(o_ddr_addr[10]); // 5 bits
|
&&(o_ddr_addr[10]); // 5 bits
|
|
|
// Need to set o_wb_dqs high one clock prior to any read.
|
// Need to set o_wb_dqs high one clock prior to any read.
|
// As per spec, ODT = 0 during reads
|
// As per spec, ODT = 0 during reads
|
assign o_ddr_bus_dir = bus_read[8];
|
assign o_ddr_bus_oe = ~bus_read[8];
|
assign o_ddr_odt = o_ddr_bus_dir;
|
|
|
// ODT must be in high impedence while reset_n=0, then it can be set
|
|
// to low or high.
|
|
assign o_ddr_odt = o_ddr_bus_oe;
|
|
|
|
|
endmodule
|
endmodule
|
|
|
