/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OpenCores/Dragonix DragonBall/68K to WISHBONE Interface ////
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//// OpenCores/Dragonix DragonBall/68K to WISHBONE Interface ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: dragonball_wbmaster.v,v 1.3 2003-01-09 16:46:14 rherveille Exp $
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// $Id: dragonball_wbmaster.v,v 1.3 2003-01-09 16:46:14 rherveille Exp $
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//
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//
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// $Date: 2003-01-09 16:46:14 $
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// $Date: 2003-01-09 16:46:14 $
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// $Revision: 1.3 $
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// $Revision: 1.3 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/12/22 16:09:33 rherveille
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// Revision 1.2 2002/12/22 16:09:33 rherveille
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// Timing enhancement bug fixes
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// Timing enhancement bug fixes
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//
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//
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//
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//
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//
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//
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// This core converts a 16bit DragonBall bus interface into a 16bit
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// This core converts a 16bit DragonBall bus interface into a 16bit
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// WISHBONE Master interface
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// WISHBONE Master interface
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module dragonball_wbmaster(
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module dragonball_wbmaster(
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clk, reset_n,
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clk, reset_n,
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a, cs_n, d, lwe_n, uwe_n, oe_n, dtack_n, berr,
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a, cs_n, d, lwe_n, uwe_n, oe_n, dtack_n, berr,
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clk_o, rst_o, cyc_o, stb_o, adr_o, sel_o, we_o, dat_o, dat_i, ack_i, err_i
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clk_o, rst_o, cyc_o, stb_o, adr_o, sel_o, we_o, dat_o, dat_i, ack_i, err_i
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);
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);
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//
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//
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// Parameters
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// Parameters
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//
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//
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parameter adr_hi = 9;
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parameter adr_hi = 9;
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//
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//
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// Inputs & outputs
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// Inputs & outputs
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//
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//
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// Motorola 68K bus
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// Motorola 68K bus
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input clk; // master clock
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input clk; // master clock
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input reset_n; // asynchronous active low reset
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input reset_n; // asynchronous active low reset
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input [adr_hi:1] a; // address inputs
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input [adr_hi:1] a; // address inputs
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input cs_n; // active low wishbone range chip select
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input cs_n; // active low wishbone range chip select
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inout [ 15:0] d; // data in-out
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inout [ 15:0] d; // data in-out
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input lwe_n, uwe_n; // active low lower-write enable, upper write enable
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input lwe_n, uwe_n; // active low lower-write enable, upper write enable
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input oe_n; // active low output enable signal
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input oe_n; // active low output enable signal
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output dtack_n; // active low data acknowledge
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output dtack_n; // active low data acknowledge
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output berr; // bus error
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output berr; // bus error
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// 16bit, 8bit granular WISHBONE bus master
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// 16bit, 8bit granular WISHBONE bus master
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output clk_o; // clock
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output clk_o; // clock
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output rst_o; // reset (asynchronous active low)
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output rst_o; // reset (asynchronous active low)
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output cyc_o; // cycle
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output cyc_o; // cycle
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output stb_o; // strobe (cycle and strobe are the same signal)
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output stb_o; // strobe (cycle and strobe are the same signal)
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output [adr_hi:1] adr_o; // address
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output [adr_hi:1] adr_o; // address
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output [ 1:0] sel_o; // select line (16bit bus ==> 2 select lines)
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output [ 1:0] sel_o; // select line (16bit bus ==> 2 select lines)
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output we_o; // write enable
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output we_o; // write enable
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output [ 15:0] dat_o; // data output
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output [ 15:0] dat_o; // data output
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input [ 15:0] dat_i; // data input
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input [ 15:0] dat_i; // data input
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input ack_i; // normal bus termination
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input ack_i; // normal bus termination
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input err_i; // abnormal bus termination (bus error)
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input err_i; // abnormal bus termination (bus error)
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//
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//
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// Module body
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// Module body
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//
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//
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reg cyc_o, stb_o;
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reg cyc_o, stb_o;
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reg [adr_hi:1] adr_o;
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reg [adr_hi:1] adr_o;
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reg [ 1:0] sel_o;
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reg [ 1:0] sel_o;
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reg we_o;
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reg we_o;
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reg dtack;
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reg dtack;
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reg [ 15:0] sdat_i;
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reg [ 15:0] sdat_i;
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wire cs = !cs_n & !(ack_i | err_i | dtack); // generate active high chip select signal
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wire cs = !cs_n & !(ack_i | err_i | dtack); // generate active high chip select signal
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wire lwe = !lwe_n; // generate active high lo_write_enable signal
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wire lwe = !lwe_n; // generate active high lo_write_enable signal
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wire uwe = !uwe_n; // generate active high hi_write_enable signal
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wire uwe = !uwe_n; // generate active high hi_write_enable signal
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wire oe = !oe_n; // generate active high output enable signal
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wire oe = !oe_n; // generate active high output enable signal
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assign clk_o = clk; // wishbone clock == external clock
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assign clk_o = clk; // wishbone clock == external clock
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assign rst_o = reset_n; // reset == external reset
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assign rst_o = reset_n; // reset == external reset
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assign berr = err_i;
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assign berr = err_i;
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always @(posedge clk or negedge reset_n)
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always @(posedge clk or negedge reset_n)
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if (!reset_n)
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if (!reset_n)
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begin
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begin
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cyc_o <= #1 1'b0;
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cyc_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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adr_o <= #1 {{adr_hi-1}{1'b0}};
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adr_o <= #1 {{adr_hi-1}{1'b0}};
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sel_o <= #1 2'b00;
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sel_o <= #1 2'b00;
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we_o <= #1 1'b0;
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we_o <= #1 1'b0;
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dtack <= #1 1'b0;
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dtack <= #1 1'b0;
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sdat_i <= #1 16'h0;
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sdat_i <= #1 16'h0;
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end
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end
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else
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else
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begin
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begin
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cyc_o <= #1 cs; // assert cyc_o when CS asserted
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cyc_o <= #1 cs; // assert cyc_o when CS asserted
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stb_o <= #1 cs; // assert stb_o when CS asserted
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stb_o <= #1 cs; // assert stb_o when CS asserted
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adr_o <= #1 a; // address == external address
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adr_o <= #1 a; // address == external address
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sel_o <= #1 oe ? 2'b11 : {uwe, lwe}; // generate select lines;
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sel_o <= #1 oe ? 2'b11 : {uwe, lwe}; // generate select lines;
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// read (oe asserted): SEL[1:0] = '11'
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// read (oe asserted): SEL[1:0] = '11'
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// write (oe negated): SEL[1:0] = 'uwe, lwe'
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// write (oe negated): SEL[1:0] = 'uwe, lwe'
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we_o <= #1 uwe | lwe; // write == uwe OR lwe asserted
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we_o <= #1 uwe | lwe; // write == uwe OR lwe asserted
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dtack <= #1 ack_i & !dtack; // generate DTACK signal
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dtack <= #1 ack_i & !dtack; // generate DTACK signal
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sdat_i <= #1 dat_i; // synchronize dat_i
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sdat_i <= #1 dat_i; // synchronize dat_i
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end
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end
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assign dat_o = d; // dat_o==external databus (not synchronised!!)
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assign dat_o = d; // dat_o==external databus (not synchronised!!)
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assign d = (~cs_n & oe) ? sdat_i : 16'hzzzz; // generate databus tri-state buffers
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assign d = (~cs_n & oe) ? sdat_i : 16'hzzzz; // generate databus tri-state buffers
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assign dtack_n = !dtack; // generate active low DTACK signal
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assign dtack_n = !dtack; // generate active low DTACK signal
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endmodule
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endmodule
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