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%% Filename:    spec.tex

%% Filename:    spec.tex

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%% Project:     Wishbone scope

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%% Purpose:     This LaTeX file contains all of the documentation/description

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%% Creator:     Dan Gisselquist

%% Creator:     Dan Gisselquist

%%              Gisselquist Technology, LLC

%%              Gisselquist Technology, LLC

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\documentclass{gqtekspec}

\documentclass{gqtekspec}

\project{Wishbone Scope}

\project{Wishbone Scope}

\title{Specification}

\title{Specification}

\author{Dan Gisselquist, Ph.D.}

\author{Dan Gisselquist, Ph.D.}

\email{dgisselq (at) opencores.org}

\email{dgisselq (at) opencores.org}

\revision{Rev.~0.1}

\revision{Rev.~0.1}

\begin{document}

\begin{document}

\pagestyle{gqtekspecplain}

\pagestyle{gqtekspecplain}

\titlepage

\titlepage

\begin{license}

\begin{license}

Copyright (C) \theyear\today, Gisselquist Technology, LLC

Copyright (C) \theyear\today, Gisselquist Technology, LLC

This project is free software (firmware): you can redistribute it and/or

This project is free software (firmware): you can redistribute it and/or

modify it under the terms of  the GNU General Public License as published

modify it under the terms of  the GNU General Public License as published

by the Free Software Foundation, either version 3 of the License, or (at

by the Free Software Foundation, either version 3 of the License, or (at

your option) any later version.

your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT

This program is distributed in the hope that it will be useful, but WITHOUT

ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

for more details.

for more details.

You should have received a copy of the GNU General Public License along

You should have received a copy of the GNU General Public License along

with this program.  If not, see \hbox{<http://www.gnu.org/licenses/>} for a

with this program.  If not, see \hbox{<http://www.gnu.org/licenses/>} for a

copy.

copy.

\end{license}

\end{license}

\begin{revisionhistory}

\begin{revisionhistory}

0.2 & 6/22/2015 & Gisselquist & Finished Draft \\\hline

0.2 & 6/22/2015 & Gisselquist & Finished Draft \\\hline

0.1 & 6/22/2015 & Gisselquist & First Draft \\\hline

0.1 & 6/22/2015 & Gisselquist & First Draft \\\hline

\end{revisionhistory}

\end{revisionhistory}

% Revision History

% Revision History

% Table of Contents, named Contents

% Table of Contents, named Contents

\tableofcontents

\tableofcontents

% \listoffigures

% \listoffigures

\listoftables

\listoftables

\begin{preface}

\begin{preface}

This project began, years ago, for all the wrong reasons.  Rather than pay a

This project began, years ago, for all the wrong reasons.  Rather than pay a

high price to purchase a Verilog simulator and then to learn how to use it,

high price to purchase a Verilog simulator and then to learn how to use it,

I took working Verilog code, to include a working bus, added features and

I took working Verilog code, to include a working bus, added features and

used the FPGA system as my testing platform.  I arranged the FPGA to step

used the FPGA system as my testing platform.  I arranged the FPGA to step

internal registers upon command, and to make many of those registers

internal registers upon command, and to make many of those registers

available via the bus.

available via the bus.

When I then needed to make the project run in real-time, as opposed to the

When I then needed to make the project run in real-time, as opposed to the

manually stepped approach, I generated a scope like this one.  I had already

manually stepped approach, I generated a scope like this one.  I had already

bench tested the components on the hardware itself.  Thu, testing and

bench tested the components on the hardware itself.  Thu, testing and

development continued on the hardware, and the scope helped me see what was

development continued on the hardware, and the scope helped me see what was

going right or wrong.  The great advantage of the approach was that, at the

going right or wrong.  The great advantage of the approach was that, at the

end of the project, I didn't need to do any hardware in the loop testing.

end of the project, I didn't need to do any hardware in the loop testing.

All of the testing that had been accomplished prior to that date was already

All of the testing that had been accomplished prior to that date was already

hardware in the loop testing.

hardware in the loop testing.

When I left that job, I took this concept with me and rebuilt this piece of

When I left that job, I took this concept with me and rebuilt this piece of

infrastructure using a Wishbone Bus.

infrastructure using a Wishbone Bus.

\end{preface}

\end{preface}

\chapter{Introduction}

\chapter{Introduction}

\pagenumbering{arabic}

\pagenumbering{arabic}

\setcounter{page}{1}

\setcounter{page}{1}

events have taken place.  In general, the scope records data until some

events have taken place.  In general, the scope records data until some

some (programmable) holdoff number of data samples after a trigger has taken

some (programmable) holdoff number of data samples after a trigger has taken

place.  Once the holdoff has been reached, the scope stops recording and

place.  Once the holdoff has been reached, the scope stops recording and

asserts an interrupt.  At this time, data may be read from the scope in order

asserts an interrupt.  At this time, data may be read from the scope in order

from oldest to most recent.  That's the basics, now for two extra details.

from oldest to most recent.  That's the basics, now for two extra details.

First, the trigger and the data that the scope records are both implementation

First, the trigger and the data that the scope records are both implementation

dependent.  The scope itself is designed to be easily reconfigurable from one

dependent.  The scope itself is designed to be easily reconfigurable from one

build to the next so that the actual configuration may even be build dependent.

build to the next so that the actual configuration may even be build dependent.

Second, the scope is built to be able to run off of a separate clock from the

Second, the scope is built to be able to run off of a separate clock from the

bus that commands and controls it.  This is configurable, set the parameter

bus that commands and controls it.  This is configurable, set the parameter

``SYNCHRONOUS'' to `1' to run off of a single clock.  When running off of two

``SYNCHRONOUS'' to `1' to run off of a single clock.  When running off of two

clocks, it means that actions associated with commands issued to the scope,

clocks, it means that actions associated with commands issued to the scope,

such as manual triggering or being disabled or released, will not act

such as manual triggering or being disabled or released, will not act

synchronously with the scope itself--but this is to be expected.

synchronously with the scope itself--but this is to be expected.

Third, the data clock associated with the scope has a clock enable line

Third, the data clock associated with the scope has a clock enable line

associated with it.  Depending on how often the clock enable line is enabled

associated with it.  Depending on how often the clock enable line is enabled

its collection.

its collection.

Finally, and in conclusion, this scope has been an invaluable tool for

Finally, and in conclusion, this scope has been an invaluable tool for

testing, for figuring out what is going on internal to a chip, and for fixing

testing, for figuring out what is going on internal to a chip, and for fixing

such things.  I have fixed interactions over a PS/2 connection, Internal

such things.  I have fixed interactions over a PS/2 connection, Internal

Configuration Access Port (ICAPE2) interfaces, mouse controller interactions,

Configuration Access Port (ICAPE2) interfaces, mouse controller interactions,

bus errors, quad-SPI flash interactions, and more using this scope.

bus errors, quad-SPI flash interactions, and more using this scope.

% \chapter{Architecture}

% \chapter{Architecture}

\chapter{Operation}

\chapter{Operation}

So how shall one use the scope?  The scope itself supports a series of

So how shall one use the scope?  The scope itself supports a series of

states:

states:

\begin{enumerate}

\begin{enumerate}

    Any write to the control register, without setting the high order bit,

    Any write to the control register, without setting the high order bit,

    Following a reset, once the scope has filled its memory, it enters the

    Following a reset, once the scope has filled its memory, it enters the

    the core, or manually, via a wishbone bus command.  Once a trigger

    the core, or manually, via a wishbone bus command.  Once a trigger

    has been received, the core will record a user configurable number of

    has been received, the core will record a user configurable number of

    further samples before stopping.

    further samples before stopping.

\end{enumerate}

\end{enumerate}

Let's go through that list again.  First, before using the scope, the holdoff

Let's go through that list again.  First, before using the scope, the holdoff

needs to be set.  The scope is designed so that setting the scope control value

needs to be set.  The scope is designed so that setting the scope control value

to the holdoff alone will reset the scope from whatever condition it was in,

to the holdoff alone will reset the scope from whatever condition it was in,

freeing it to run.  Once running, then upon every clock enabled clock, one

freeing it to run.  Once running, then upon every clock enabled clock, one

sample of data is read into the scope and recorded.  Once every memory value

sample of data is read into the scope and recorded.  Once every memory value

is filled, the scope has been {\tt PRIMED}.  Once the scope has been

is filled, the scope has been {\tt PRIMED}.  Once the scope has been

{\tt PRIMED}, it will then be responsive to its trigger.  Should the trigger be

{\tt PRIMED}, it will then be responsive to its trigger.  Should the trigger be

active on a clock--enabled input, the scope will then be {\tt TRIGGERED}.  It

active on a clock--enabled input, the scope will then be {\tt TRIGGERED}.  It

will then count for the number of clocks in the holdoff before stopping

will then count for the number of clocks in the holdoff before stopping

There are two further commands that will affect the operation of the scope.  The

There are two further commands that will affect the operation of the scope.  The

first is the {\tt MANUAL} trigger command/bit.  This bit may be set by writing

first is the {\tt MANUAL} trigger command/bit.  This bit may be set by writing

the holdoff to the control register while setting this bit high.  This will

the holdoff to the control register while setting this bit high.  This will

cause the scope to trigger immediately.  If coupled with a {\tt RESET} command,

cause the scope to trigger immediately.  If coupled with a {\tt RESET} command,

The last command that can affect the operation of the scope is the {\tt DISABLE}

The last command that can affect the operation of the scope is the {\tt DISABLE}

command/bit in the control register.  Setting this bit will prevent the scope

command/bit in the control register.  Setting this bit will prevent the scope

Finally, be careful how you set the clock enable line.  If the clock enable

Finally, be careful how you set the clock enable line.  If the clock enable

line leaves the clock too often disabled, the scope might never prime in any

line leaves the clock too often disabled, the scope might never prime in any

reasonable amount of time.

reasonable amount of time.

So, in summary, to use this scope you first set the holdoff value in the

So, in summary, to use this scope you first set the holdoff value in the

stopped.  Finally, you read from the data register once for every memory value

stopped.  Finally, you read from the data register once for every memory value

in the buffer and you can then sit back, relax, and study what took place

in the buffer and you can then sit back, relax, and study what took place

within the FPGA.

within the FPGA.

\chapter{Registers}

\chapter{Registers}

This scope core supports two registers, as listed in

This scope core supports two registers, as listed in

Tbl.~\ref{tbl:reglist}: a control register and a data register.

Tbl.~\ref{tbl:reglist}: a control register and a data register.

\begin{table}[htbp]

\begin{table}[htbp]

\begin{center}

\begin{center}

\begin{reglist}

\begin{reglist}

        scope.\\\hline

        scope.\\\hline

        from the core.  Writes to this register reset the read address

        from the core.  Writes to this register reset the read address

        to the beginning of the buffer, but are otherwise ignored.

        to the beginning of the buffer, but are otherwise ignored.

        \\\hline

        \\\hline

\end{reglist}\caption{List of Registers}\label{tbl:reglist}

\end{reglist}\caption{List of Registers}\label{tbl:reglist}

\end{center}\end{table}

\end{center}\end{table}

Each register will be discussed in detail in this chapter.

Each register will be discussed in detail in this chapter.

\section{Control Register}

\section{Control Register}

The bits in the control register are defined in Tbl.~\ref{tbl:control}.

The bits in the control register are defined in Tbl.~\ref{tbl:control}.

\begin{table}[htbp]

\begin{table}[htbp]

\begin{center}

\begin{center}

\begin{bitlist}

\begin{bitlist}

        Reading a `1' from this register means the reset has not finished

        Reading a `1' from this register means the reset has not finished

        crossing clock domains and is still pending.\\\hline

        crossing clock domains and is still pending.\\\hline

        the scope is counting for holdoff samples before stopping.\\\hline

        the scope is counting for holdoff samples before stopping.\\\hline

        scope is now waiting on a trigger.\\\hline

        scope is now waiting on a trigger.\\\hline

        register is pointed at the beginning of the memory.\\\hline

        register is pointed at the beginning of the memory.\\\hline

0--19 & R/W & Unsigned holdoff\\\hline

0--19 & R/W & Unsigned holdoff\\\hline

\end{bitlist}

\end{bitlist}

\caption{Control Register}\label{tbl:control}

\caption{Control Register}\label{tbl:control}

\end{center}\end{table}

\end{center}\end{table}

The register has been designed so that one need only write the holdoff value to

The register has been designed so that one need only write the holdoff value to

it, while leaving the other bits zero, to get the scope going.  On such a write,

it, while leaving the other bits zero, to get the scope going.  On such a write,

the RESET\_n bit will be a zero, causing the scope to internally reset itself.

the RESET\_n bit will be a zero, causing the scope to internally reset itself.

Further, during normal operation, the high order nibble will go from 4'h8

Further, during normal operation, the high order nibble will go from 4'h8

Finally, user's are cautioned not to adjust the holdoff between the time the

Finally, user's are cautioned not to adjust the holdoff between the time the

scope triggers and the time it stops--just to guarantee data coherency.

scope triggers and the time it stops--just to guarantee data coherency.

While this approach works, the scope has some other capabilities.  For example,

While this approach works, the scope has some other capabilities.  For example,

A second optional capability is to disable the scope entirely.  This might be

A second optional capability is to disable the scope entirely.  This might be

useful if, for example, certain irrelevant things might trigger the scope.

useful if, for example, certain irrelevant things might trigger the scope.

\section{Data Register}

\section{Data Register}

This is perhaps the simplest register to explain.  Before the core stops

This is perhaps the simplest register to explain.  Before the core stops

recording, reads from this register will produce reads of the bits going into

recording, reads from this register will produce reads of the bits going into

the core, save only that they have not been protected from any meta-stability

the core, save only that they have not been protected from any meta-stability

issues.  This is useful for reading what's going on when the various lines are

issues.  This is useful for reading what's going on when the various lines are

stuck.  After the core stops recording, reads from this register return values

stuck.  After the core stops recording, reads from this register return values

If you would like some assurance that you are reading from the beginning of the

If you would like some assurance that you are reading from the beginning of the

memory, you may either check the control register's {\tt RZERO} flag which will

memory, you may either check the control register's {\tt RZERO} flag which will

be `1' for the first value in the buffer, or you may write to the data register.

be `1' for the first value in the buffer, or you may write to the data register.

Such writes will be ignored, save that they will reset the read address back

Such writes will be ignored, save that they will reset the read address back

to the beginning of the buffer.

to the beginning of the buffer.

\chapter{Clocks}

\chapter{Clocks}

This scope supports two clocks: a wishbone bus clock, and a data clock.

This scope supports two clocks: a wishbone bus clock, and a data clock.

If the internal parameter ``SYNCHRONOUS'' is set to zero, proper transfers

If the internal parameter ``SYNCHRONOUS'' is set to zero, proper transfers

will take place between these two clocks.  Setting this parameter to a one

will take place between these two clocks.  Setting this parameter to a one

will save some flip flops and logic in implementation.  The speeds of the

will save some flip flops and logic in implementation.  The speeds of the

respective clocks are based upon the speed of your device, and not specific

respective clocks are based upon the speed of your device, and not specific

to this core.

to this core.

\chapter{Wishbone Datasheet}\label{chap:wishbone}

\chapter{Wishbone Datasheet}\label{chap:wishbone}

Tbl.~\ref{tbl:wishbone}

Tbl.~\ref{tbl:wishbone}

\begin{table}[htbp]

\begin{table}[htbp]

\begin{center}

\begin{center}

\begin{wishboneds}

\begin{wishboneds}

Revision level of wishbone & WB B4 spec \\\hline

Revision level of wishbone & WB B4 spec \\\hline

Type of interface & Slave, Read/Write, pipeline reads supported \\\hline

Type of interface & Slave, Read/Write, pipeline reads supported \\\hline

Port size & 32--bit \\\hline

Port size & 32--bit \\\hline

Port granularity & 32--bit \\\hline

Port granularity & 32--bit \\\hline

Maximum Operand Size & 32--bit \\\hline

Maximum Operand Size & 32--bit \\\hline

Data transfer ordering & (Irrelevant) \\\hline

Data transfer ordering & (Irrelevant) \\\hline

Clock constraints & None.\\\hline

Clock constraints & None.\\\hline

Signal Names & \begin{tabular}{ll}

Signal Names & \begin{tabular}{ll}

                Signal Name & Wishbone Equivalent \\\hline

                Signal Name & Wishbone Equivalent \\\hline

                {\tt i\_wb\_clk} & {\tt CLK\_I} \\

                {\tt i\_wb\_clk} & {\tt CLK\_I} \\

                {\tt i\_wb\_cyc} & {\tt CYC\_I} \\

                {\tt i\_wb\_cyc} & {\tt CYC\_I} \\

                {\tt i\_wb\_stb} & {\tt STB\_I} \\

                {\tt i\_wb\_stb} & {\tt STB\_I} \\

                {\tt i\_wb\_we} & {\tt WE\_I} \\

                {\tt i\_wb\_we} & {\tt WE\_I} \\

                {\tt i\_wb\_addr} & {\tt ADR\_I} \\

                {\tt i\_wb\_addr} & {\tt ADR\_I} \\

                {\tt i\_wb\_data} & {\tt DAT\_I} \\

                {\tt i\_wb\_data} & {\tt DAT\_I} \\

                {\tt o\_wb\_ack} & {\tt ACK\_O} \\

                {\tt o\_wb\_ack} & {\tt ACK\_O} \\

                {\tt o\_wb\_stall} & {\tt STALL\_O} \\

                {\tt o\_wb\_stall} & {\tt STALL\_O} \\

                {\tt o\_wb\_data} & {\tt DAT\_O}

                {\tt o\_wb\_data} & {\tt DAT\_O}

                \end{tabular}\\\hline

                \end{tabular}\\\hline

\end{wishboneds}

\end{wishboneds}

\caption{Wishbone Datasheet}\label{tbl:wishbone}

\caption{Wishbone Datasheet}\label{tbl:wishbone}

\end{center}\end{table}

\end{center}\end{table}

is required by the wishbone specification, and so

is required by the wishbone specification, and so

it is included here.  The big thing to notice is that this core

it is included here.  The big thing to notice is that this core

acts as a wishbone slave, and that all accesses to the wishbone scope

acts as a wishbone slave, and that all accesses to the wishbone scope

registers become 32--bit reads and writes to this interface.  You may also wish

registers become 32--bit reads and writes to this interface.  You may also wish

to note that the scope supports pipeline reads from the data port, to speed

to note that the scope supports pipeline reads from the data port, to speed

up reading the results out.

up reading the results out.

\chapter{IO Ports}

\chapter{IO Ports}

The ports are listed in Table.~\ref{tbl:ioports}.

The ports are listed in Table.~\ref{tbl:ioports}.

\begin{table}[htbp]

\begin{table}[htbp]

\begin{center}

\begin{center}

\begin{portlist}

\begin{portlist}

        out.\\\hline

        out.\\\hline

        set to one on any clock enabled data clock cycle, once

        set to one on any clock enabled data clock cycle, once

        \\\hline

        \\\hline

        recording and later examining.  These can be anything, only

        recording and later examining.  These can be anything, only

        they should be synchronous with the data clock.

        they should be synchronous with the data clock.

        \\\hline

        \\\hline

                \\\hline

                \\\hline

                \\\hline

                \\\hline

                register.  \\\hline

                register.  \\\hline

                ignored otherwise.  \\\hline

                ignored otherwise.  \\\hline

                \\\hline

                \\\hline

                \\\hline

                \\\hline

        read cycle when the {\tt i\_wb\_ack} line is high.

        read cycle when the {\tt i\_wb\_ack} line is high.

        \\\hline

        \\\hline

\end{portlist}

\end{portlist}

\caption{List of IO ports}\label{tbl:ioports}

\caption{List of IO ports}\label{tbl:ioports}

\end{center}\end{table}

\end{center}\end{table}

At this point, most of these ports should have been well defined and described

At this point, most of these ports should have been well defined and described

earlier in this document.  The only new things are the data clock, {\tt i\_clk},

earlier in this document.  The only new things are the data clock, {\tt i\_clk},

the clock enable for the data, {\tt i\_ce}, the trigger, {\tt i\_trigger}, and

the clock enable for the data, {\tt i\_ce}, the trigger, {\tt i\_trigger}, and

the data of interest itself, {\tt i\_data}.  Hopefully these are fairly self

the data of interest itself, {\tt i\_data}.  Hopefully these are fairly self

explanatory by this point.  If not, just remember the data, {\tt i\_data},

explanatory by this point.  If not, just remember the data, {\tt i\_data},

are synchronous to the clock, {\tt i\_clk}.  On every clock where the clock

are synchronous to the clock, {\tt i\_clk}.  On every clock where the clock

enable line is high, {\tt i\_ce}, the data will be recorded until the scope

enable line is high, {\tt i\_ce}, the data will be recorded until the scope

has stopped.  Further, the scope will stop some programmable holdoff number

has stopped.  Further, the scope will stop some programmable holdoff number

of clock enabled data clocks after {\tt i\_trigger} goes high.  Further,

of clock enabled data clocks after {\tt i\_trigger} goes high.  Further,

{\tt i\_trigger} need only be high for one clock cycle to be noticed by the

{\tt i\_trigger} need only be high for one clock cycle to be noticed by the

scope.

scope.

% Appendices

% Appendices

% Index

% Index

\end{document}

\end{document}