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%% Filename: spec.tex
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%% Filename: spec.tex
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%% Project: Wishbone scope
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%% Project: Wishbone scope
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%%
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%%
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%% Purpose: This LaTeX file contains all of the documentation/description
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%% Purpose: This LaTeX file contains all of the documentation/description
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%% currently provided with this Wishbone scope core. It's not
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%% currently provided with this Wishbone scope core. It's not
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%% nearly as interesting as the PDF file it creates, so I'd
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%% nearly as interesting as the PDF file it creates, so I'd
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%% recommend reading that before diving into this file. You
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%% recommend reading that before diving into this file. You
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%% should be able to find the PDF file in the SVN distribution
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%% in the doc directory and it (should) build without a problem.
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%% in the doc directory and it (should) build without a problem.
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%%
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%%
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%%
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%%
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%% Creator: Dan Gisselquist
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%% Creator: Dan Gisselquist
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%% Gisselquist Technology, LLC
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%% Gisselquist Technology, LLC
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%%
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%%
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%% Copyright (C) 2015, Gisselquist Technology, LLC
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%% Copyright (C) 2015, Gisselquist Technology, LLC
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%%
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%%
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%% This program is free software (firmware): you can redistribute it and/or
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%% This program is free software (firmware): you can redistribute it and/or
|
%% modify it under the terms of the GNU General Public License as published
|
%% modify it under the terms of the GNU General Public License as published
|
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%% by the Free Software Foundation, either version 3 of the License, or (at
|
%% your option) any later version.
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%% your option) any later version.
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%%
|
%%
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%% This program is distributed in the hope that it will be useful, but WITHOUT
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%% This program is distributed in the hope that it will be useful, but WITHOUT
|
%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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%% for more details.
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%% for more details.
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%%
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%%
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%% You should have received a copy of the GNU General Public License along
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|
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%%
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\documentclass{gqtekspec}
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\documentclass{gqtekspec}
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\project{Wishbone Scope}
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\project{Wishbone Scope}
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\title{Specification}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\email{dgisselq (at) opencores.org}
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\revision{Rev.~0.1}
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\revision{Rev.~0.1}
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\begin{document}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\pagestyle{gqtekspecplain}
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\titlepage
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\titlepage
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\begin{license}
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\begin{license}
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
|
|
|
This project is free software (firmware): you can redistribute it and/or
|
This project is free software (firmware): you can redistribute it and/or
|
modify it under the terms of the GNU General Public License as published
|
modify it under the terms of the GNU General Public License as published
|
by the Free Software Foundation, either version 3 of the License, or (at
|
by the Free Software Foundation, either version 3 of the License, or (at
|
your option) any later version.
|
your option) any later version.
|
|
|
This program is distributed in the hope that it will be useful, but WITHOUT
|
This program is distributed in the hope that it will be useful, but WITHOUT
|
ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
for more details.
|
for more details.
|
|
|
You should have received a copy of the GNU General Public License along
|
You should have received a copy of the GNU General Public License along
|
with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
|
with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
|
copy.
|
copy.
|
\end{license}
|
\end{license}
|
\begin{revisionhistory}
|
\begin{revisionhistory}
|
0.2 & 6/22/2015 & Gisselquist & Finished Draft \\\hline
|
0.2 & 6/22/2015 & Gisselquist & Finished Draft \\\hline
|
0.1 & 6/22/2015 & Gisselquist & First Draft \\\hline
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0.1 & 6/22/2015 & Gisselquist & First Draft \\\hline
|
\end{revisionhistory}
|
\end{revisionhistory}
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% Revision History
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% Revision History
|
% Table of Contents, named Contents
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% Table of Contents, named Contents
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\tableofcontents
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\tableofcontents
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% \listoffigures
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% \listoffigures
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\listoftables
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\listoftables
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\begin{preface}
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\begin{preface}
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This project began, years ago, for all the wrong reasons. Rather than pay a
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This project began, years ago, for all the wrong reasons. Rather than pay a
|
high price to purchase a Verilog simulator and then to learn how to use it,
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high price to purchase a Verilog simulator and then to learn how to use it,
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I took working Verilog code, to include a working bus, added features and
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I took working Verilog code, to include a working bus, added features and
|
used the FPGA system as my testing platform. I arranged the FPGA to step
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used the FPGA system as my testing platform. I arranged the FPGA to step
|
internal registers upon command, and to make many of those registers
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internal registers upon command, and to make many of those registers
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available via the bus.
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available via the bus.
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|
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When I then needed to make the project run in real-time, as opposed to the
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When I then needed to make the project run in real-time, as opposed to the
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manually stepped approach, I generated a scope like this one. I had already
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manually stepped approach, I generated a scope like this one. I had already
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bench tested the components on the hardware itself. Thu, testing and
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bench tested the components on the hardware itself. Thus, testing and
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development continued on the hardware, and the scope helped me see what was
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development continued on the hardware, and the scope helped me see what was
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going right or wrong. The great advantage of the approach was that, at the
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going right or wrong. The great advantage of the approach was that, at the
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end of the project, I didn't need to do any hardware in the loop testing.
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end of the project, I didn't need to do any hardware in the loop testing.
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All of the testing that had been accomplished prior to that date was already
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All of the testing that had been accomplished prior to that date was already
|
hardware in the loop testing.
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hardware in the loop testing.
|
|
|
When I left that job, I took this concept with me and rebuilt this piece of
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When I left that job, I took this concept with me and rebuilt this piece of
|
infrastructure using a Wishbone Bus.
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infrastructure using a Wishbone Bus.
|
\end{preface}
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\end{preface}
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|
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\chapter{Introduction}
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\chapter{Introduction}
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\pagenumbering{arabic}
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\pagenumbering{arabic}
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\setcounter{page}{1}
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\setcounter{page}{1}
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|
|
The Wishbone Scope is a debugging tool for reading results from the chip after
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The Wishbone Scope is a debugging tool for reading results from the chip after
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events have taken place. In general, the scope records data until some
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events have taken place. In general, the scope records data until some
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some (programmable) holdoff number of data samples after a trigger has taken
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some (programmable) holdoff number of data samples after a trigger has taken
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place. Once the holdoff has been reached, the scope stops recording and
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place. Once the holdoff has been reached, the scope stops recording and
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asserts an interrupt. At this time, data may be read from the scope in order
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asserts an interrupt. At this time, data may be read from the scope in order
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from oldest to most recent. That's the basics, now for two extra details.
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from oldest to most recent. That's the basics, now for two extra details.
|
|
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First, the trigger and the data that the scope records are both implementation
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First, the trigger and the data that the scope records are both implementation
|
dependent. The scope itself is designed to be easily reconfigurable from one
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dependent. The scope itself is designed to be easily reconfigurable from one
|
build to the next so that the actual configuration may even be build dependent.
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build to the next so that the actual configuration may even be build dependent.
|
|
|
Second, the scope is built to be able to run off of a separate clock from the
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Second, the scope is built to be able to run off of a separate clock from the
|
bus that commands and controls it. This is configurable, set the parameter
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bus that commands and controls it. This is configurable, set the parameter
|
``SYNCHRONOUS'' to `1' to run off of a single clock. When running off of two
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``SYNCHRONOUS'' to `1' to run off of a single clock. When running off of two
|
clocks, it means that actions associated with commands issued to the scope,
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clocks, it means that actions associated with commands issued to the scope,
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such as manual triggering or being disabled or released, will not act
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such as manual triggering or being disabled or released, will not act
|
synchronously with the scope itself--but this is to be expected.
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synchronously with the scope itself--but this is to be expected.
|
|
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Third, the data clock associated with the scope has a clock enable line
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Third, the data clock associated with the scope has a clock enable line
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associated with it. Depending on how often the clock enable line is enabled
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associated with it. Depending on how often the clock enable line is enabled
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may determine how fast the scope is {\tt PRIMED}, {\tt TRIGGERED}, and eventually completes
|
may determine how fast the scope is {\tt PRIMED}, {\tt TRIGGERED}, and eventually completes
|
its collection.
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its collection.
|
|
|
Finally, and in conclusion, this scope has been an invaluable tool for
|
Finally, and in conclusion, this scope has been an invaluable tool for
|
testing, for figuring out what is going on internal to a chip, and for fixing
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testing, for figuring out what is going on internal to a chip, and for fixing
|
such things. I have fixed interactions over a PS/2 connection, Internal
|
such things. I have fixed interactions over a PS/2 connection, Internal
|
Configuration Access Port (ICAPE2) interfaces, mouse controller interactions,
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Configuration Access Port (ICAPE2) interfaces, mouse controller interactions,
|
bus errors, quad-SPI flash interactions, and more using this scope.
|
bus errors, quad-SPI flash interactions, and more using this scope.
|
|
|
% \chapter{Architecture}
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% \chapter{Architecture}
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\chapter{Operation}
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\chapter{Operation}
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|
|
So how shall one use the scope? The scope itself supports a series of
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So how shall one use the scope? The scope itself supports a series of
|
states:
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states:
|
\begin{enumerate}
|
\begin{enumerate}
|
\item {\tt RESET}
|
\item {\tt RESET}
|
|
|
Any write to the control register, without setting the high order bit,
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Any write to the control register, without setting the high order bit,
|
will automatically reset the scope. Once reset, the scope will
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will automatically reset the scope. Once reset, the scope will
|
immediately start collecting.
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immediately start collecting.
|
\item {\tt PRIMED}
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\item {\tt PRIMED}
|
|
|
Following a reset, once the scope has filled its memory, it enters the
|
Following a reset, once the scope has filled its memory, it enters the
|
{\tt PRIMED} state. Once it reaches this state, it will be sensitive
|
{\tt PRIMED} state. Once it reaches this state, it will be sensitive
|
to a trigger.
|
to a trigger.
|
\item {\tt TRIGGERED}
|
\item {\tt TRIGGERED}
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|
|
The scope may be {\tt TRIGGERED} either automatically, via an input port to
|
The scope may be {\tt TRIGGERED} either automatically, via an input port to
|
the core, or manually, via a wishbone bus command. Once a trigger
|
the core, or manually, via a wishbone bus command. Once a trigger
|
has been received, the core will record a user configurable number of
|
has been received, the core will record a user configurable number of
|
further samples before stopping.
|
further samples before stopping.
|
|
|
\item {\tt STOPPED}
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\item {\tt STOPPED}
|
|
|
Once the core has {\tt STOPPED}, the data within it may be read back off.
|
Once the core has {\tt STOPPED}, the data within it may be read back off.
|
\end{enumerate}
|
\end{enumerate}
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|
|
Let's go through that list again. First, before using the scope, the holdoff
|
Let's go through that list again. First, before using the scope, the holdoff
|
needs to be set. The scope is designed so that setting the scope control value
|
needs to be set. The scope is designed so that setting the scope control value
|
to the holdoff alone will reset the scope from whatever condition it was in,
|
to the holdoff alone, with all other bits set to zero, will reset the scope
|
|
from whatever condition it was in,
|
freeing it to run. Once running, then upon every clock enabled clock, one
|
freeing it to run. Once running, then upon every clock enabled clock, one
|
sample of data is read into the scope and recorded. Once every memory value
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sample of data is read into the scope and recorded. Once every memory value
|
is filled, the scope has been {\tt PRIMED}. Once the scope has been
|
is filled, the scope has been {\tt PRIMED}. Once the scope has been
|
{\tt PRIMED}, it will then be responsive to its trigger. Should the trigger be
|
{\tt PRIMED}, it will then be responsive to its trigger. Should the trigger be
|
active on a clock--enabled input, the scope will then be {\tt TRIGGERED}. It
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active on an input clock with the clock--enable line set, the scope will then
|
|
be {\tt TRIGGERED}. It
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will then count for the number of clocks in the holdoff before stopping
|
will then count for the number of clocks in the holdoff before stopping
|
collection, placing it in the {\tt STOPPED} state. (Don't change the holdoff
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collection, placing it in the {\tt STOPPED} state. \footnote{You can even
|
during between triggered and stopped, or it may stop at some other non--holdoff
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change the holdoff while the scope is running by writing a new holdoff value
|
value!) If the holdoff is zero, the last sample in the buffer will be the
|
together with setting the {\tt RESET\_n} bit of the control register. However,
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sample containing the trigger. Likewise if the holdoff is one less than the
|
if you do this after the core has triggered it may stop at some other
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size of the memory, the first sample in the buffer will be the one containing
|
non--holdoff value!} If the holdoff is zero, the last sample in the buffer
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the trigger.
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will be the sample containing the trigger. Likewise if the holdoff is one
|
|
less than the size of the memory, the first sample in the buffer will be the
|
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one containing the trigger.
|
|
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There are two further commands that will affect the operation of the scope. The
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There are two further commands that will affect the operation of the scope. The
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first is the {\tt MANUAL} trigger command/bit. This bit may be set by writing
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first is the {\tt MANUAL} trigger command/bit. This bit may be set by writing
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the holdoff to the control register while setting this bit high. This will
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the holdoff to the control register while setting this bit high. This will
|
cause the scope to trigger immediately. If coupled with a {\tt RESET} command,
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cause the scope to trigger as soon as it is primed. If the {\tt RESET\_n}
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that is if the {\tt RESET\_n} bit isn't also set, then recording will start
|
bit is also set so as to prevent an internal reset, and if the scope was already
|
at the beginning and the scope will first wait until its {\tt PRIMED} state
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primed, then manual trigger command will cause it to trigger immediately.
|
before the manual trigger takes effect.
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|
|
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The last command that can affect the operation of the scope is the {\tt DISABLE}
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The last command that can affect the operation of the scope is the {\tt DISABLE}
|
command/bit in the control register. Setting this bit will prevent the scope
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command/bit in the control register. Setting this bit will prevent the scope
|
from triggering, or if {\tt TRIGGERED}, it will prevent the scope from
|
from triggering, or if {\tt TRIGGERED}, it will prevent the scope from
|
generating an interrupt.
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generating an interrupt.
|
|
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Finally, be careful how you set the clock enable line. If the clock enable
|
Finally, be careful how you set the clock enable line. If the clock enable
|
line leaves the clock too often disabled, the scope might never prime in any
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line leaves the clock too often disabled, the scope might never prime in any
|
reasonable amount of time.
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reasonable amount of time.
|
|
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So, in summary, to use this scope you first set the holdoff value in the
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So, in summary, to use this scope you first set the holdoff value in the
|
control register. Second, you wait until the scope has been {\tt TRIGGERED} and
|
control register. Second, you wait until the scope has been {\tt TRIGGERED}
|
stopped. Finally, you read from the data register once for every memory value
|
and {\tt STOPPED}. Finally, you read from the data register once for every
|
in the buffer and you can then sit back, relax, and study what took place
|
memory value in the buffer and you can then sit back, relax, and study what
|
within the FPGA.
|
took place within the FPGA. Additional modes allow you to manually trigger
|
|
the scope, or to disable the automatic trigger entirely.
|
|
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\chapter{Registers}
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\chapter{Registers}
|
|
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This scope core supports two registers, as listed in
|
This scope core supports two registers, as listed in
|
Tbl.~\ref{tbl:reglist}: a control register and a data register.
|
Tbl.~\ref{tbl:reglist}: a control register and a data register.
|
\begin{table}[htbp]
|
\begin{table}[htbp]
|
\begin{center}
|
\begin{center}
|
\begin{reglist}
|
\begin{reglist}
|
CONTROL & 0 & 32 & R/W & Configuration, control, and status of the
|
CONTROL & 0 & 32 & R/W & Configuration, control, and status of the
|
scope.\\\hline
|
scope.\\\hline
|
DATA & 1 & 32 & R(/W) & Read out register, to read out the data
|
DATA & 1 & 32 & R(/W) & Read out register, to read out the data
|
from the core. Writes to this register reset the read address
|
from the core. Writes to this register reset the read address
|
to the beginning of the buffer, but are otherwise ignored.
|
to the beginning of the buffer, but are otherwise ignored.
|
\\\hline
|
\\\hline
|
\end{reglist}\caption{List of Registers}\label{tbl:reglist}
|
\end{reglist}\caption{List of Registers}\label{tbl:reglist}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
Each register will be discussed in detail in this chapter.
|
Each register will be discussed in detail in this chapter.
|
|
|
\section{Control Register}
|
\section{Control Register}
|
The bits in the control register are defined in Tbl.~\ref{tbl:control}.
|
The bits in the control register are defined in Tbl.~\ref{tbl:control}.
|
\begin{table}[htbp]
|
\begin{table}[htbp]
|
\begin{center}
|
\begin{center}
|
\begin{bitlist}
|
\begin{bitlist}
|
31 & R/W & {\tt RESET\_n}. Write a `0' to this register to command a reset.
|
31 & R/W & {\tt RESET\_n}. Write a `0' to this register to command a reset.
|
Reading a `1' from this register means the reset has not finished
|
Reading a `1' from this register means the reset has not finished
|
crossing clock domains and is still pending.\\\hline
|
crossing clock domains and is still pending.\\\hline
|
30 & R & {\tt STOPPED}, indicates that all collection has stopped.\\\hline
|
30 & R & {\tt STOPPED}, indicates that all collection has stopped.\\\hline
|
29 & R & {\tt TRIGGERED}, indicates that a trigger has been recognized, and that
|
29 & R & {\tt TRIGGERED}, indicates that a trigger has been recognized, and that
|
the scope is counting for holdoff samples before stopping.\\\hline
|
the scope is counting for holdoff samples before stopping.\\\hline
|
28 & R & {\tt PRIMED}, indicates that the memory has been filled, and that the
|
28 & R & {\tt PRIMED}, indicates that the memory has been filled, and that the
|
scope is now waiting on a trigger.\\\hline
|
scope is now waiting on a trigger.\\\hline
|
27 & R/W & {\tt MANUAL}, set to invoke a manual trigger.\\\hline
|
27 & R/W & {\tt MANUAL}, set to invoke a manual trigger.\\\hline
|
26 & R/W & {\tt DISABLE}, set to disable the internal trigger. The scope may still
|
26 & R/W & {\tt DISABLE}, set to disable the internal trigger. The scope may still
|
be {\tt TRIGGERED} manually.\\\hline
|
be {\tt TRIGGERED} manually.\\\hline
|
25 & R & {\tt RZERO}, this will be true whenever the scope's internal address
|
25 & R & {\tt RZERO}, this will be true whenever the scope's internal address
|
register is pointed at the beginning of the memory.\\\hline
|
register is pointed at the beginning of the memory.\\\hline
|
20--24 & R & {\tt LGMEMLEN}, the base two logarithm of the memory length. Thus,
|
20--24 & R & {\tt LGMEMLEN}, the base two logarithm of the memory length. Thus,
|
the memory internal to the scope is given by 1$<<$LGMEMLEN. \\\hline
|
the memory internal to the scope is given by 1$<<$LGMEMLEN. \\\hline
|
0--19 & R/W & Unsigned holdoff\\\hline
|
0--19 & R/W & Unsigned holdoff\\\hline
|
\end{bitlist}
|
\end{bitlist}
|
\caption{Control Register}\label{tbl:control}
|
\caption{Control Register}\label{tbl:control}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
The register has been designed so that one need only write the holdoff value to
|
The register has been designed so that one need only write the holdoff value to
|
it, while leaving the other bits zero, to get the scope going. On such a write,
|
it, while leaving the other bits zero, to get the scope going. On such a write,
|
the RESET\_n bit will be a zero, causing the scope to internally reset itself.
|
the RESET\_n bit will be a zero, causing the scope to internally reset itself.
|
Further, during normal operation, the high order nibble will go from 4'h8
|
Further, during normal operation, the high order nibble will go from 4'h8
|
(a nearly instantaneous reset state) to 4'h0 (running), to 4'h1 ({\tt PRIMED}),
|
(a nearly instantaneous reset state) to 4'h0 (running), to 4'h1 ({\tt PRIMED}),
|
to 4'h3 ({\tt TRIGGERED}), and then stop at 4'h7 ({\tt PRIMED}, {\tt TRIGGERED},
|
to 4'h3 ({\tt TRIGGERED}), and then stop at 4'h7 ({\tt PRIMED}, {\tt TRIGGERED},
|
and {\tt STOPPED}).
|
and {\tt STOPPED}).
|
Finally, user's are cautioned not to adjust the holdoff between the time the
|
Finally, user's are cautioned not to adjust the holdoff between the time the
|
scope triggers and the time it stops--just to guarantee data coherency.
|
scope triggers and the time it stops--just to guarantee data coherency.
|
|
|
While this approach works, the scope has some other capabilities. For example,
|
While this approach works, the scope has some other capabilities. For example,
|
if you set the {\tt MANUAL} bit, the scope will trigger as soon as it is {\tt PRIMED}.
|
if you set the {\tt MANUAL} bit, the scope will trigger as soon as it is {\tt PRIMED}.
|
If you set the {\tt MANUAL} bit and the {\tt RESET\_n} bit, it will trigger
|
If you set the {\tt MANUAL} bit and the {\tt RESET\_n} bit, it will trigger
|
immediately if the scope was already {\tt PRIMED}. However, if the
|
immediately if the scope was already {\tt PRIMED}. However, if the
|
{\tt RESET\_n} bit was not also set, a reset will take place and the scope
|
{\tt RESET\_n} bit was not also set, a reset will take place and the scope
|
will start over by first collecting enough data to be {\tt PRIMED}, and only
|
will start over by first collecting enough data to be {\tt PRIMED}, and only
|
then will the {\tt MANUAL} trigger take effect.
|
then will the {\tt MANUAL} trigger take effect.
|
|
|
A second optional capability is to disable the scope entirely. This might be
|
A second optional capability is to disable the scope entirely. This might be
|
useful if, for example, certain irrelevant things might trigger the scope.
|
useful if, for example, certain irrelevant things might trigger the scope.
|
By setting the {\tt DISABLE} bit, the scope will not automatically trigger. It
|
By setting the {\tt DISABLE} bit, the scope will not automatically trigger. It
|
will still record into its memory, and it will still prime itself, it will just
|
will still record into its memory, and it will still prime itself, it will just
|
not trigger automatically. The scope may still be manually {\tt TRIGGERED}
|
not trigger automatically. The scope may still be manually {\tt TRIGGERED}
|
while the {\tt DISABLE} bit is set. Likewise, if the {\tt DISABLE} bit is set
|
while the {\tt DISABLE} bit is set. Likewise, if the {\tt DISABLE} bit is set
|
after the scope has been {\tt TRIGGERED}, the scope will continue to its
|
after the scope has been {\tt TRIGGERED}, the scope will continue to its
|
natural stopped state--it just won't generate an interrupt.
|
natural stopped state--it just won't generate an interrupt.
|
|
|
There are two other interesting bits in this control register. The {\tt RZERO}
|
There are two other interesting bits in this control register. The {\tt RZERO}
|
bit indicates that the next read from the data register will read from the first
|
bit indicates that the next read from the data register will read from the first
|
value in the memory, while the {\tt LGMEMLEN} bits indicate how long the memory is. Thus, if {\tt LGMEMLEN} is 10, the FIFO will be (1$<<$10) or 1024 words
|
value in the memory, while the {\tt LGMEMLEN} bits indicate how long the memory is. Thus, if {\tt LGMEMLEN} is 10, the FIFO will be (1$<<$10) or 1024 words
|
long, whereas if {\tt LGMEMLEN} is 14, the FIFO will be (1$<<$14) or 16,384 words
|
long, whereas if {\tt LGMEMLEN} is 14, the FIFO will be (1$<<$14) or 16,384 words
|
long.
|
long.
|
|
|
\section{Data Register}
|
\section{Data Register}
|
|
|
This is perhaps the simplest register to explain. Before the core stops
|
This is perhaps the simplest register to explain. Before the core stops
|
recording, reads from this register will produce reads of the bits going into
|
recording, reads from this register will produce reads of the bits going into
|
the core, save only that they have not been protected from any meta-stability
|
the core, save only that they have not been protected from any meta-stability
|
issues. This is useful for reading what's going on when the various lines are
|
issues. This is useful for reading what's going on when the various lines are
|
stuck. After the core stops recording, reads from this register return values
|
stuck. After the core stops recording, reads from this register return values
|
from the stored memory, beginning at the oldest and ending with the value
|
from the stored memory, beginning at the oldest and ending with the value
|
holdoff clocks after the trigger. Further, after recording has stopped, every
|
holdoff clocks after the trigger. Further, after recording has stopped, every
|
read increments an internal memory address, so that after (1$<<$LGMEMLEN)
|
read increments an internal memory address, so that after (1$<<$LGMEMLEN)
|
reads (for however long the internal memory is), the entire memory has been
|
reads (for however long the internal memory is), the entire memory has been
|
returned over the bus.
|
returned over the bus.
|
If you would like some assurance that you are reading from the beginning of the
|
If you would like some assurance that you are reading from the beginning of the
|
memory, you may either check the control register's {\tt RZERO} flag which will
|
memory, you may either check the control register's {\tt RZERO} flag which will
|
be `1' for the first value in the buffer, or you may write to the data register.
|
be `1' for the first value in the buffer, or you may write to the data register.
|
Such writes will be ignored, save that they will reset the read address back
|
Such writes will be ignored, save that they will reset the read address back
|
to the beginning of the buffer.
|
to the beginning of the buffer.
|
|
|
\chapter{Clocks}
|
\chapter{Clocks}
|
|
|
This scope supports two clocks: a wishbone bus clock, and a data clock.
|
This scope supports two clocks: a wishbone bus clock, and a data clock.
|
If the internal parameter ``SYNCHRONOUS'' is set to zero, proper transfers
|
If the internal parameter ``SYNCHRONOUS'' is set to zero, proper transfers
|
will take place between these two clocks. Setting this parameter to a one
|
will take place between these two clocks. Setting this parameter to a one
|
will save some flip flops and logic in implementation. The speeds of the
|
will save some flip flops and logic in implementation. The speeds of the
|
respective clocks are based upon the speed of your device, and not specific
|
respective clocks are based upon the speed of your device, and not specific
|
to this core.
|
to this core.
|
|
|
\chapter{Wishbone Datasheet}\label{chap:wishbone}
|
\chapter{Wishbone Datasheet}\label{chap:wishbone}
|
Tbl.~\ref{tbl:wishbone}
|
Tbl.~\ref{tbl:wishbone}
|
\begin{table}[htbp]
|
\begin{table}[htbp]
|
\begin{center}
|
\begin{center}
|
\begin{wishboneds}
|
\begin{wishboneds}
|
Revision level of wishbone & WB B4 spec \\\hline
|
Revision level of wishbone & WB B4 spec \\\hline
|
Type of interface & Slave, Read/Write, pipeline reads supported \\\hline
|
Type of interface & Slave, Read/Write, pipeline reads supported \\\hline
|
Port size & 32--bit \\\hline
|
Port size & 32--bit \\\hline
|
Port granularity & 32--bit \\\hline
|
Port granularity & 32--bit \\\hline
|
Maximum Operand Size & 32--bit \\\hline
|
Maximum Operand Size & 32--bit \\\hline
|
Data transfer ordering & (Irrelevant) \\\hline
|
Data transfer ordering & (Irrelevant) \\\hline
|
Clock constraints & None.\\\hline
|
Clock constraints & None.\\\hline
|
Signal Names & \begin{tabular}{ll}
|
Signal Names & \begin{tabular}{ll}
|
Signal Name & Wishbone Equivalent \\\hline
|
Signal Name & Wishbone Equivalent \\\hline
|
{\tt i\_wb\_clk} & {\tt CLK\_I} \\
|
{\tt i\_wb\_clk} & {\tt CLK\_I} \\
|
{\tt i\_wb\_cyc} & {\tt CYC\_I} \\
|
{\tt i\_wb\_cyc} & {\tt CYC\_I} \\
|
{\tt i\_wb\_stb} & {\tt STB\_I} \\
|
{\tt i\_wb\_stb} & {\tt STB\_I} \\
|
{\tt i\_wb\_we} & {\tt WE\_I} \\
|
{\tt i\_wb\_we} & {\tt WE\_I} \\
|
{\tt i\_wb\_addr} & {\tt ADR\_I} \\
|
{\tt i\_wb\_addr} & {\tt ADR\_I} \\
|
{\tt i\_wb\_data} & {\tt DAT\_I} \\
|
{\tt i\_wb\_data} & {\tt DAT\_I} \\
|
{\tt o\_wb\_ack} & {\tt ACK\_O} \\
|
{\tt o\_wb\_ack} & {\tt ACK\_O} \\
|
{\tt o\_wb\_stall} & {\tt STALL\_O} \\
|
{\tt o\_wb\_stall} & {\tt STALL\_O} \\
|
{\tt o\_wb\_data} & {\tt DAT\_O}
|
{\tt o\_wb\_data} & {\tt DAT\_O}
|
\end{tabular}\\\hline
|
\end{tabular}\\\hline
|
\end{wishboneds}
|
\end{wishboneds}
|
\caption{Wishbone Datasheet}\label{tbl:wishbone}
|
\caption{Wishbone Datasheet}\label{tbl:wishbone}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
is required by the wishbone specification, and so
|
is required by the wishbone specification, and so
|
it is included here. The big thing to notice is that this core
|
it is included here. The big thing to notice is that this core
|
acts as a wishbone slave, and that all accesses to the wishbone scope
|
acts as a wishbone slave, and that all accesses to the wishbone scope
|
registers become 32--bit reads and writes to this interface. You may also wish
|
registers become 32--bit reads and writes to this interface. You may also wish
|
to note that the scope supports pipeline reads from the data port, to speed
|
to note that the scope supports pipeline reads from the data port, to speed
|
up reading the results out.
|
up reading the results out.
|
|
|
|
What this table doesn't show is that all accesses to the port take a single
|
|
clock. That is, if the {\tt i\_wb\_stb} line is high on one clock, the
|
|
{\tt i\_wb\_ack} line will be high the next. Further, the {\tt o\_wb\_stall}
|
|
line is tied to zero.
|
\chapter{IO Ports}
|
\chapter{IO Ports}
|
|
|
The ports are listed in Table.~\ref{tbl:ioports}.
|
The ports are listed in Table.~\ref{tbl:ioports}.
|
\begin{table}[htbp]
|
\begin{table}[htbp]
|
\begin{center}
|
\begin{center}
|
\begin{portlist}
|
\begin{portlist}
|
{\tt i\_clk} & 1 & Input & The clock the data lines, clock enable, and trigger
|
{\tt i\_clk} & 1 & Input & The clock the data lines, clock enable, and trigger
|
are synchronous to. \\\hline
|
are synchronous to. \\\hline
|
{\tt i\_ce} & 1 & Input & Clock Enable. Set this high to clock data in and
|
{\tt i\_ce} & 1 & Input & Clock Enable. Set this high to clock data in and
|
out.\\\hline
|
out.\\\hline
|
{\tt i\_trigger} & 1 & Input & An active high trigger line. If this trigger is
|
{\tt i\_trigger} & 1 & Input & An active high trigger line. If this trigger is
|
set to one on any clock enabled data clock cycle, once
|
set to one on any clock enabled data clock cycle, once
|
the scope has been {\tt PRIMED}, it will then enter into its
|
the scope has been {\tt PRIMED}, it will then enter into its
|
{\tt TRIGGERED} state.
|
{\tt TRIGGERED} state.
|
\\\hline
|
\\\hline
|
{\tt i\_data} & 32 & Input & 32--wires of ... whatever you are interested in
|
{\tt i\_data} & 32 & Input & 32--wires of ... whatever you are interested in
|
recording and later examining. These can be anything, only
|
recording and later examining. These can be anything, only
|
they should be synchronous with the data clock.
|
they should be synchronous with the data clock.
|
\\\hline
|
\\\hline
|
{\tt i\_wb\_clk} & 1 & Input & The clock that the wishbone interface runs on.
|
{\tt i\_wb\_clk} & 1 & Input & The clock that the wishbone interface runs on.
|
\\\hline
|
\\\hline
|
{\tt i\_wb\_cyc} & 1 & Input & Indicates a wishbone bus cycle is active when
|
{\tt i\_wb\_cyc} & 1 & Input & Indicates a wishbone bus cycle is active when
|
high. \\\hline
|
high. \\\hline
|
{\tt i\_wb\_stb} & 1 & Input & Indicates a wishbone bus cycle for this
|
{\tt i\_wb\_stb} & 1 & Input & Indicates a wishbone bus cycle for this
|
peripheral when high. (See the wishbone spec for more details) \\\hline
|
peripheral when high. (See the wishbone spec for more details) \\\hline
|
{\tt i\_wb\_we} & 1 & Input & Write enable, allows indicates a write to one of
|
{\tt i\_wb\_we} & 1 & Input & Write enable, allows indicates a write to one of
|
the two registers when {\tt i\_wb\_stb} is also high.
|
the two registers when {\tt i\_wb\_stb} is also high.
|
\\\hline
|
\\\hline
|
{\tt i\_wb\_addr} & 1 & Input & A single address line, set to zero to access the
|
{\tt i\_wb\_addr} & 1 & Input & A single address line, set to zero to access the
|
configuration and control register, to one to access the data
|
configuration and control register, to one to access the data
|
register. \\\hline
|
register. \\\hline
|
{\tt i\_wb\_data} & 32 & Input & Data used when writing to the control register,
|
{\tt i\_wb\_data} & 32 & Input & Data used when writing to the control register,
|
ignored otherwise. \\\hline
|
ignored otherwise. \\\hline
|
{\tt o\_wb\_ack} & 1 & Output & Wishbone acknowledgement. This line will go
|
{\tt o\_wb\_ack} & 1 & Output & Wishbone acknowledgement. This line will go
|
high on the clock after any wishbone access, as long as the
|
high on the clock after any wishbone access, as long as the
|
wishbone {\tt i\_wb\_cyc} line remains high (i.e., no ack's if
|
wishbone {\tt i\_wb\_cyc} line remains high (i.e., no ack's if
|
you terminate the cycle early).
|
you terminate the cycle early).
|
\\\hline
|
\\\hline
|
{\tt o\_wb\_stall} & 1 & Output & Required by the wishbone spec, but always
|
{\tt o\_wb\_stall} & 1 & Output & Required by the wishbone spec, but always
|
set to zero in this implementation.
|
set to zero in this implementation.
|
\\\hline
|
\\\hline
|
{\tt o\_wb\_data} & 32 & Output & Values read, either control or data, headed
|
{\tt o\_wb\_data} & 32 & Output & Values read, either control or data, headed
|
back to the wishbone bus. These values will be valid during any
|
back to the wishbone bus. These values will be valid during any
|
read cycle when the {\tt i\_wb\_ack} line is high.
|
read cycle when the {\tt i\_wb\_ack} line is high.
|
\\\hline
|
\\\hline
|
\end{portlist}
|
\end{portlist}
|
\caption{List of IO ports}\label{tbl:ioports}
|
\caption{List of IO ports}\label{tbl:ioports}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
At this point, most of these ports should have been well defined and described
|
At this point, most of these ports should have been well defined and described
|
earlier in this document. The only new things are the data clock, {\tt i\_clk},
|
earlier in this document. The only new things are the data clock, {\tt i\_clk},
|
the clock enable for the data, {\tt i\_ce}, the trigger, {\tt i\_trigger}, and
|
the clock enable for the data, {\tt i\_ce}, the trigger, {\tt i\_trigger}, and
|
the data of interest itself, {\tt i\_data}. Hopefully these are fairly self
|
the data of interest itself, {\tt i\_data}. Hopefully these are fairly self
|
explanatory by this point. If not, just remember the data, {\tt i\_data},
|
explanatory by this point. If not, just remember the data, {\tt i\_data},
|
are synchronous to the clock, {\tt i\_clk}. On every clock where the clock
|
are synchronous to the clock, {\tt i\_clk}. On every clock where the clock
|
enable line is high, {\tt i\_ce}, the data will be recorded until the scope
|
enable line is high, {\tt i\_ce}, the data will be recorded until the scope
|
has stopped. Further, the scope will stop some programmable holdoff number
|
has stopped. Further, the scope will stop some programmable holdoff number
|
of clock enabled data clocks after {\tt i\_trigger} goes high. Further,
|
of clock enabled data clocks after {\tt i\_trigger} goes high. Further,
|
{\tt i\_trigger} need only be high for one clock cycle to be noticed by the
|
{\tt i\_trigger} need only be high for one clock cycle to be noticed by the
|
scope.
|
scope.
|
|
|
% Appendices
|
% Appendices
|
% Index
|
% Index
|
\end{document}
|
\end{document}
|
|
|
|
|
|
|