////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: helloworld.v
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// Filename: helloworld.v
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//
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//
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// Project: wbuart32, a full featured UART with simulator
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// Project: wbuart32, a full featured UART with simulator
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//
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//
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// Purpose: To create a *very* simple UART test program, which can be used
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// Purpose: To create a *very* simple UART test program, which can be used
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// as the top level design file of any FPGA program.
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// as the top level design file of any FPGA program.
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//
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//
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// With some modifications (discussed below), this RTL should be able to
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// With some modifications (discussed below), this RTL should be able to
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// run as a top-level testing file, requiring only the UART and clock pin
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// run as a top-level testing file, requiring only the UART and clock pin
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// to work.
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// to work.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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// One issue with the design is how to set the values of the setup register.
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// One issue with the design is how to set the values of the setup register.
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// (*This is a comment, not a verilator attribute ... ) Verilator needs to
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// (*This is a comment, not a verilator attribute ... ) Verilator needs to
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// know/set those values in order to work. However, this design can also be
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// know/set those values in order to work. However, this design can also be
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// used as a stand-alone top level configuration file. In this latter case,
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// used as a stand-alone top level configuration file. In this latter case,
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// the setup register needs to be set internal to the file. Here, we use
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// the setup register needs to be set internal to the file. Here, we use
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// OPT_STANDALONE to distinguish between the two. If set, the file runs under
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// OPT_STANDALONE to distinguish between the two. If set, the file runs under
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// (* Another comment still ...) Verilator and we need to get i_setup from the
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// (* Another comment still ...) Verilator and we need to get i_setup from the
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// external environment. If not, it must be set internally.
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// external environment. If not, it must be set internally.
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//
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//
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`ifndef VERILATOR
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`ifndef VERILATOR
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`define OPT_STANDALONE
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`define OPT_STANDALONE
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`endif
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`endif
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//
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//
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//
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// Two versions of the UART can be found in the rtl directory: a full featured
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// UART, and a LITE UART that only handles 8N1 -- no break sending, break
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// detection, parity error detection, etc. If we set USE_LITE_UART here, those
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// simplified UART modules will be used.
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//
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// `define USE_LITE_UART
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//
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//
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module helloworld(i_clk,
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module helloworld(i_clk,
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`ifndef OPT_STANDALONE
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`ifndef OPT_STANDALONE
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i_setup,
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i_setup,
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`endif
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`endif
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o_uart_tx);
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o_uart_tx);
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input i_clk;
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input i_clk;
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output wire o_uart_tx;
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output wire o_uart_tx;
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// Here we set i_setup to something appropriate to create a 115200 Baud
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// Here we set i_setup to something appropriate to create a 115200 Baud
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// UART system from a 100MHz clock. This also sets us to an 8-bit data
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// UART system from a 100MHz clock. This also sets us to an 8-bit data
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// word, 1-stop bit, and no parity. This will be overwritten by
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// word, 1-stop bit, and no parity. This will be overwritten by
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// i_setup, but at least it gives us something to start with/from.
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// i_setup, but at least it gives us something to start with/from.
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parameter INITIAL_UART_SETUP = 31'd868;
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parameter INITIAL_UART_SETUP = 31'd868;
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// The i_setup wires are input when run under Verilator, but need to
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// The i_setup wires are input when run under Verilator, but need to
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// be set internally if this is going to run as a standalone top level
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// be set internally if this is going to run as a standalone top level
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// test configuration.
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// test configuration.
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`ifdef OPT_STANDALONE
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`ifdef OPT_STANDALONE
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wire [30:0] i_setup;
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wire [30:0] i_setup;
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assign i_setup = INITIAL_UART_SETUP;
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assign i_setup = INITIAL_UART_SETUP;
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`else
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`else
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input [30:0] i_setup;
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input [30:0] i_setup;
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`endif
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`endif
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reg pwr_reset;
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reg pwr_reset;
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initial pwr_reset = 1'b1;
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initial pwr_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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pwr_reset <= 1'b0;
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pwr_reset <= 1'b0;
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reg [7:0] message [0:15];
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reg [7:0] message [0:15];
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initial begin
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initial begin
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message[ 0] = "H";
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message[ 0] = "H";
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message[ 1] = "e";
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message[ 1] = "e";
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message[ 2] = "l";
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message[ 2] = "l";
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message[ 3] = "l";
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message[ 3] = "l";
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message[ 4] = "o";
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message[ 4] = "o";
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message[ 5] = ",";
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message[ 5] = ",";
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message[ 6] = " ";
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message[ 6] = " ";
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message[ 7] = "W";
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message[ 7] = "W";
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message[ 8] = "o";
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message[ 8] = "o";
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message[ 9] = "r";
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message[ 9] = "r";
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message[10] = "l";
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message[10] = "l";
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message[11] = "d";
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message[11] = "d";
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message[12] = "!";
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message[12] = "!";
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message[13] = " ";
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message[13] = " ";
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message[14] = "\r";
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message[14] = "\r";
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message[15] = "\n";
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message[15] = "\n";
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end
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end
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reg [27:0] counter;
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reg [27:0] counter;
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initial counter = 28'hffffff0;
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initial counter = 28'hffffff0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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counter <= counter + 1'b1;
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counter <= counter + 1'b1;
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wire tx_break, tx_busy;
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wire tx_break, tx_busy;
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reg tx_stb;
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reg tx_stb;
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reg [3:0] tx_index;
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reg [3:0] tx_index;
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reg [7:0] tx_data;
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reg [7:0] tx_data;
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assign tx_break = 1'b0;
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assign tx_break = 1'b0;
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initial tx_index = 4'h0;
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initial tx_index = 4'h0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((tx_stb)&&(!tx_busy))
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if ((tx_stb)&&(!tx_busy))
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tx_index <= tx_index + 1'b1;
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tx_index <= tx_index + 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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tx_data <= message[tx_index];
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tx_data <= message[tx_index];
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initial tx_stb = 1'b0;
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initial tx_stb = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (&counter)
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if (&counter)
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tx_stb <= 1'b1;
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tx_stb <= 1'b1;
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else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf))
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else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf))
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tx_stb <= 1'b0;
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tx_stb <= 1'b0;
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// Bypass any hardware flow control
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// Bypass any hardware flow control
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wire rts;
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wire cts_n;
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assign rts = 1'b1;
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assign cts_n = 1'b0;
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`ifdef USE_LITE_UART
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txuartlite
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#(24'd868)
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transmitter(i_clk, tx_stb, tx_data, o_uart_tx, tx_busy);
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`else
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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tx_stb, tx_data, rts, o_uart_tx, tx_busy);
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tx_stb, tx_data, cts_n, o_uart_tx, tx_busy);
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`endif
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endmodule
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endmodule
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