////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: speechfifo.v
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// Filename: speechfifo.v
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//
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//
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// Project: wbuart32, a full featured UART with simulator
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// Project: wbuart32, a full featured UART with simulator
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//
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//
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// Purpose: To test/demonstrate/prove the wishbone access to the FIFO'd
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// Purpose: To test/demonstrate/prove the wishbone access to the FIFO'd
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// UART via sending more information than the FIFO can hold,
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// UART via sending more information than the FIFO can hold,
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// and then verifying that this was the value received.
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// and then verifying that this was the value received.
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//
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//
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// To do this, we "borrow" a copy of Abraham Lincolns Gettysburg address,
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// To do this, we "borrow" a copy of Abraham Lincolns Gettysburg address,
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// make that the FIFO isn't large enough to hold it, and then try
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// make that the FIFO isn't large enough to hold it, and then try
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// to send this address every couple of minutes.
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// to send this address every couple of minutes.
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//
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//
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// With some minor modifications (discussed below), this RTL should be
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// With some minor modifications (discussed below), this RTL should be
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// able to be run as a top-level testing file, requiring only that the
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// able to be run as a top-level testing file, requiring only that the
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// clock and the transmit UART pins be working.
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// clock and the transmit UART pins be working.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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// One issue with the design is how to set the values of the setup register.
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// One issue with the design is how to set the values of the setup register.
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// (*This is a comment, not a verilator attribute ... ) Verilator needs to
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// (*This is a comment, not a verilator attribute ... ) Verilator needs to
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// know/set those values in order to work. However, this design can also be
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// know/set those values in order to work. However, this design can also be
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// used as a stand-alone top level configuration file. In this latter case,
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// used as a stand-alone top level configuration file. In this latter case,
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// the setup register needs to be set internal to the file. Here, we use
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// the setup register needs to be set internal to the file. Here, we use
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// OPT_STANDALONE to distinguish between the two. If set, the file runs under
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// OPT_STANDALONE to distinguish between the two. If set, the file runs under
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// (* Another comment still ...) Verilator and we need to get i_setup from the
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// (* Another comment still ...) Verilator and we need to get i_setup from the
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// external environment. If not, it must be set internally.
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// external environment. If not, it must be set internally.
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//
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//
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`ifndef VERILATOR
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`ifndef VERILATOR
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`define OPT_STANDALONE
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`define OPT_STANDALONE
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`endif
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`endif
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//
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//
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module speechfifo(i_clk,
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module speechfifo(i_clk,
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`ifndef OPT_STANDALONE
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`ifndef OPT_STANDALONE
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i_setup,
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i_setup,
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`endif
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`endif
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o_uart_tx);
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o_uart_tx);
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input i_clk;
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input i_clk;
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output wire o_uart_tx;
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output wire o_uart_tx;
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|
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// Here we set i_setup to something appropriate to create a 115200 Baud
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// Here we set i_setup to something appropriate to create a 115200 Baud
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// UART system from a 100MHz clock. This also sets us to an 8-bit data
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// UART system from a 100MHz clock. This also sets us to an 8-bit data
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// word, 1-stop bit, and no parity. This will be overwritten by
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// word, 1-stop bit, and no parity. This will be overwritten by
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// i_setup, but at least it gives us something to start with/from.
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// i_setup, but at least it gives us something to start with/from.
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parameter INITIAL_UART_SETUP = 31'd868;
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parameter INITIAL_UART_SETUP = 31'd868;
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|
|
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// Let's set our message length, in case we ever wish to change it in
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// the future
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localparam MSGLEN=2203;
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|
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// The i_setup wires are input when run under Verilator, but need to
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// The i_setup wires are input when run under Verilator, but need to
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// be set internally if this is going to run as a standalone top level
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// be set internally if this is going to run as a standalone top level
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// test configuration.
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// test configuration.
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`ifdef OPT_STANDALONE
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`ifdef OPT_STANDALONE
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wire [30:0] i_setup;
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wire [30:0] i_setup;
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assign i_setup = INITIAL_UART_SETUP;
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assign i_setup = INITIAL_UART_SETUP;
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`else
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`else
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input [30:0] i_setup;
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input [30:0] i_setup;
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`endif
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`endif
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reg restart;
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reg restart;
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reg wb_stb;
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reg wb_stb;
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reg [1:0] wb_addr;
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reg [1:0] wb_addr;
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reg [31:0] wb_data;
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reg [31:0] wb_data;
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|
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wire uart_stall, uart_ack;
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wire uart_stall;
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// We aren't using the receive interrupts, or the received data, or the
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// ready to send line, so we'll just mark them all here as ignored.
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/* verilator lint_off UNUSED */
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wire uart_ack, tx_int;
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wire [31:0] uart_data;
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wire [31:0] uart_data;
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wire ignored_rx_int, ignored_rxfifo_int;
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wire rts_n_ignored;
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/* verilator lint_on UNUSED */
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wire tx_int, txfifo_int;
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/* verilator lint_on UNUSED */
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wire txfifo_int;
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// The next four lines create a strobe signal that is true on the first
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// The next four lines create a strobe signal that is true on the first
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// clock, but never after. This makes for a decent power-on reset
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// clock, but never after. This makes for a decent power-on reset
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// signal.
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// signal.
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reg pwr_reset;
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reg pwr_reset;
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initial pwr_reset = 1'b1;
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initial pwr_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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pwr_reset <= 1'b0;
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pwr_reset <= 1'b0;
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|
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// The message we wish to transmit is kept in "message". It needs to be
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// The message we wish to transmit is kept in "message". It needs to be
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// set initially. Do so here.
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// set initially. Do so here.
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//
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//
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// Since the message has fewer than 2048 elements in it, we preset every
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// Since the message has fewer than 2048 elements in it, we preset every
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// element to a space so that if (for some reason) we broadcast past the
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// element to a space so that if (for some reason) we broadcast past the
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// end of our message, we'll at least be sending something useful.
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// end of our message, we'll at least be sending something useful.
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integer i;
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integer i;
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reg [7:0] message [0:2047];
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reg [7:0] message [0:4095];
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initial begin
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initial begin
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// xx Verilator needs this file to be in the directory the file
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// xx Verilator needs this file to be in the directory the file
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// is run from. For that reason, the project builds, makes,
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// is run from. For that reason, the project builds, makes,
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// and keeps speech.hex in bench/cpp.
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// and keeps speech.hex in bench/cpp.
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//
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//
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// Vivado, however, wants speech.hex to be in a project file
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// Vivado, however, wants speech.hex to be in a project file
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// directory, such as bench/verilog. For that reason, the
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// directory, such as bench/verilog. For that reason, the
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// build function in bench/cpp also copies speech.hex to the
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// build function in bench/cpp also copies speech.hex to the
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// bench/verilog directory. You may need to make certain the
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// bench/verilog directory. You may need to make certain the
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// file is both built, and copied into a directory where your
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// file is both built, and copied into a directory where your
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// synthesis tool can find it.
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// synthesis tool can find it.
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//
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//
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$readmemh("speech.hex", message);
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$readmemh("speech.hex", message);
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for(i=1481; i<2048; i=i+1)
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for(i=MSGLEN; i<4095; i=i+1)
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message[i] = 8'h20;
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message[i] = 8'h20;
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//
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//
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// The problem with the above approach is Xilinx's ISE program.
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// The problem with the above approach is Xilinx's ISE program.
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// It's broken. It can't handle HEX files well (at all?) and
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// It's broken. It can't handle HEX files well (at all?) and
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// has more problems with HEX's defining ROM's. For that
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// has more problems with HEX's defining ROM's. For that
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// reason, the mkspeech program can be tuned to create an
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// reason, the mkspeech program can be tuned to create an
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// include file, speech.inc. We include that program here.
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// include file, speech.inc. We include that program here.
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// It is rather ugly, though, and not a very elegant solution,
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// It is rather ugly, though, and not a very elegant solution,
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// since it walks through every value in our speech, byte by
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// since it walks through every value in our speech, byte by
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// byte, with an initial line for each byte declaring what it
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// byte, with an initial line for each byte declaring what it
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// is to be.
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// is to be.
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//
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//
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// If you (need to) use this route, comment out both the
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// If you (need to) use this route, comment out both the
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// readmemh, the for loop, and the message[i] = 8'h20 lines
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// readmemh, the for loop, and the message[i] = 8'h20 lines
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// above and uncomment the include line below.
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// above and uncomment the include line below.
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//
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//
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// `include "speech.inc"
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// `include "speech.inc"
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end
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end
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|
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// Let's keep track of time, and send our message over and over again.
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// Let's keep track of time, and send our message over and over again.
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// To do this, we'll keep track of a restart counter. When this counter
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// To do this, we'll keep track of a restart counter. When this counter
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// rolls over, we restart our message.
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// rolls over, we restart our message.
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reg [30:0] restart_counter;
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reg [30:0] restart_counter;
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// Since we want to start our message just a couple clocks after power
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// Since we want to start our message just a couple clocks after power
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// up, we'll set the reset counter just a couple clocks shy of a roll
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// up, we'll set the reset counter just a couple clocks shy of a roll
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// over.
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// over.
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initial restart_counter = -31'd16;
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initial restart_counter = -31'd16;
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always @(posedge i_clk)
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always @(posedge i_clk)
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restart_counter <= restart_counter+1'b1;
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restart_counter <= restart_counter+1'b1;
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|
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// Ok, now that we have a counter that tells us when to start over,
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// Ok, now that we have a counter that tells us when to start over,
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// let's build a set of signals that we can use to get things started
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// let's build a set of signals that we can use to get things started
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// again. This will be the restart signal. On this signal, we just
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// again. This will be the restart signal. On this signal, we just
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// restart everything.
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// restart everything.
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initial restart = 0;
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initial restart = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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restart <= (restart_counter == 0);
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restart <= (restart_counter == 0);
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|
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// Our message index. This is the address of the character we wish to
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// Our message index. This is the address of the character we wish to
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// transmit next. Note, there's a clock delay between setting this
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// transmit next. Note, there's a clock delay between setting this
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// index and when the wb_data is valid. Hence, we set the index on
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// index and when the wb_data is valid. Hence, we set the index on
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// restart[0] to zero.
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// restart[0] to zero.
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reg [10:0] msg_index;
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reg [11:0] msg_index;
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initial msg_index = 11'd2040;
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initial msg_index = 12'h000 - 12'h8;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (restart)
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if (restart)
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msg_index <= 0;
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msg_index <= 0;
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else if ((wb_stb)&&(!uart_stall))
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else if ((wb_stb)&&(!uart_stall))
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// We only advance the index if a port operation on the
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// We only advance the index if a port operation on the
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// wbuart has taken place. That's what the
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// wbuart has taken place. That's what the
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// (wb_stb)&&(!uart_stall) is about. (wb_stb) is the
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// (wb_stb)&&(!uart_stall) is about. (wb_stb) is the
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// request for a transaction on the bus, uart_stall
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// request for a transaction on the bus, uart_stall
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// tells us to wait 'cause the peripheral isn't ready.
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// tells us to wait 'cause the peripheral isn't ready.
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// In our case, it's always ready, uart_stall == 0, but
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// In our case, it's always ready, uart_stall == 0, but
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// we keep/maintain this logic for good form.
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// we keep/maintain this logic for good form.
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//
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//
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// Note also, we only advance when restart[0] is zero.
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// Note also, we only advance when restart[0] is zero.
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// This keeps us from advancing prior to the setup
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// This keeps us from advancing prior to the setup
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// word.
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// word.
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msg_index <= msg_index + 1'b1;
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msg_index <= msg_index + 1'b1;
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end
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end
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|
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// What data will we be sending to the port?
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// What data will we be sending to the port?
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (restart)
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if (restart)
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// The first thing we do is set the baud rate, and
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// The first thing we do is set the baud rate, and
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// serial port configuration parameters. Ideally,
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// serial port configuration parameters. Ideally,
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// we'd only set this once. But rather than complicate
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// we'd only set this once. But rather than complicate
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// the logic, we set it everytime we start over.
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// the logic, we set it everytime we start over.
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wb_data <= { 1'b0, i_setup };
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wb_data <= { 1'b0, i_setup };
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else if ((wb_stb)&&(!uart_stall))
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else if ((wb_stb)&&(!uart_stall))
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// Then, if the last thing was received over the bus,
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// Then, if the last thing was received over the bus,
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// we move to the next data item.
|
// we move to the next data item.
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wb_data <= { 24'h00, message[msg_index] };
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wb_data <= { 24'h00, message[msg_index] };
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|
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// We send our first value to the SETUP address (all zeros), all other
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// We send our first value to the SETUP address (all zeros), all other
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// values we send to the transmitters address. We should really be
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// values we send to the transmitters address. We should really be
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// double checking that stall remains low, but its not required here.
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// double checking that stall remains low, but its not required here.
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (restart)
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if (restart)
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wb_addr <= 2'b00;
|
wb_addr <= 2'b00;
|
else // if (!uart_stall)??
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else // if (!uart_stall)??
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wb_addr <= 2'b11;
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wb_addr <= 2'b11;
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|
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// Knowing when to stop sending the speech is important, but depends
|
// Knowing when to stop sending the speech is important, but depends
|
// upon an 11 bit comparison. Since FPGA logic is best measured by the
|
// upon an 11 bit comparison. Since FPGA logic is best measured by the
|
// number of inputs to an always block, we pull those 11-bits out of
|
// number of inputs to an always block, we pull those 11-bits out of
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// the always block for wb_stb, and place them here on the clock prior.
|
// the always block for wb_stb, and place them here on the clock prior.
|
// If end_of_message is true, then we need to stop transmitting, and
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// If end_of_message is true, then we need to stop transmitting, and
|
// wait for the next (restart) to get us started again. We set that
|
// wait for the next (restart) to get us started again. We set that
|
// flag hee.
|
// flag hee.
|
reg end_of_message;
|
reg end_of_message;
|
initial end_of_message = 1'b1;
|
initial end_of_message = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (restart)
|
if (restart)
|
end_of_message <= 1'b0;
|
end_of_message <= 1'b0;
|
else
|
else
|
end_of_message <= (msg_index >= 1481);
|
end_of_message <= (msg_index >= MSGLEN);
|
|
|
// The wb_stb signal indicates that we wish to write, using the wishbone
|
// The wb_stb signal indicates that we wish to write, using the wishbone
|
// to our peripheral. We have two separate types of writes. First,
|
// to our peripheral. We have two separate types of writes. First,
|
// we wish to write our setup. Then we want to drop STB and write
|
// we wish to write our setup. Then we want to drop STB and write
|
// our data. Once we've filled half of the FIFO, we wait for the FIFO
|
// our data. Once we've filled half of the FIFO, we wait for the FIFO
|
// to empty before issuing a STB again and then fill up half the FIFO
|
// to empty before issuing a STB again and then fill up half the FIFO
|
// again.
|
// again.
|
initial wb_stb = 1'b0;
|
initial wb_stb = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (restart)
|
if (restart)
|
// Start sending to the UART on a reset. The first
|
// Start sending to the UART on a reset. The first
|
// thing we'll send will be the configuration, but
|
// thing we'll send will be the configuration, but
|
// that's done elsewhere. This just starts up the
|
// that's done elsewhere. This just starts up the
|
// writes to the peripheral wbuart.
|
// writes to the peripheral wbuart.
|
wb_stb <= 1'b1;
|
wb_stb <= 1'b1;
|
else if (end_of_message)
|
else if (end_of_message)
|
// Stop transmitting when we get to the end of our
|
// Stop transmitting when we get to the end of our
|
// message.
|
// message.
|
wb_stb <= 1'b0;
|
wb_stb <= 1'b0;
|
else if (txfifo_int)
|
else if (txfifo_int)
|
// If the FIFO is less than half full, then write to
|
// If the FIFO is less than half full, then write to
|
// it.
|
// it.
|
wb_stb <= 1'b1;
|
wb_stb <= 1'b1;
|
else
|
else
|
// But once the FIFO gets to half full, stop.
|
// But once the FIFO gets to half full, stop.
|
wb_stb <= 1'b0;
|
wb_stb <= 1'b0;
|
|
|
// We aren't using the receive interrupts, so we'll just mark them
|
|
// here as ignored.
|
|
wire ignored_rx_int, ignored_rxfifo_int;
|
|
|
|
// The WBUART can handle hardware flow control signals. This test,
|
// The WBUART can handle hardware flow control signals. This test,
|
// however, cannot. The reason? Simply just to keep things simple.
|
// however, cannot. The reason? Simply just to keep things simple.
|
// If you want to add hardware flow control to your design, simply
|
// If you want to add hardware flow control to your design, simply
|
// make rts an input to this module.
|
// make rts an input to this module.
|
//
|
//
|
// Since this is an output only module demonstrator, what would be the
|
// Since this is an output only module demonstrator, what would be the
|
// cts output is unused.
|
// cts output is unused.
|
wire cts_n, rts_n_ignored;
|
wire cts_n;
|
assign cts_n = 1'b0;
|
assign cts_n = 1'b0;
|
|
|
// Finally--the unit under test--now that we've set up all the wires
|
// Finally--the unit under test--now that we've set up all the wires
|
// to run/test it.
|
// to run/test it.
|
wbuart #(INITIAL_UART_SETUP)
|
wbuart #(INITIAL_UART_SETUP)
|
wbuarti(i_clk, pwr_reset,
|
wbuarti(i_clk, pwr_reset,
|
wb_stb, wb_stb, 1'b1, wb_addr, wb_data,
|
wb_stb, wb_stb, 1'b1, wb_addr, wb_data,
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uart_ack, uart_stall, uart_data,
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uart_ack, uart_stall, uart_data,
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1'b1, o_uart_tx, cts_n, rts_n_ignored,
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1'b1, o_uart_tx, cts_n, rts_n_ignored,
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ignored_rx_int, tx_int,
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ignored_rx_int, tx_int,
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ignored_rxfifo_int, txfifo_int);
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ignored_rxfifo_int, txfifo_int);
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|
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endmodule
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endmodule
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