////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: ufifo.v
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// Filename: ufifo.v
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//
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//
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// Project: wbuart32, a full featured UART with simulator
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// Project: wbuart32, a full featured UART with simulator
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//
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//
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// Purpose:
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// Purpose: A synchronous data FIFO, designed for supporting the Wishbone
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// UART. Particular features include the ability to read and
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// write on the same clock, while maintaining the correct output FIFO
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// parameters. Two versions of the FIFO exist within this file, separated
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// by the RXFIFO parameter's value. One, where RXFIFO = 1, produces status
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// values appropriate for reading and checking a read FIFO from logic,
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// whereas the RXFIFO = 0 applies to writing to the FIFO from bus logic
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// and reading it automatically any time the transmit UART is idle.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`default_nettype none
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`default_nettype none
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//
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//
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module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err);
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module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err);
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parameter BW=8; // Byte/data width
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parameter BW=8; // Byte/data width
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parameter [3:0] LGFLEN=4;
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parameter [3:0] LGFLEN=4;
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parameter RXFIFO=1'b0;
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parameter RXFIFO=1'b0;
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input wire i_clk, i_rst;
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input wire i_clk, i_rst;
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input wire i_wr;
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input wire i_wr;
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input wire [(BW-1):0] i_data;
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input wire [(BW-1):0] i_data;
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output wire o_empty_n; // True if something is in FIFO
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output wire o_empty_n; // True if something is in FIFO
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input wire i_rd;
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input wire i_rd;
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output wire [(BW-1):0] o_data;
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output wire [(BW-1):0] o_data;
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output wire [15:0] o_status;
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output wire [15:0] o_status;
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output wire o_err;
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output wire o_err;
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localparam FLEN=(1<<LGFLEN);
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localparam FLEN=(1<<LGFLEN);
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reg [(BW-1):0] fifo[0:(FLEN-1)];
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reg [(BW-1):0] fifo[0:(FLEN-1)];
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reg [(LGFLEN-1):0] r_first, r_last, r_next;
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reg [(LGFLEN-1):0] r_first, r_last, r_next;
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wire [(LGFLEN-1):0] w_first_plus_one, w_first_plus_two,
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wire [(LGFLEN-1):0] w_first_plus_one, w_first_plus_two,
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w_last_plus_one;
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w_last_plus_one;
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assign w_first_plus_two = r_first + {{(LGFLEN-2){1'b0}},2'b10};
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assign w_first_plus_two = r_first + {{(LGFLEN-2){1'b0}},2'b10};
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assign w_first_plus_one = r_first + {{(LGFLEN-1){1'b0}},1'b1};
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assign w_first_plus_one = r_first + {{(LGFLEN-1){1'b0}},1'b1};
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assign w_last_plus_one = r_next; // r_last + 1'b1;
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assign w_last_plus_one = r_next; // r_last + 1'b1;
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reg will_overflow;
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reg will_overflow;
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initial will_overflow = 1'b0;
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initial will_overflow = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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will_overflow <= 1'b0;
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will_overflow <= 1'b0;
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else if (i_rd)
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else if (i_rd)
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will_overflow <= (will_overflow)&&(i_wr);
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will_overflow <= (will_overflow)&&(i_wr);
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else if (i_wr)
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else if (i_wr)
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will_overflow <= (will_overflow)||(w_first_plus_two == r_last);
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will_overflow <= (will_overflow)||(w_first_plus_two == r_last);
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else if (w_first_plus_one == r_last)
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else if (w_first_plus_one == r_last)
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will_overflow <= 1'b1;
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will_overflow <= 1'b1;
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// Write
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// Write
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reg r_ovfl;
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reg r_ovfl;
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initial r_first = 0;
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initial r_first = 0;
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initial r_ovfl = 0;
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initial r_ovfl = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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r_ovfl <= 1'b0;
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r_ovfl <= 1'b0;
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r_first <= { (LGFLEN){1'b0} };
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r_first <= { (LGFLEN){1'b0} };
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end else if (i_wr)
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end else if (i_wr)
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begin // Cowardly refuse to overflow
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begin // Cowardly refuse to overflow
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if ((i_rd)||(!will_overflow)) // (r_first+1 != r_last)
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if ((i_rd)||(!will_overflow)) // (r_first+1 != r_last)
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r_first <= w_first_plus_one;
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r_first <= w_first_plus_one;
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else
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else
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r_ovfl <= 1'b1;
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r_ovfl <= 1'b1;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wr) // Write our new value regardless--on overflow or not
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if (i_wr) // Write our new value regardless--on overflow or not
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fifo[r_first] <= i_data;
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fifo[r_first] <= i_data;
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// Reads
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// Reads
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// Following a read, the next sample will be available on the
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// Following a read, the next sample will be available on the
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// next clock
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// next clock
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// Clock ReadCMD ReadAddr Output
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// Clock ReadCMD ReadAddr Output
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// 0 0 0 fifo[0]
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// 0 0 0 fifo[0]
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// 1 1 0 fifo[0]
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// 1 1 0 fifo[0]
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// 2 0 1 fifo[1]
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// 2 0 1 fifo[1]
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// 3 0 1 fifo[1]
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// 3 0 1 fifo[1]
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// 4 1 1 fifo[1]
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// 4 1 1 fifo[1]
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// 5 1 2 fifo[2]
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// 5 1 2 fifo[2]
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// 6 0 3 fifo[3]
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// 6 0 3 fifo[3]
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// 7 0 3 fifo[3]
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// 7 0 3 fifo[3]
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reg will_underflow;
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reg will_underflow;
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initial will_underflow = 1'b1;
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initial will_underflow = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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will_underflow <= 1'b1;
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will_underflow <= 1'b1;
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else if (i_wr)
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else if (i_wr)
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will_underflow <= (will_underflow)&&(i_rd);
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will_underflow <= 1'b0;
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else if (i_rd)
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else if (i_rd)
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will_underflow <= (will_underflow)||(w_last_plus_one == r_first);
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will_underflow <= (will_underflow)||(w_last_plus_one == r_first);
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else
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else
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will_underflow <= (r_last == r_first);
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will_underflow <= (r_last == r_first);
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//
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//
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// Don't report FIFO underflow errors. These'll be caught elsewhere
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// Don't report FIFO underflow errors. These'll be caught elsewhere
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// in the system, and the logic below makes it hard to reset them.
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// in the system, and the logic below makes it hard to reset them.
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// We'll still report FIFO overflow, however.
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// We'll still report FIFO overflow, however.
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//
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//
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// reg r_unfl;
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// reg r_unfl;
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// initial r_unfl = 1'b0;
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// initial r_unfl = 1'b0;
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initial r_last = 0;
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initial r_last = 0;
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initial r_next = { {(LGFLEN-1){1'b0}}, 1'b1 };
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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r_last <= 0;
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r_last <= 0;
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r_next <= { {(LGFLEN-1){1'b0}}, 1'b1 };
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r_next <= { {(LGFLEN-1){1'b0}}, 1'b1 };
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// r_unfl <= 1'b0;
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// r_unfl <= 1'b0;
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end else if (i_rd)
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end else if (i_rd)
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begin
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begin
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if ((i_wr)||(!will_underflow)) // (r_first != r_last)
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if (!will_underflow) // (r_first != r_last)
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begin
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begin
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r_last <= r_next;
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r_last <= r_next;
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r_next <= r_last +{{(LGFLEN-2){1'b0}},2'b10};
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r_next <= r_last +{{(LGFLEN-2){1'b0}},2'b10};
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// Last chases first
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// Last chases first
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// Need to be prepared for a possible two
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// Need to be prepared for a possible two
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// reads in quick succession
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// reads in quick succession
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// o_data <= fifo[r_last+1];
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// o_data <= fifo[r_last+1];
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end
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end
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// else r_unfl <= 1'b1;
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// else r_unfl <= 1'b1;
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end
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end
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reg [(BW-1):0] fifo_here, fifo_next, r_data;
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reg [(BW-1):0] fifo_here, fifo_next, r_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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fifo_here <= fifo[r_last];
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fifo_here <= fifo[r_last];
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always @(posedge i_clk)
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always @(posedge i_clk)
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fifo_next <= fifo[r_next];
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fifo_next <= fifo[r_next];
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_data <= i_data;
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r_data <= i_data;
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reg [1:0] osrc;
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reg [1:0] osrc;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (will_underflow)
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if (will_underflow)
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// o_data <= i_data;
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// o_data <= i_data;
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osrc <= 2'b00;
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osrc <= 2'b00;
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else if ((i_rd)&&(r_first == w_last_plus_one))
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else if ((i_rd)&&(r_first == w_last_plus_one))
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osrc <= 2'b01;
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osrc <= 2'b01;
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else if (i_rd)
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else if (i_rd)
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osrc <= 2'b11;
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osrc <= 2'b11;
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else
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else
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osrc <= 2'b10;
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osrc <= 2'b10;
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assign o_data = (osrc[1]) ? ((osrc[0])?fifo_next:fifo_here) : r_data;
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assign o_data = (osrc[1]) ? ((osrc[0])?fifo_next:fifo_here) : r_data;
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// wire [(LGFLEN-1):0] current_fill;
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// wire [(LGFLEN-1):0] current_fill;
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// assign current_fill = (r_first-r_last);
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// assign current_fill = (r_first-r_last);
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reg r_empty_n;
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reg r_empty_n;
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initial r_empty_n = 1'b0;
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initial r_empty_n = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_empty_n <= 1'b0;
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r_empty_n <= 1'b0;
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else casez({i_wr, i_rd, will_underflow})
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else casez({i_wr, i_rd, will_underflow})
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3'b00?: r_empty_n <= (r_first != r_last);
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3'b00?: r_empty_n <= (r_first != r_last);
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3'b11?: r_empty_n <= (r_first != r_last);
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3'b10?: r_empty_n <= 1'b1;
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3'b010: r_empty_n <= (r_first != w_last_plus_one);
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3'b010: r_empty_n <= (r_first != w_last_plus_one);
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// 3'b001: r_empty_n <= 1'b0;
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3'b10?: r_empty_n <= 1'b1;
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3'b110: r_empty_n <= (r_first != r_last);
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3'b111: r_empty_n <= 1'b1;
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default: begin end
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default: begin end
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endcase
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endcase
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wire w_full_n;
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wire w_full_n;
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assign w_full_n = will_overflow;
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assign w_full_n = will_overflow;
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//
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//
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// If this is a receive FIFO, the FIFO count that matters is the number
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// If this is a receive FIFO, the FIFO count that matters is the number
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// of values yet to be read. If instead this is a transmit FIFO, then
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// of values yet to be read. If instead this is a transmit FIFO, then
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// the FIFO count that matters is the number of empty positions that
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// the FIFO count that matters is the number of empty positions that
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// can still be filled before the FIFO is full.
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// can still be filled before the FIFO is full.
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//
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//
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// Adjust for these differences here.
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// Adjust for these differences here.
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reg [(LGFLEN-1):0] r_fill;
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reg [(LGFLEN-1):0] r_fill;
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generate
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if (RXFIFO != 0)
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initial r_fill = 0;
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initial r_fill = 0;
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else
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initial r_fill = -1;
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endgenerate
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (RXFIFO!=0) begin
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if (RXFIFO!=0) begin
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// Calculate the number of elements in our FIFO
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// Calculate the number of elements in our FIFO
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//
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//
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// Although used for receive, this is actually the more
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// Although used for receive, this is actually the more
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// generic answer--should you wish to use the FIFO in
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// generic answer--should you wish to use the FIFO in
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// another context.
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// another context.
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if (i_rst)
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if (i_rst)
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r_fill <= 0;
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r_fill <= 0;
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else case({(i_wr)&&(!will_overflow), (i_rd)&&(!will_underflow)})
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else casez({(i_wr), (!will_overflow), (i_rd)&&(!will_underflow)})
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2'b01: r_fill <= r_first - r_next;
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3'b0?1: r_fill <= r_first - r_next;
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2'b10: r_fill <= r_first - r_last + 1'b1;
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3'b110: r_fill <= r_first - r_last + 1'b1;
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3'b1?1: r_fill <= r_first - r_last;
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default: r_fill <= r_first - r_last;
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default: r_fill <= r_first - r_last;
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endcase
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endcase
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end else begin
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end else begin
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// Calculate the number of elements that are empty and
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// Calculate the number of elements that are empty and
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// can be filled within our FIFO. Hence, this is really
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// can be filled within our FIFO. Hence, this is really
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// not the fill, but (SIZE-1)-fill.
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// not the fill, but (SIZE-1)-fill.
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if (i_rst)
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if (i_rst)
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r_fill <= { (LGFLEN){1'b1} };
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r_fill <= { (LGFLEN){1'b1} };
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else case({i_wr, i_rd})
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else casez({i_wr, (!will_overflow), (i_rd)&&(!will_underflow)})
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2'b01: r_fill <= r_last - r_first;
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3'b0?1: r_fill <= r_fill + 1'b1;
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2'b10: r_fill <= r_last - w_first_plus_two;
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3'b110: r_fill <= r_fill - 1'b1;
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default: r_fill <= r_last - w_first_plus_one;
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default: r_fill <= r_fill;
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endcase
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endcase
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end
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end
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|
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// We don't report underflow errors. These
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// We don't report underflow errors. These
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assign o_err = (r_ovfl); // || (r_unfl);
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assign o_err = (r_ovfl); // || (r_unfl);
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|
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wire [3:0] lglen;
|
wire [3:0] lglen;
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assign lglen = LGFLEN;
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assign lglen = LGFLEN;
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|
|
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wire w_half_full;
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wire [9:0] w_fill;
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wire [9:0] w_fill;
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assign w_fill[(LGFLEN-1):0] = r_fill;
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assign w_fill[(LGFLEN-1):0] = r_fill;
|
generate if (LGFLEN < 10)
|
generate if (LGFLEN < 10)
|
assign w_fill[9:(LGFLEN)] = 0;
|
assign w_fill[9:(LGFLEN)] = 0;
|
endgenerate
|
endgenerate
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|
|
wire w_half_full;
|
|
assign w_half_full = r_fill[(LGFLEN-1)];
|
assign w_half_full = r_fill[(LGFLEN-1)];
|
|
|
assign o_status = {
|
assign o_status = {
|
// Our status includes a 4'bit nibble telling anyone reading
|
// Our status includes a 4'bit nibble telling anyone reading
|
// this the size of our FIFO. The size is then given by
|
// this the size of our FIFO. The size is then given by
|
// 2^(this value). Hence a 4'h4 in this position means that the
|
// 2^(this value). Hence a 4'h4 in this position means that the
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// FIFO has 2^4 or 16 values within it.
|
// FIFO has 2^4 or 16 values within it.
|
lglen,
|
lglen,
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// The FIFO fill--for a receive FIFO the number of elements
|
// The FIFO fill--for a receive FIFO the number of elements
|
// left to be read, and for a transmit FIFO the number of
|
// left to be read, and for a transmit FIFO the number of
|
// empty elements within the FIFO that can yet be filled.
|
// empty elements within the FIFO that can yet be filled.
|
w_fill,
|
w_fill,
|
// A '1' here means a half FIFO length can be read (receive
|
// A '1' here means a half FIFO length can be read (receive
|
// FIFO) or written to (not a receive FIFO).
|
// FIFO) or written to (not a receive FIFO).
|
// receive FIFO), or be written to (if it isn't).
|
// receive FIFO), or be written to (if it isn't).
|
(RXFIFO!=0)?w_half_full:w_half_full,
|
(RXFIFO!=0)?w_half_full:w_half_full,
|
// A '1' here means the FIFO can be read from (if it is a
|
// A '1' here means the FIFO can be read from (if it is a
|
// receive FIFO), or be written to (if it isn't).
|
// receive FIFO), or be written to (if it isn't).
|
(RXFIFO!=0)?r_empty_n:w_full_n
|
(RXFIFO!=0)?r_empty_n:w_full_n
|
};
|
};
|
|
|
assign o_empty_n = r_empty_n;
|
assign o_empty_n = r_empty_n;
|
|
|
|
//
|
|
//
|
|
//
|
|
// FORMAL METHODS
|
|
//
|
|
//
|
|
//
|
|
`ifdef FORMAL
|
|
|
|
`ifdef UFIFO
|
|
`define ASSUME assume
|
|
`else
|
|
`define ASSUME assert
|
|
`endif
|
|
|
|
//
|
|
// Assumptions about our input(s)
|
|
//
|
|
//
|
|
reg f_past_valid, f_last_clk;
|
|
|
|
initial restrict(i_rst);
|
|
|
|
always @($global_clock)
|
|
begin
|
|
restrict(i_clk == !f_last_clk);
|
|
f_last_clk <= i_clk;
|
|
if (!$rose(i_clk))
|
|
begin
|
|
`ASSUME($stable(i_rst));
|
|
`ASSUME($stable(i_wr));
|
|
`ASSUME($stable(i_data));
|
|
`ASSUME($stable(i_rd));
|
|
end
|
|
end
|
|
|
|
//
|
|
// Underflows are a very real possibility, should the user wish to
|
|
// read from this FIFO while it is empty. Our parent module will need
|
|
// to deal with this.
|
|
//
|
|
// always @(posedge i_clk)
|
|
// `ASSUME((!will_underflow)||(!i_rd)||(i_rst));
|
|
//
|
|
// Assertions about our outputs
|
|
//
|
|
//
|
|
|
|
initial f_past_valid = 1'b0;
|
|
always @(posedge i_clk)
|
|
f_past_valid <= 1'b1;
|
|
|
|
wire [(LGFLEN-1):0] f_fill, f_next, f_empty;
|
|
assign f_fill = r_first - r_last;
|
|
assign f_empty = {(LGFLEN){1'b1}} -f_fill;
|
|
assign f_next = r_last + 1'b1;
|
|
always @(posedge i_clk)
|
|
begin
|
|
if (RXFIFO)
|
|
assert(f_fill == r_fill);
|
|
else
|
|
assert(f_empty== r_fill);
|
|
if (f_fill == 0)
|
|
begin
|
|
assert(will_underflow);
|
|
assert(!o_empty_n);
|
|
end else begin
|
|
assert(!will_underflow);
|
|
assert(o_empty_n);
|
|
end
|
|
|
|
if (f_fill == {(LGFLEN){1'b1}})
|
|
assert(will_overflow);
|
|
else
|
|
assert(!will_overflow);
|
|
|
|
assert(r_next == f_next);
|
|
end
|
|
|
|
always @(posedge i_clk)
|
|
if (f_past_valid)
|
|
begin
|
|
if ($past(i_rst))
|
|
assert(!o_err);
|
|
else begin
|
|
// No underflow detection in this core
|
|
//
|
|
// if (($past(i_rd))&&($past(r_fill == 0)))
|
|
// assert(o_err);
|
|
//
|
|
// We do, though, have overflow detection
|
|
if (($past(i_wr))&&(!$past(i_rd))
|
|
&&($past(will_overflow)))
|
|
assert(o_err);
|
|
end
|
|
end
|
|
|
|
`endif
|
endmodule
|
endmodule
|
|
|
