////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: ufifo.v
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// Filename: ufifo.v
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//
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//
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// Project: wbuart32, a full featured UART with simulator
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// Project: wbuart32, a full featured UART with simulator
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module ufifo(i_clk, i_rst, i_wr, i_data, i_rd, o_data,
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module ufifo(i_clk, i_rst, i_wr, i_data, i_rd, o_data,
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o_empty_n, o_half_full, o_status, o_err);
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o_empty_n, o_half_full, o_status, o_err);
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parameter BW=8, LGFLEN=4;
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parameter BW=8, LGFLEN=4;
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_wr;
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input i_wr;
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input [(BW-1):0] i_data;
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input [(BW-1):0] i_data;
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input i_rd;
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input i_rd;
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output wire [(BW-1):0] o_data;
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output wire [(BW-1):0] o_data;
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output reg o_empty_n;
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output reg o_empty_n;
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output wire o_half_full;
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output wire o_half_full;
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output wire [15:0] o_status;
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output wire [15:0] o_status;
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output wire o_err;
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output wire o_err;
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localparam FLEN=(1<<LGFLEN);
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localparam FLEN=(1<<LGFLEN);
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reg [(BW-1):0] fifo[0:(FLEN-1)];
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reg [(BW-1):0] fifo[0:(FLEN-1)];
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reg [(LGFLEN-1):0] r_first, r_last;
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reg [(LGFLEN-1):0] r_first, r_last, r_next;
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wire [(LGFLEN-1):0] w_first_plus_one, w_first_plus_two,
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wire [(LGFLEN-1):0] w_first_plus_one, w_first_plus_two,
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w_last_plus_one;
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w_last_plus_one;
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assign w_first_plus_two = r_first + {{(LGFLEN-2){1'b0}},2'b10};
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assign w_first_plus_two = r_first + {{(LGFLEN-2){1'b0}},2'b10};
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assign w_first_plus_one = r_first + {{(LGFLEN-1){1'b0}},1'b1};
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assign w_first_plus_one = r_first + {{(LGFLEN-1){1'b0}},1'b1};
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assign w_last_plus_one = r_last + {{(LGFLEN-1){1'b0}},1'b1};
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assign w_last_plus_one = r_next; // r_last + 1'b1;
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reg will_overflow;
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reg will_overflow;
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initial will_overflow = 1'b0;
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initial will_overflow = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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will_overflow <= 1'b0;
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will_overflow <= 1'b0;
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else if (i_rd)
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else if (i_rd)
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will_overflow <= (will_overflow)&&(i_wr);
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will_overflow <= (will_overflow)&&(i_wr);
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else if (i_wr)
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else if (i_wr)
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will_overflow <= (w_first_plus_two == r_last);
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will_overflow <= (w_first_plus_two == r_last);
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else if (w_first_plus_one == r_last)
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else if (w_first_plus_one == r_last)
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will_overflow <= 1'b1;
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will_overflow <= 1'b1;
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// Write
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// Write
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reg r_ovfl;
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reg r_ovfl;
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initial r_first = 0;
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initial r_first = 0;
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initial r_ovfl = 0;
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initial r_ovfl = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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r_ovfl <= 1'b0;
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r_ovfl <= 1'b0;
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r_first <= { (LGFLEN){1'b0} };
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r_first <= { (LGFLEN){1'b0} };
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end else if (i_wr)
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end else if (i_wr)
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begin // Cowardly refuse to overflow
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begin // Cowardly refuse to overflow
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if ((i_rd)||(!will_overflow)) // (r_first+1 != r_last)
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if ((i_rd)||(!will_overflow)) // (r_first+1 != r_last)
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r_first <= w_first_plus_one;
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r_first <= w_first_plus_one;
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else
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else
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r_ovfl <= 1'b1;
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r_ovfl <= 1'b1;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wr) // Write our new value regardless--on overflow or not
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if (i_wr) // Write our new value regardless--on overflow or not
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fifo[r_first] <= i_data;
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fifo[r_first] <= i_data;
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// Reads
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// Reads
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// Following a read, the next sample will be available on the
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// Following a read, the next sample will be available on the
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// next clock
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// next clock
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// Clock ReadCMD ReadAddr Output
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// Clock ReadCMD ReadAddr Output
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// 0 0 0 fifo[0]
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// 0 0 0 fifo[0]
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// 1 1 0 fifo[0]
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// 1 1 0 fifo[0]
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// 2 0 1 fifo[1]
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// 2 0 1 fifo[1]
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// 3 0 1 fifo[1]
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// 3 0 1 fifo[1]
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// 4 1 1 fifo[1]
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// 4 1 1 fifo[1]
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// 5 1 2 fifo[2]
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// 5 1 2 fifo[2]
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// 6 0 3 fifo[3]
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// 6 0 3 fifo[3]
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// 7 0 3 fifo[3]
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// 7 0 3 fifo[3]
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reg will_underflow, r_unfl;
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reg will_underflow, r_unfl;
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initial will_underflow = 1'b1;
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initial will_underflow = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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will_underflow <= 1'b1;
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will_underflow <= 1'b1;
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else if (i_wr)
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else if (i_wr)
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will_underflow <= (will_underflow)&&(i_rd);
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will_underflow <= (will_underflow)&&(i_rd);
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else if (i_rd)
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else if (i_rd)
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will_underflow <= (w_last_plus_one == r_first);
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will_underflow <= (w_last_plus_one == r_first);
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else
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else
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will_underflow <= (r_last == r_first);
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will_underflow <= (r_last == r_first);
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initial r_unfl = 1'b0;
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initial r_unfl = 1'b0;
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initial r_last = 0;
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initial r_last = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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r_last <= { (LGFLEN){1'b0} };
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r_last <= 0;
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r_next <= { {(LGFLEN-1){1'b0}}, 1'b1 };
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r_unfl <= 1'b0;
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r_unfl <= 1'b0;
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end else if (i_rd)
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end else if (i_rd)
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begin
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begin
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if ((i_wr)||(!will_underflow)) // (r_first != r_last)
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if ((i_wr)||(!will_underflow)) // (r_first != r_last)
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r_last <= w_last_plus_one;
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begin
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r_last <= r_next;
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r_next <= r_last +{{(LGFLEN-2){1'b0}},2'b10};
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// Last chases first
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// Last chases first
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// Need to be prepared for a possible two
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// Need to be prepared for a possible two
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// reads in quick succession
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// reads in quick succession
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// o_data <= fifo[r_last+1];
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// o_data <= fifo[r_last+1];
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else
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end else
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r_unfl <= 1'b1;
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r_unfl <= 1'b1;
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end
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end
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reg [7:0] fifo_here, fifo_next, r_data;
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reg [7:0] fifo_here, fifo_next, r_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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fifo_here <= fifo[r_last];
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fifo_here <= fifo[r_last];
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always @(posedge i_clk)
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always @(posedge i_clk)
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fifo_next <= fifo[r_last+{{(LGFLEN-1){1'b0}},1'b1}];
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fifo_next <= fifo[r_next];
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_data <= i_data;
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r_data <= i_data;
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reg [1:0] osrc;
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reg [1:0] osrc;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (will_underflow)
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if (will_underflow)
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// o_data <= i_data;
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// o_data <= i_data;
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osrc <= 2'b00;
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osrc <= 2'b00;
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else if ((i_rd)&&(r_first == w_last_plus_one))
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else if ((i_rd)&&(r_first == w_last_plus_one))
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osrc <= 2'b01;
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osrc <= 2'b01;
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else if (i_rd)
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else if (i_rd)
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osrc <= 2'b11;
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osrc <= 2'b11;
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else
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else
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osrc <= 2'b10;
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osrc <= 2'b10;
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assign o_data = (osrc[1]) ? ((osrc[0])?fifo_next:fifo_here) : r_data;
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assign o_data = (osrc[1]) ? ((osrc[0])?fifo_next:fifo_here) : r_data;
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// wire [(LGFLEN-1):0] current_fill;
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// wire [(LGFLEN-1):0] current_fill;
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// assign current_fill = (r_first-r_last);
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// assign current_fill = (r_first-r_last);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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o_empty_n <= 1'b0;
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o_empty_n <= 1'b0;
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else case({i_wr, i_rd})
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else case({i_wr, i_rd})
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2'b00: o_empty_n <= (r_first != r_last);
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2'b00: o_empty_n <= (r_first != r_last);
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2'b11: o_empty_n <= (r_first != r_last);
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2'b11: o_empty_n <= (r_first != r_last);
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2'b10: o_empty_n <= 1'b1;
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2'b10: o_empty_n <= 1'b1;
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2'b01: o_empty_n <= (r_first != w_last_plus_one);
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2'b01: o_empty_n <= (r_first != w_last_plus_one);
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endcase
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endcase
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reg [(LGFLEN-1):0] r_fill;
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reg [(LGFLEN-1):0] r_fill;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_fill <= 0;
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r_fill <= 0;
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else if ((i_rd)&&(!i_wr))
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else if ((i_rd)&&(!i_wr))
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r_fill <= r_first - r_last - 1'b1;
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r_fill <= r_first - r_next;
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else if ((!i_rd)&&(i_wr))
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else if ((!i_rd)&&(i_wr))
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r_fill <= r_first - r_last + 1'b1;
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r_fill <= r_first - r_last + 1'b1;
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else
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else
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r_fill <= r_first - r_last;
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r_fill <= r_first - r_last;
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assign o_half_full = r_fill[(LGFLEN-1)];
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assign o_half_full = r_fill[(LGFLEN-1)];
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assign o_err = (r_ovfl) || (r_unfl);
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assign o_err = (r_ovfl) || (r_unfl);
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wire [3:0] lglen;
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wire [3:0] lglen;
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assign lglen = LGFLEN;
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assign lglen = LGFLEN;
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assign o_status = { lglen, {(16-2-4-LGFLEN){1'b0}}, r_fill, o_half_full, o_empty_n };
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assign o_status = { lglen, {(16-2-4-LGFLEN){1'b0}}, r_fill, o_half_full, o_empty_n };
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endmodule
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endmodule
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