library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity interface_slave_iir is
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entity interface_slave_iir is
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generic(
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generic(
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Data_wordwidth: integer;
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Data_wordwidth: integer;
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Adress_wordwidth: integer;
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Adress_wordwidth: integer;
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Adr_bas:integer;
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Adr_bas:integer;
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Reg_control:integer;
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Reg_control:integer;
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Reg_data:integer;
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Reg_data:integer;
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Reg_status:integer;
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Reg_status:integer;
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Reg_coef:integer;
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Reg_coef:integer;
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Reg_gain:integer;
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Reg_gain:integer;
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Reg_Nsec:integer;
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Reg_Nsec:integer;
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NSECT:integer;
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NSECT:integer;
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M:integer
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M:integer
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);
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);
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port(
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port(
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ACK_O: out std_logic;--to MASTER
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ACK_O: out std_logic;--to MASTER
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ADR_I: in std_logic_vector( Adress_wordwidth-1 downto 0 );
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ADR_I: in std_logic_vector( Adress_wordwidth-1 downto 0 );
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DAT_I: in std_logic_vector( Data_wordwidth-1 downto 0 );--from MASTER
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DAT_I: in std_logic_vector( Data_wordwidth-1 downto 0 );--from MASTER
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sDAT_I: in std_logic_vector( Data_wordwidth-1 downto 0 );--from SLAVE
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sDAT_I: in std_logic_vector( Data_wordwidth-1 downto 0 );--from SLAVE
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DAT_O: out std_logic_vector( Data_wordwidth-1 downto 0 );--to MASTER
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DAT_O: out std_logic_vector( Data_wordwidth-1 downto 0 );--to MASTER
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sDAT_O: out std_logic_vector( Data_wordwidth-1 downto 0 );--to SLAVE
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sDAT_O: out std_logic_vector( Data_wordwidth-1 downto 0 );--to SLAVE
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en_out: out std_logic_vector( 3 downto 0 );--to slave
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en_out: out std_logic_vector( 3 downto 0 );--to slave
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STB_I: in std_logic;--from MASTER
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STB_I: in std_logic;--from MASTER
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WE_I: in std_logic;--from MASTER
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WE_I: in std_logic;--from MASTER
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Start: out std_logic;--to SLAVE
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Start: out std_logic;--to SLAVE
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h0: out std_logic_vector( (NSECT*M*6)-1 downto 0 );--to SLAVE
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h0: out std_logic_vector( (NSECT*M*6)-1 downto 0 );--to SLAVE
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gain: out std_logic_vector(M-1 downto 0);
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gain: out std_logic_vector(M-1 downto 0);
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enable_in: in std_logic;
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enable_in: in std_logic;
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clear,reset,clk: in std_logic
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clear,reset,clk: in std_logic
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);
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);
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end entity;
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end entity;
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architecture RTL of interface_slave_iir is
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architecture RTL of interface_slave_iir is
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--The fullregister component
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--The fullregister component
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component fullregister is
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component fullregister is
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generic
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generic
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(
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(
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N: integer
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N: integer
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);
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);
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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reset_n : in std_logic;
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reset_n : in std_logic;
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enable : in std_logic;
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enable : in std_logic;
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clear : in std_logic;
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clear : in std_logic;
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d : in std_logic_vector(N-1 downto 0);
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d : in std_logic_vector(N-1 downto 0);
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q : out std_logic_vector(N-1 downto 0)
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q : out std_logic_vector(N-1 downto 0)
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);
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);
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end component;
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end component;
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signal OUT_AUX, ZERO,ssDAT_O,RegsDAT_O: std_logic_vector( Data_wordwidth-1 downto 0 );
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signal OUT_AUX, ZERO,ssDAT_O,RegsDAT_O: std_logic_vector( Data_wordwidth-1 downto 0 );
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signal rSTATUS_O,enable_in_aux:std_logic_vector( 0 downto 0 );
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signal rSTATUS_O,enable_in_aux:std_logic_vector( 0 downto 0 );
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signal Clear_Status:std_logic;
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signal Clear_Status:std_logic;
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signal enable_gain:std_logic;
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signal enable_gain:std_logic;
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signal EN_ZERO: std_logic_vector(3 downto 0);
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signal EN_ZERO: std_logic_vector(3 downto 0);
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type array_aux is array(6*NSECT downto 0) of std_logic_vector(M-1 downto 0);
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type array_aux is array(6*NSECT downto 0) of std_logic_vector(M-1 downto 0);
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signal h0_aux:array_aux;
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signal h0_aux:array_aux;
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signal gains: std_logic_vector(M-1 downto 0);
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signal gains: std_logic_vector(M-1 downto 0);
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type array_aux1 is array(6*NSECT downto 0) of std_logic;
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type array_aux1 is array(6*NSECT downto 0) of std_logic;
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signal enables:array_aux1;
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signal enables:array_aux1;
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begin
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begin
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ZERO<=std_logic_vector(to_unsigned(0,Data_wordwidth));
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ZERO<=std_logic_vector(to_unsigned(0,Data_wordwidth));
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EN_ZERO<=std_logic_vector(to_unsigned(0,4));
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EN_ZERO<=std_logic_vector(to_unsigned(0,4));
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OUT_AUX<=DAT_I;
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OUT_AUX<=DAT_I;
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ACK_O<=STB_I;
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ACK_O<=STB_I;
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enable_in_aux(0)<=enable_in;
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enable_in_aux(0)<=enable_in;
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--DAT_O<=sDAT_I;
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--DAT_O<=sDAT_I;
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coefficients:
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coefficients:
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for k in 6*NSECT-1 downto 0 generate
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for k in 6*NSECT-1 downto 0 generate
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enables(k)<='1' when ( WE_I='1' and STB_I='1' and ADR_I(7 downto 0)=std_logic_vector(to_unsigned((4*k)+Reg_coef,8))) else
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enables(k)<='1' when ( WE_I='1' and STB_I='1' and ADR_I(7 downto 0)=std_logic_vector(to_unsigned((4*k)+Reg_coef,8))) else
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'0';
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'0';
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coefs:fullregister
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coefs:fullregister
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generic map(
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generic map(
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N=>M
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N=>M
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)
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)
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port map (
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port map (
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clk=>clk,
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clk=>clk,
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reset_n=>reset,
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reset_n=>reset,
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enable=>enables(k),
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enable=>enables(k),
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clear=>clear,
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clear=>clear,
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d=>OUT_AUX(M-1 downto 0),
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d=>OUT_AUX(M-1 downto 0),
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q=>h0_aux(k)
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q=>h0_aux(k)
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);
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);
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h0((k+1)*M-1 downto k*M)<=std_logic_vector(h0_aux(k));
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h0((k+1)*M-1 downto k*M)<=std_logic_vector(h0_aux(k));
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end generate;
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end generate;
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process(ADR_I,STB_I,WE_I,ZERO,EN_ZERO,OUT_AUX,rSTATUS_O)
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process(ADR_I,STB_I,WE_I,ZERO,EN_ZERO,OUT_AUX,rSTATUS_O)
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begin
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begin
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if (WE_I='1' and STB_I='1') then--ESCRIBIR EN EL FILTRO
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if (WE_I='1' and STB_I='1') then--ESCRIBIR EN EL FILTRO
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case ADR_I(7 downto 0) is
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case ADR_I(7 downto 0) is
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when std_logic_vector(to_unsigned(Reg_control,8)) => start<='1';
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when std_logic_vector(to_unsigned(Reg_control,8)) => start<='1';
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DAT_O<=ZERO;
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DAT_O<=ZERO;
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Clear_Status<='0';
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Clear_Status<='0';
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when std_logic_vector(to_unsigned(Reg_status,8))=> Clear_Status<='1';
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when std_logic_vector(to_unsigned(Reg_status,8))=> Clear_Status<='1';
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DAT_O<=ZERO;
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DAT_O<=ZERO;
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start<='0';
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start<='0';
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when OTHERS => start<='0';
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when OTHERS => start<='0';
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DAT_O<=ZERO;
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DAT_O<=ZERO;
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Clear_Status<='0';
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Clear_Status<='0';
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end case;
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end case;
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elsif (WE_I='0' and STB_I='1') then
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elsif (WE_I='0' and STB_I='1') then
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case ADR_I(7 downto 0) is --LEER EL FILTRO
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case ADR_I(7 downto 0) is --LEER EL FILTRO
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when std_logic_vector(to_unsigned(Reg_data,8)) =>
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when std_logic_vector(to_unsigned(Reg_data,8)) =>
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DAT_O<=RegsDAT_O;
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DAT_O<=RegsDAT_O;
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start<='0';
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start<='0';
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Clear_Status<='0';
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Clear_Status<='0';
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when std_logic_vector(to_unsigned(Reg_status,8)) => DAT_O(0)<=rSTATUS_O(0);
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when std_logic_vector(to_unsigned(Reg_status,8)) => DAT_O(0)<=rSTATUS_O(0);
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DAT_O(Data_wordwidth-1 downto 1)<=ZERO(Data_wordwidth-1 downto 1);
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DAT_O(Data_wordwidth-1 downto 1)<=ZERO(Data_wordwidth-1 downto 1);
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start<='0';
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start<='0';
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Clear_Status<='0';
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Clear_Status<='0';
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when OTHERS => start<='0';
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when OTHERS => start<='0';
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--DAT_O(M-1 downto 0)<= h0_aux(to_integer(unsigned(ADR_I(7 downto 0))-Reg_coef)/4);
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--DAT_O(M-1 downto 0)<= h0_aux(to_integer(unsigned(ADR_I(7 downto 0))-Reg_coef)/4);
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--DAT_O(Data_wordwidth-1 downto M)<=(others => h0_aux(to_integer(unsigned(ADR_I(7 downto 0))-Reg_coef)/4)(M-1) );
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--DAT_O(Data_wordwidth-1 downto M)<=(others => h0_aux(to_integer(unsigned(ADR_I(7 downto 0))-Reg_coef)/4)(M-1) );
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--DAT_O<=ssDAT_O;
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DAT_O<=ssDAT_O;
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DAT_O(M-1 downto 0)<= gains;
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--DAT_O(M-1 downto 0)<= gains;
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DAT_O(Data_wordwidth-1 downto M)<=(others => gains(M-1) );
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--DAT_O(Data_wordwidth-1 downto M)<=(others => gains(M-1) );
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Clear_Status<='0';
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Clear_Status<='0';
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end case;
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end case;
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else
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else
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start<='0';
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start<='0';
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DAT_O<=ZERO;
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DAT_O<=ZERO;
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Clear_Status<='0';
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Clear_Status<='0';
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end if;
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end if;
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end process;
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end process;
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process(ADR_I,STB_I,WE_I,OUT_AUX)
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process(ADR_I,STB_I,WE_I,OUT_AUX)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if (WE_I='1' and STB_I='1') then
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if (WE_I='1' and STB_I='1') then
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if ADR_I(7 downto 0)=std_logic_vector(to_unsigned(reg_data,8)) then
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if ADR_I(7 downto 0)=std_logic_vector(to_unsigned(reg_data,8)) then
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ssDAT_O<=OUT_AUX;
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ssDAT_O<=OUT_AUX;
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end if;
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end if;
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if ADR_I(7 downto 0)=std_logic_vector(to_unsigned(Reg_Nsec,8)) then
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if ADR_I(7 downto 0)=std_logic_vector(to_unsigned(Reg_Nsec,8)) then
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en_out<=OUT_AUX(3 downto 0);
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en_out<=OUT_AUX(3 downto 0);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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Reg_Stat:fullregister
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Reg_Stat:fullregister
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generic map(
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generic map(
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N=>1
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N=>1
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)
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)
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port map (
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port map (
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clk=>clk,
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clk=>clk,
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reset_n=>reset,
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reset_n=>reset,
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enable=>(enable_in or Clear_Status),
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enable=>(enable_in or Clear_Status),
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clear=>Clear_Status,
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clear=>Clear_Status,
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d=>enable_in_aux,
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d=>enable_in_aux,
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q=>rSTATUS_O
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q=>rSTATUS_O
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);
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);
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Reg_sDat_O:fullregister
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Reg_sDat_O:fullregister
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generic map(
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generic map(
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N=>Data_wordwidth
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N=>Data_wordwidth
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)
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)
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port map (
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port map (
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clk=>clk,
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clk=>clk,
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reset_n=>reset,
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reset_n=>reset,
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enable=>enable_in ,
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enable=>enable_in ,
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clear=>clear,
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clear=>clear,
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d=>sDAT_I,
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d=>sDAT_I,
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q=>RegsDAT_O
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q=>RegsDAT_O
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);
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);
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sDAT_O<=ssDAT_O;
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sDAT_O<=ssDAT_O;
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--Registro para gain
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--Registro para gain
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enable_gain<='1' when ( WE_I='1' and STB_I='1' and ADR_I(7 downto 0)=std_logic_vector(to_unsigned(Reg_gain,8))) else
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enable_gain<='1' when ( WE_I='1' and STB_I='1' and ADR_I(7 downto 0)=std_logic_vector(to_unsigned(Reg_gain,8))) else
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'0';
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'0';
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gainreg:fullregister
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gainreg:fullregister
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generic map(
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generic map(
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N=>M
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N=>M
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)
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)
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port map (
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port map (
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clk=>clk,
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clk=>clk,
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reset_n=>reset,
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reset_n=>reset,
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enable=>enable_gain,
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enable=>enable_gain,
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clear=>clear,
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clear=>clear,
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d=>DAT_I(M-1 downto 0),
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d=>DAT_I(M-1 downto 0),
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q=>gains
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q=>gains
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);
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);
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gain<=gains;
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gain<=gains;
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end architecture;
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end architecture;
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