//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_cinterface.v
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// fm_cinterface.v
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//
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//
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// Abstract:
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// Abstract:
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// Memory Interconnect command interface
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// Memory Interconnect command interface
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2016, Kenji Ishimaru
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// Copyright (c) 2016, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_cinterface (
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module fm_cinterface (
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clk_core,
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clk_core,
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rst_x,
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rst_x,
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// bus side port
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// bus side port
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i_bstr,
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i_bstr,
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i_bdata,
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i_bdata,
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o_back,
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o_back,
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// internal port
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// internal port
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o_istr,
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o_istr,
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o_idata,
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o_idata,
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i_iack
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i_iack
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);
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);
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parameter P_WIDTH = 8;
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parameter P_WIDTH = 8;
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////////////////////////////
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////////////////////////////
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// I/O definitions
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// I/O definitions
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////////////////////////////
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////////////////////////////
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input i_bstr; // input strobe
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input i_bstr; // input strobe
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input [P_WIDTH-1:0]
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input [P_WIDTH-1:0]
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i_bdata; // input data
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i_bdata; // input data
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output o_back; // output acknowledge
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output o_back; // output acknowledge
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output o_istr; // output strobe
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output o_istr; // output strobe
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output [P_WIDTH-1:0]
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output [P_WIDTH-1:0]
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o_idata; // output data
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o_idata; // output data
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input i_iack; // input acknowledge
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input i_iack; // input acknowledge
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input clk_core; // system clock
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input clk_core; // system clock
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input rst_x; // system reset
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input rst_x; // system reset
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/////////////////////////
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/////////////////////////
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// register definition
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// register definition
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/////////////////////////
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/////////////////////////
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// input register
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// input register
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reg r_bstr;
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reg r_bstr;
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reg [P_WIDTH-1:0]
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reg [P_WIDTH-1:0]
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r_bdata;
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r_bdata;
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reg r_back;
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reg r_back;
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/////////////////////////
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/////////////////////////
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// wire definition
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// wire definition
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/////////////////////////
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/////////////////////////
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wire w_empty;
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wire w_empty;
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/////////////////////////
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/////////////////////////
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// assign statement
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// assign statement
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/////////////////////////
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/////////////////////////
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assign o_istr = !w_empty;
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assign o_istr = !w_empty;
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assign o_back = r_back;
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assign o_back = r_back;
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/////////////////////////
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/////////////////////////
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// always statement
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// always statement
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/////////////////////////
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/////////////////////////
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_bstr <= 1'b0;
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r_bstr <= 1'b0;
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end else begin
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end else begin
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r_bstr <= i_bstr;
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r_bstr <= i_bstr;
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end
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end
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end
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end
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_back <= 1'b0;
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r_back <= 1'b0;
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end else begin
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end else begin
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r_back <= i_iack;
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r_back <= i_iack;
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end
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end
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end
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end
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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r_bdata <= i_bdata;
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r_bdata <= i_bdata;
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end
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end
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/////////////////////////
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/////////////////////////
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// module instanciation
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// module instanciation
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/////////////////////////
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/////////////////////////
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// input data fifo
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// input data fifo
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fm_ififo #(P_WIDTH) fifo (
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fm_ififo #(P_WIDTH) fifo (
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.i_wstrobe(r_bstr),
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.i_wstrobe(r_bstr),
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.i_dt(r_bdata),
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.i_dt(r_bdata),
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.o_full(),
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.o_full(),
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.i_renable(i_iack),
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.i_renable(i_iack),
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.o_dt(o_idata),
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.o_dt(o_idata),
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.o_empty(w_empty),
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.o_empty(w_empty),
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x)
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.rst_x(rst_x)
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);
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);
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endmodule
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endmodule
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