//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_cmn_if_ff_out.v
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// fm_cmn_if_ff_out.v
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//
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//
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// Abstract:
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// Abstract:
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// F/F bus interface
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// F/F bus interface
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2016, Kenji Ishimaru
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// Copyright (c) 2016, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_cmn_if_ff_out (
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module fm_cmn_if_ff_out (
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clk_core,
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clk_core,
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rst_x,
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rst_x,
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// local interface
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// local interface
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i_req,
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i_req,
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i_wr,
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i_wr,
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i_adrs,
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i_adrs,
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i_len,
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i_len,
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o_ack,
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o_ack,
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i_strw,
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i_strw,
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i_be,
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i_be,
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i_dbw,
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i_dbw,
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o_ackw,
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o_ackw,
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o_strr,
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o_strr,
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o_dbr,
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o_dbr,
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// F/F interface
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// F/F interface
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o_req,
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o_req,
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o_wr,
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o_wr,
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o_adrs,
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o_adrs,
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o_len,
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o_len,
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i_ack,
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i_ack,
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o_strw,
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o_strw,
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o_be,
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o_be,
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o_dbw,
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o_dbw,
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i_ackw,
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i_ackw,
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i_strr,
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i_strr,
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i_dbr
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i_dbr
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);
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);
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//////////////////////////////////
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//////////////////////////////////
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// parameter
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// parameter
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//////////////////////////////////
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//////////////////////////////////
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parameter P_ADRS_WIDTH = 'd22;
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parameter P_ADRS_WIDTH = 'd22;
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parameter P_DATA_WIDTH = 'd32;
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parameter P_DATA_WIDTH = 'd32;
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parameter P_BLEN_WIDTH = 'd6;
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parameter P_BLEN_WIDTH = 'd6;
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parameter P_BE_WIDTH = P_DATA_WIDTH/8;
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parameter P_BE_WIDTH = P_DATA_WIDTH/8;
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//////////////////////////////////
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//////////////////////////////////
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// I/O port definition
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// I/O port definition
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//////////////////////////////////
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//////////////////////////////////
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input clk_core;
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input clk_core;
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input rst_x;
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input rst_x;
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// local interface
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// local interface
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input i_req;
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input i_req;
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input i_wr;
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input i_wr;
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input [P_ADRS_WIDTH-1:0]
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input [P_ADRS_WIDTH-1:0]
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i_adrs;
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i_adrs;
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input [P_BLEN_WIDTH-1:0]
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input [P_BLEN_WIDTH-1:0]
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i_len;
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i_len;
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output o_ack;
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output o_ack;
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input i_strw;
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input i_strw;
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input [P_BE_WIDTH-1:0]
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input [P_BE_WIDTH-1:0]
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i_be;
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i_be;
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input [P_DATA_WIDTH-1:0]
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input [P_DATA_WIDTH-1:0]
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i_dbw;
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i_dbw;
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output o_ackw;
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output o_ackw;
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output o_strr;
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output o_strr;
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output [P_DATA_WIDTH-1:0]
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output [P_DATA_WIDTH-1:0]
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o_dbr;
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o_dbr;
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// F/F-ed interface
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// F/F-ed interface
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output o_req;
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output o_req;
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output o_wr;
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output o_wr;
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output [P_ADRS_WIDTH-1:0]
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output [P_ADRS_WIDTH-1:0]
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o_adrs;
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o_adrs;
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output [P_BLEN_WIDTH-1:0]
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output [P_BLEN_WIDTH-1:0]
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o_len;
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o_len;
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input i_ack;
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input i_ack;
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output o_strw;
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output o_strw;
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output [P_BE_WIDTH-1:0]
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output [P_BE_WIDTH-1:0]
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o_be;
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o_be;
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output [P_DATA_WIDTH-1:0]
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output [P_DATA_WIDTH-1:0]
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o_dbw;
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o_dbw;
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input i_ackw;
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input i_ackw;
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input i_strr;
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input i_strr;
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input [P_DATA_WIDTH-1:0]
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input [P_DATA_WIDTH-1:0]
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i_dbr;
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i_dbr;
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//////////////////////////////////
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//////////////////////////////////
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// reg
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// reg
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//////////////////////////////////
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//////////////////////////////////
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reg r_req;
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reg r_req;
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reg r_wr;
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reg r_wr;
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reg [P_ADRS_WIDTH-1:0]
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reg [P_ADRS_WIDTH-1:0]
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r_adrs;
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r_adrs;
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reg [P_BLEN_WIDTH-1:0]
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reg [P_BLEN_WIDTH-1:0]
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r_len;
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r_len;
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reg r_ack;
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reg r_ack;
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reg r_strw;
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reg r_strw;
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reg [P_BE_WIDTH-1:0]
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reg [P_BE_WIDTH-1:0]
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r_be;
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r_be;
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reg [P_DATA_WIDTH-1:0]
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reg [P_DATA_WIDTH-1:0]
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r_dbw;
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r_dbw;
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reg r_ackw;
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reg r_ackw;
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// reg [P_DATA_WIDTH-1:0]
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// reg [P_DATA_WIDTH-1:0]
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// r_dbr;
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// r_dbr;
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// reg r_strr;
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// reg r_strr;
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//////////////////////////////////
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//////////////////////////////////
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// wire
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// wire
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//////////////////////////////////
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//////////////////////////////////
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//////////////////////////////////
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//////////////////////////////////
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// assign
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// assign
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//////////////////////////////////
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//////////////////////////////////
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assign o_req = r_req;
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assign o_req = r_req;
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assign o_wr = r_wr;
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assign o_wr = r_wr;
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assign o_adrs = r_adrs;
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assign o_adrs = r_adrs;
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assign o_len = r_len;
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assign o_len = r_len;
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assign o_strw = r_strw;
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assign o_strw = r_strw;
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assign o_be = r_be;
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assign o_be = r_be;
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assign o_dbw = r_dbw;
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assign o_dbw = r_dbw;
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assign o_ack = (i_req & i_wr) ? (r_ack & r_ackw) : r_ack;
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assign o_ack = (i_req & i_wr) ? (r_ack & r_ackw) : r_ack;
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assign o_ackw = (i_req & i_wr) ? (r_ack & r_ackw) : r_ackw;
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assign o_ackw = (i_req & i_wr) ? (r_ack & r_ackw) : r_ackw;
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assign o_dbr = i_dbr;
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assign o_dbr = i_dbr;
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assign o_strr = i_strr;
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assign o_strr = i_strr;
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//////////////////////////////////
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//////////////////////////////////
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// always
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// always
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//////////////////////////////////
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//////////////////////////////////
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_req <= 1'b0;
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r_req <= 1'b0;
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r_wr <= 1'b0;
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r_wr <= 1'b0;
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r_strw <= 1'b0;
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r_strw <= 1'b0;
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end else begin
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end else begin
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r_req <= (o_ack) ? i_req : 1'b0;
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r_req <= (o_ack) ? i_req : 1'b0;
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r_wr <= i_wr;
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r_wr <= i_wr;
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r_strw <= (o_ackw & i_strw);
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r_strw <= (o_ackw & i_strw);
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end
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end
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end
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end
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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r_adrs <= i_adrs;
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r_adrs <= i_adrs;
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r_len <= i_len;
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r_len <= i_len;
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r_be <= i_be;
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r_be <= i_be;
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r_dbw <= i_dbw;
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r_dbw <= i_dbw;
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end
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end
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_ack <= 1'b0;
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r_ack <= 1'b0;
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r_ackw <= 1'b0;
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r_ackw <= 1'b0;
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end else begin
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end else begin
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r_ack <= i_ack;
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r_ack <= i_ack;
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r_ackw <= i_ackw;
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r_ackw <= i_ackw;
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end
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end
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end
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end
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endmodule
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endmodule
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