//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_hvc.v
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// fm_hvc.v
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//
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//
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// Abstract:
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// Abstract:
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// VGA LCD Controller
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// VGA LCD Controller
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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// 2016/08/14 64-bit bus support
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// 2016/08/14 64-bit bus support
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module fm_hvc (
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module fm_hvc (
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clk_core,
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clk_core,
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clk_vi,
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clk_vi,
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rst_x,
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rst_x,
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// configuration registers
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// configuration registers
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i_video_start,
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i_video_start,
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i_fb0_offset,
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i_fb0_offset,
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i_fb1_offset,
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i_fb1_offset,
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i_color_mode,
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i_color_mode,
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i_front_buffer,
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i_front_buffer,
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// status out
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// status out
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o_vint_x,
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o_vint_x,
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o_vint_edge,
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o_vint_edge,
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// dram if
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// dram if
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o_req,
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o_req,
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o_adrs,
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o_adrs,
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o_len,
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o_len,
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i_ack,
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i_ack,
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i_rstr,
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i_rstr,
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i_rd,
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i_rd,
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// video out
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// video out
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clk_vo,
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clk_vo,
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o_r,
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o_r,
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o_g,
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o_g,
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o_b,
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o_b,
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o_vsync_x,
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o_vsync_x,
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o_hsync_x,
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o_hsync_x,
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o_blank_x,
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o_blank_x,
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o_de
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o_de
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);
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);
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localparam P_IB_LEN_WIDTH = 'd6;
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localparam P_IB_LEN_WIDTH = 'd6;
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`ifdef PP_BUSWIDTH_64
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`ifdef PP_BUSWIDTH_64
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localparam P_IB_BASE_WIDTH = 'd12;
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localparam P_IB_BASE_WIDTH = 'd12;
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localparam P_IB_ADDR_WIDTH = 'd29;
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localparam P_IB_ADDR_WIDTH = 'd29;
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localparam P_IB_DATA_WIDTH = 'd64;
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localparam P_IB_DATA_WIDTH = 'd64;
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`else
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`else
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localparam P_IB_BASE_WIDTH = 'd7;
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localparam P_IB_BASE_WIDTH = 'd7;
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localparam P_IB_ADDR_WIDTH = 'd24;
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localparam P_IB_ADDR_WIDTH = 'd24;
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localparam P_IB_DATA_WIDTH = 'd32;
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localparam P_IB_DATA_WIDTH = 'd32;
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`endif
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`endif
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//////////////////////////////////
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//////////////////////////////////
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// I/O port definition
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// I/O port definition
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//////////////////////////////////
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//////////////////////////////////
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input clk_core;
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input clk_core;
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input clk_vi; // 25MHz
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input clk_vi; // 25MHz
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input rst_x;
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input rst_x;
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// configuration registers
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// configuration registers
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input i_video_start;
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input i_video_start;
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input [P_IB_BASE_WIDTH-1:0] i_fb0_offset;
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input [P_IB_BASE_WIDTH-1:0] i_fb0_offset;
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input [P_IB_BASE_WIDTH-1:0] i_fb1_offset;
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input [P_IB_BASE_WIDTH-1:0] i_fb1_offset;
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input [1:0] i_color_mode;
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input [1:0] i_color_mode;
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input i_front_buffer;
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input i_front_buffer;
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// status out
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// status out
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output o_vint_x;
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output o_vint_x;
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output o_vint_edge;
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output o_vint_edge;
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// dram if
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// dram if
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output o_req;
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output o_req;
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output [P_IB_ADDR_WIDTH-1:0]
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output [P_IB_ADDR_WIDTH-1:0]
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o_adrs;
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o_adrs;
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output [P_IB_LEN_WIDTH-1:0]
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output [P_IB_LEN_WIDTH-1:0]
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o_len;
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o_len;
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input i_ack;
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input i_ack;
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input i_rstr;
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input i_rstr;
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input [P_IB_DATA_WIDTH-1:0]
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input [P_IB_DATA_WIDTH-1:0]
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i_rd;
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i_rd;
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output clk_vo;
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output clk_vo;
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output [7:0] o_r;
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output [7:0] o_r;
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output [7:0] o_g;
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output [7:0] o_g;
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output [7:0] o_b;
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output [7:0] o_b;
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output o_vsync_x;
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output o_vsync_x;
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output o_hsync_x;
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output o_hsync_x;
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output o_blank_x;
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output o_blank_x;
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output o_de;
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output o_de;
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//////////////////////////////////
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//////////////////////////////////
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// wire
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// wire
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//////////////////////////////////
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//////////////////////////////////
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wire [7:0] w_test_r;
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wire [7:0] w_test_r;
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wire [7:0] w_test_g;
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wire [7:0] w_test_g;
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wire [7:0] w_test_b;
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wire [7:0] w_test_b;
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wire w_vsync_i;
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wire w_vsync_i;
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wire w_hsync_i;
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wire w_hsync_i;
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wire w_active;
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wire w_active;
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wire w_first_line;
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wire w_first_line;
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wire w_fifo_available;
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wire w_fifo_available;
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wire w_fifo_available_ack;
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wire w_fifo_available_ack;
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//////////////////////////////////
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//////////////////////////////////
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// assign
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// assign
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//////////////////////////////////
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//////////////////////////////////
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assign clk_vo = clk_vi;
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assign clk_vo = clk_vi;
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///////////////////////////
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///////////////////////////
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// module instance
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// module instance
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//////////////////////////
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//////////////////////////
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fm_hvc_core fm_hvc_core (
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fm_hvc_core fm_hvc_core (
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.clk_vi(clk_vi),
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.clk_vi(clk_vi),
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.rst_x(rst_x),
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.rst_x(rst_x),
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// configuration registers
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// configuration registers
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.i_video_start(i_video_start),
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.i_video_start(i_video_start),
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// control out (only for internal use)
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// control out (only for internal use)
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.o_vsync_i(w_vsync_i),
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.o_vsync_i(w_vsync_i),
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.o_hsync_i(w_hsync_i),
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.o_hsync_i(w_hsync_i),
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// video out timing
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// video out timing
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.o_active(w_active),
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.o_active(w_active),
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.o_first_line(w_first_line),
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.o_first_line(w_first_line),
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.o_r(w_test_r),
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.o_r(w_test_r),
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.o_g(w_test_g),
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.o_g(w_test_g),
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.o_b(w_test_b),
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.o_b(w_test_b),
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.o_vsync_x(o_vsync_x),
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.o_vsync_x(o_vsync_x),
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.o_hsync_x(o_hsync_x),
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.o_hsync_x(o_hsync_x),
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.o_blank_x(o_blank_x),
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.o_blank_x(o_blank_x),
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.o_de(o_de)
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.o_de(o_de)
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);
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);
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`ifdef PP_USE_AXI
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`ifdef PP_USE_AXI
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`ifdef PP_BUSWIDTH_64
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`ifdef PP_BUSWIDTH_64
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`else
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`else
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wire w_req;
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wire w_req;
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wire [P_IB_ADDR_WIDTH-1:0]
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wire [P_IB_ADDR_WIDTH-1:0]
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w_adrs;
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w_adrs;
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wire [P_IB_LEN_WIDTH-1:0]
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wire [P_IB_LEN_WIDTH-1:0]
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w_len;
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w_len;
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wire w_ack;
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wire w_ack;
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fm_rd_split fm_rd_split (
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fm_rd_split fm_rd_split (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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.i_req(w_req),
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.i_req(w_req),
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.i_adrs(w_adrs),
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.i_adrs(w_adrs),
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.i_len(w_len),
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.i_len(w_len),
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.o_ack(w_ack),
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.o_ack(w_ack),
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// dram if
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// dram if
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.o_req(o_req),
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.o_req(o_req),
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.o_adrs(o_adrs),
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.o_adrs(o_adrs),
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.o_len(o_len),
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.o_len(o_len),
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.i_ack(i_ack)
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.i_ack(i_ack)
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);
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);
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`endif
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`endif
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`endif
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`endif
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fm_hvc_dma #(.P_IB_ADDR_WIDTH(P_IB_ADDR_WIDTH),
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fm_hvc_dma #(.P_IB_ADDR_WIDTH(P_IB_ADDR_WIDTH),
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.P_IB_LEN_WIDTH(P_IB_LEN_WIDTH))
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.P_IB_LEN_WIDTH(P_IB_LEN_WIDTH))
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fm_hvc_dma (
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fm_hvc_dma (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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.i_color_mode(i_color_mode),
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.i_color_mode(i_color_mode),
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.i_video_start(i_video_start),
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.i_video_start(i_video_start),
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.i_vsync(w_vsync_i),
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.i_vsync(w_vsync_i),
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.i_hsync(w_hsync_i),
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.i_hsync(w_hsync_i),
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.i_fb0_offset(i_fb0_offset),
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.i_fb0_offset(i_fb0_offset),
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.i_fb1_offset(i_fb1_offset),
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.i_fb1_offset(i_fb1_offset),
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.i_front_buffer(i_front_buffer),
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.i_front_buffer(i_front_buffer),
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.i_fifo_available(w_fifo_available),
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.i_fifo_available(w_fifo_available),
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.o_fifo_available_ack(w_fifo_available_ack),
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.o_fifo_available_ack(w_fifo_available_ack),
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.o_vsync(o_vint_x),
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.o_vsync(o_vint_x),
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.o_vsync_edge(o_vint_edge),
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.o_vsync_edge(o_vint_edge),
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// dram if
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// dram if
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`ifdef PP_USE_AXI
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`ifdef PP_USE_AXI
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`ifdef PP_BUSWIDTH_64
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`ifdef PP_BUSWIDTH_64
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.o_req(o_req),
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.o_req(o_req),
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.o_adrs(o_adrs),
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.o_adrs(o_adrs),
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.o_len(o_len),
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.o_len(o_len),
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.i_ack(i_ack)
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.i_ack(i_ack)
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`else
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`else
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.o_req(w_req),
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.o_req(w_req),
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.o_adrs(w_adrs),
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.o_adrs(w_adrs),
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.o_len(w_len),
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.o_len(w_len),
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.i_ack(w_ack)
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.i_ack(w_ack)
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`endif
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`endif
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`else
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`else
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.o_req(o_req),
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.o_req(o_req),
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.o_adrs(o_adrs),
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.o_adrs(o_adrs),
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.o_len(o_len),
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.o_len(o_len),
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.i_ack(i_ack)
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.i_ack(i_ack)
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`endif
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`endif
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);
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);
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fm_hvc_data fm_hvc_data (
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fm_hvc_data fm_hvc_data (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.clk_vi(clk_vi),
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.clk_vi(clk_vi),
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.rst_x(rst_x),
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.rst_x(rst_x),
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// sdram interface
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// sdram interface
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.i_rstr(i_rstr),
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.i_rstr(i_rstr),
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.i_rd(i_rd),
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.i_rd(i_rd),
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// timing control
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// timing control
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.i_h_active(w_active),
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.i_h_active(w_active),
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.i_first_line(w_first_line),
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.i_first_line(w_first_line),
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.i_hsync(w_hsync_i),
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.i_hsync(w_hsync_i),
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.i_vsync(w_vsync_i),
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.i_vsync(w_vsync_i),
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.o_fifo_available(w_fifo_available),
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.o_fifo_available(w_fifo_available),
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.i_fifo_available_ack(w_fifo_available_ack),
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.i_fifo_available_ack(w_fifo_available_ack),
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// configuration
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// configuration
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.i_video_start(i_video_start),
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.i_video_start(i_video_start),
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.i_color_mode(i_color_mode),
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.i_color_mode(i_color_mode),
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// test color input
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// test color input
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.i_test_r(w_test_r),
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.i_test_r(w_test_r),
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.i_test_g(w_test_g),
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.i_test_g(w_test_g),
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.i_test_b(w_test_b),
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.i_test_b(w_test_b),
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// color out
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// color out
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.o_r(o_r),
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.o_r(o_r),
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.o_g(o_g),
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.o_g(o_g),
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.o_b(o_b),
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.o_b(o_b),
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.o_a()
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.o_a()
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);
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);
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endmodule
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endmodule
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