Wire-Frame 3D Graphics Accelerator IP Core
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Wire-Frame 3D Graphics Accelerator IP Core
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Project Monophony
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Project Monophony
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================================================
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================================================
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Author: Kenji Ishimaru
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Author: Kenji Ishimaru
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2016/09/19
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2016/09/19
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Sample implementation for ZedBoard is added.
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Sample implementation for ZedBoard is added.
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2016/08/14
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2016/08/14
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new demo appication is added.
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new demo appication is added.
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2015/09/30
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2015/09/30
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Overview
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Overview
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This IP Core is a wire-frame 3D hardware accelerator.
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This IP Core is a wire-frame 3D hardware accelerator.
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Features:
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Features:
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- Hardware Geometry Engine and Rasterizer
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- Hardware Geometry Engine and Rasterizer
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- Model-View-Projection matrix transformation
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- Model-View-Projection matrix transformation
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- Clipping
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- Clipping
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- Back-face culling
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- Back-face culling
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- Viewport mapping
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- Viewport mapping
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- Wire-Frame rasterization with 8 bit color
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- Wire-Frame rasterization with 8 bit color
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- DMAC for reading 3D object vertices
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- DMAC for reading 3D object vertices
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- support triangle format only.
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- support triangle format only.
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(does NOT support triangle strip, point, line etc.)
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(does NOT support triangle strip, point, line etc.)
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- Screen size: up to 2014 x 1536(QXGA)
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- Screen size: up to 2014 x 1536(QXGA)
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- Small logic consumption
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- Small logic consumption
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- Low bandwidth requirement
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- Low bandwidth requirement
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The IP Core does NOT support:
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The IP Core does NOT support:
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- Memory clear DMAC
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- Memory clear DMAC
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- Filled triangle rasterization
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- Filled triangle rasterization
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- Texture mapping
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- Texture mapping
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- Lighting
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- Lighting
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Additional resources:
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Additional resources:
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- Sample FPGA system implementation (DE0/ZedBoard)
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- Sample FPGA system implementation (DE0/ZedBoard)
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- with original VGA controller
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- with original VGA controller
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- Demo applications
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- Demo applications
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- C API for controlling 3D scene
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- C API for controlling 3D scene
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- 3D model convert script
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- 3D model convert script
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For more details,
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For more details,
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please see doc/3DGraphics_IPCore_Specification.pdf.
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please see doc/3DGraphics_IPCore_Specification.pdf.
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Directories
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Directories
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---------------------------------------
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---------------------------------------
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The directory structure looks as follows:
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The directory structure looks as follows:
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doc/ - Documentation
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doc/ - Documentation
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rtl/ - HDL source code
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rtl/ - HDL source code
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scenario/ - Simulation test benches
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scenario/ - Simulation test benches
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bin/ - Simulation scripts
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bin/ - Simulation scripts
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sim_work/ - Simulation work directory
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sim_work/ - Simulation work directory
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implement/ - FPGA implementation example (DE0/ZedBoard)
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implement/ - FPGA implementation example (DE0/ZedBoard)
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tool/ - 3D model convert tool and sample.
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tool/ - 3D model convert tool and sample.
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clib/ - C API source code
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clib/ - C API source code
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demo_app/ - Demo applications
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demo_app/ - Demo applications
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IP Core Source Code
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IP Core Source Code
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----------------------------
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----------------------------
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The IP Core is written by verilog-HDL. The source code is Vendor independent.
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The IP Core is written by verilog-HDL. The source code is Vendor independent.
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does not require any Vendor specific module.
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does not require any Vendor specific module.
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Simulation
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Simulation
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----------------------------
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scenario directory contains simple rendering bench.
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scenario directory contains simple rendering bench.
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the rendering result is converted to bmp file.
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the rendering result is converted to bmp file.
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For more details, please see sim_work/readme.txt
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For more details, please see sim_work/readme.txt
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FPGA Sample Implementation
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FPGA Sample Implementation
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----------------------------
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FPGA system implementation sample is available.
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FPGA system implementation sample is available.
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The target board is DE0.
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The target board is DE0.
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The project data is tested on Quartus II Version 13.1.
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The project data is tested on Quartus II Version 13.1.
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For more details, please see implement/readme_de0.txt
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For more details, please see implement/readme_de0.txt
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The other target board is Zedboard.
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The other target board is Zedboard.
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The project data is tested on Vivado v2015.6(64-bit) Windows.
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The project data is tested on Vivado v2015.6(64-bit) Windows.
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For more details, please see implement/readme_zedboard.txt
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For more details, please see implement/readme_zedboard.txt
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Graphics C API
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Graphics C API
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----------------------------
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clib/ contains C API source code for this IP Core.
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clib/ contains C API source code for this IP Core.
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The API controls 3D scene, and controls IP Core by register configuration.
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The API controls 3D scene, and controls IP Core by register configuration.
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For more details,
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For more details,
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please see doc/3DGraphics_C_Library_Specification.pdf.
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please see doc/3DGraphics_C_Library_Specification.pdf.
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Demo Application
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Demo Application
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demo_app/ contains demo applications.
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demo_app/ contains demo applications.
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simple_cube: rotating cube demo
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simple_cube: rotating cube demo
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main_cubes: rotating cubes. matrix push/pop demo
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main_cubes: rotating cubes. matrix push/pop demo
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main_bear: bear characters
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main_bear: bear characters
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main_hand: hand animation
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main_hand: hand animation
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Screen shots of these demos are available in screen_shot/
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Screen shots of these demos are available in screen_shot/
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3D Data Tool
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3D Data Tool
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tool/objcnv.pl perl script convertes .obj format 3D data to
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tool/objcnv.pl perl script convertes .obj format 3D data to
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C float array format, and output as C header file.
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C float array format, and output as C header file.
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For more details, please see tool/readme.txt
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For more details, please see tool/readme.txt
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