//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// rand_delay.v
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// rand_delay.v
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//
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//
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// Abstract:
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// Abstract:
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// Pipeline delay module (without reset)
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// Pipeline delay module (without reset)
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// parameters :
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// parameters :
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// WIDTH data width (default value is 8)
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// WIDTH data width (default value is 8)
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// NUM_DELAY number of delay cycle (default value is 8)
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// NUM_DELAY number of delay cycle (default value is 8)
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module rand_delay (
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module rand_delay (
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clk_core,
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clk_core,
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rst_x,
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rst_x,
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i_en,
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i_en,
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i_delay,
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i_delay,
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i_data,
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i_data,
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o_data,
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o_data,
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o_en
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o_en
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);
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);
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////////////////////////////
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////////////////////////////
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// parameter
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// parameter
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////////////////////////////
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////////////////////////////
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parameter P_WIDTH = 8;
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parameter P_WIDTH = 8;
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parameter P_NUM_DELAY = 8;
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parameter P_NUM_DELAY = 8;
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////////////////////////////
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////////////////////////////
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// I/O definition
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// I/O definition
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////////////////////////////
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////////////////////////////
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input clk_core;
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input clk_core;
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input rst_x;
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input rst_x;
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input i_en;
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input i_en;
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input [7:0] i_delay;
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input [7:0] i_delay;
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input [P_WIDTH-1:0] i_data;
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input [P_WIDTH-1:0] i_data;
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output [P_WIDTH-1:0] o_data;
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output [P_WIDTH-1:0] o_data;
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output o_en;
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output o_en;
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////////////////////////////
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////////////////////////////
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// wire
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// wire
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////////////////////////////
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////////////////////////////
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wire w_full;
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wire w_full;
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wire w_ren;
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wire w_ren;
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wire [P_WIDTH-1:0] w_dt;
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wire [P_WIDTH-1:0] w_dt;
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wire w_empty;
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wire w_empty;
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////////////////////////////
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////////////////////////////
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// reg
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// reg
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////////////////////////////
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////////////////////////////
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localparam P_IDLE = 'd0;
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localparam P_IDLE = 'd0;
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localparam P_WAIT = 'd1;
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localparam P_WAIT = 'd1;
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reg [1:0] r_state;
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reg [1:0] r_state;
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reg [7:0] r_cnt;
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reg [7:0] r_cnt;
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reg [7:0] r_end;
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reg [7:0] r_end;
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////////////////////////////
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////////////////////////////
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// assign
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// assign
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////////////////////////////
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////////////////////////////
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assign w_ren = ((r_state == P_IDLE) & (i_delay == 'd0))|
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assign w_ren = ((r_state == P_IDLE) & (i_delay == 'd0))|
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((r_state == P_WAIT) & (r_end == r_cnt));
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((r_state == P_WAIT) & (r_end == r_cnt));
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// in/out port connection
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// in/out port connection
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assign o_data = (w_empty) ? 'd0 : w_dt;
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assign o_data = (w_empty) ? 'd0 : w_dt;
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assign o_en = w_ren & !w_empty;
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assign o_en = w_ren & !w_empty;
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////////////////////////////
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////////////////////////////
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// always
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// always
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////////////////////////////
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////////////////////////////
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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end else begin
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end else begin
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case (r_state)
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case (r_state)
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P_IDLE:begin
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P_IDLE:begin
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if (~w_empty) begin
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if (~w_empty) begin
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if (i_delay != 0) begin
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if (i_delay != 0) begin
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r_end <= i_delay;
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r_end <= i_delay;
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r_cnt <= 'd0;
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r_cnt <= 'd0;
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r_state <= P_WAIT;
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r_state <= P_WAIT;
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end
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end
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end
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end
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end
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end
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P_WAIT:begin
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P_WAIT:begin
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r_cnt <= r_cnt + 1;
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r_cnt <= r_cnt + 1;
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if (r_end == r_cnt) begin
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if (r_end == r_cnt) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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mfifo #(P_WIDTH,8) u_fifo (
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mfifo #(P_WIDTH,8) u_fifo (
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.i_wstrobe(i_en),
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.i_wstrobe(i_en),
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.i_dt(i_data),
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.i_dt(i_data),
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.o_full(w_full),
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.o_full(w_full),
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.i_renable(w_ren),
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.i_renable(w_ren),
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.o_dt(w_dt),
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.o_dt(w_dt),
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.o_empty(w_empty),
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.o_empty(w_empty),
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.o_dnum(),
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.o_dnum(),
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.clk(clk_core),
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.clk(clk_core),
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.rst_x(rst_x)
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.rst_x(rst_x)
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);
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);
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endmodule
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endmodule
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