//******************************************************************************************************
|
//******************************************************************************************************
|
// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
|
// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
|
|
|
|
|
//File name : ahbmas_wbslv_top_tb.v
|
//File name : ahbmas_wbslv_top_tb.v
|
//Designer : Ravi S Gupta
|
//Designer : Ravi S Gupta
|
//Date : 23 May, 2007
|
//Date : 23 May, 2007
|
//Description : Wishbone to AHB interface protocol converter Testbench
|
//Description : Wishbone to AHB interface protocol converter Testbench
|
//Revision : 1.0
|
//Revision : 1.0
|
|
|
|
|
//******************************************************************************************************
|
//******************************************************************************************************
|
|
|
//DEFINES
|
//DEFINES
|
`define DEL 1 //Clock to output delay, zero time delays can cause problems
|
`define DEL 1 //Clock to output delay, zero time delays can cause problems
|
//TOP MODULE
|
//TOP MODULE
|
module AHBMAS_WBSLV_TOP_tb ;
|
module AHBMAS_WBSLV_TOP_tb ;
|
//PARAMETERS
|
//PARAMETERS
|
parameter DWIDTH = 32 ;
|
parameter DWIDTH = 32 ;
|
parameter AWIDTH = 32 ;
|
parameter AWIDTH = 32 ;
|
parameter TON = 5 ;
|
parameter TON = 5 ;
|
parameter TOFF = 5 ;
|
parameter TOFF = 5 ;
|
|
|
integer address = 0;
|
integer address = 0;
|
integer data = 0;
|
integer data = 0;
|
//SIGNAL DECLARATIONS
|
//SIGNAL DECLARATIONS
|
wire [1:0] htrans ;
|
wire [1:0] htrans ;
|
reg stb_i ;
|
reg stb_i ;
|
reg [DWIDTH-1:0] data_i ;
|
reg [DWIDTH-1:0] data_i ;
|
wire hwrite ;
|
wire hwrite ;
|
reg [3:0] sel_i ;
|
reg [3:0] sel_i ;
|
reg [DWIDTH-1:0] hrdata ;
|
reg [DWIDTH-1:0] hrdata ;
|
wire ack_o ;
|
wire ack_o ;
|
reg hready ;
|
reg hready ;
|
wire [DWIDTH-1:0] data_o ;
|
wire [DWIDTH-1:0] data_o ;
|
wire [2:0] hburst ;
|
wire [2:0] hburst ;
|
wire [31:0] hwdata ;
|
wire [31:0] hwdata ;
|
reg [1:0] hresp ;
|
reg [1:0] hresp ;
|
reg [AWIDTH-1:0] addr_i ;
|
reg [AWIDTH-1:0] addr_i ;
|
wire [AWIDTH-1:0] haddr ;
|
wire [AWIDTH-1:0] haddr ;
|
wire [2:0] hsize ;
|
wire [2:0] hsize ;
|
reg we_i ;
|
reg we_i ;
|
reg cyc_i ;
|
reg cyc_i ;
|
reg clk_i ;
|
reg clk_i ;
|
reg rst_i ;
|
reg rst_i ;
|
reg hclk;
|
reg hclk;
|
reg hresetn;
|
reg hresetn;
|
|
|
//MAIN CODE
|
//MAIN CODE
|
//Instantiate the DUT
|
//Instantiate the DUT
|
AHBMAS_WBSLV_TOP #( DWIDTH , AWIDTH )
|
AHBMAS_WBSLV_TOP #( DWIDTH , AWIDTH )
|
DUT (
|
DUT (
|
.htrans (htrans ) ,
|
.htrans (htrans ) ,
|
.stb_i (stb_i ) ,
|
.stb_i (stb_i ) ,
|
.data_i (data_i ) ,
|
.data_i (data_i ) ,
|
.hwrite (hwrite ) ,
|
.hwrite (hwrite ) ,
|
.sel_i (sel_i ) ,
|
.sel_i (sel_i ) ,
|
.hrdata (hrdata ) ,
|
.hrdata (hrdata ) ,
|
.ack_o (ack_o ) ,
|
.ack_o (ack_o ) ,
|
.hready (hready ) ,
|
.hready (hready ) ,
|
.data_o (data_o ) ,
|
.data_o (data_o ) ,
|
.hburst (hburst ) ,
|
.hburst (hburst ) ,
|
.hwdata (hwdata ) ,
|
.hwdata (hwdata ) ,
|
.hresp (hresp ) ,
|
.hresp (hresp ) ,
|
.addr_i (addr_i ) ,
|
.addr_i (addr_i ) ,
|
.haddr (haddr ) ,
|
.haddr (haddr ) ,
|
.hsize (hsize ) ,
|
.hsize (hsize ) ,
|
.we_i (we_i ) ,
|
.we_i (we_i ) ,
|
.cyc_i (cyc_i ) ,
|
.cyc_i (cyc_i ) ,
|
.clk_i (clk_i),
|
.clk_i (clk_i),
|
.rst_i (rst_i),
|
.rst_i (rst_i),
|
.hclk (hclk),
|
.hclk (hclk),
|
.hresetn(hresetn));
|
.hresetn(hresetn));
|
|
|
// Clock Generation
|
// Clock Generation
|
always begin
|
always begin
|
#TOFF //clk generation with OFF timeperiod = 5
|
#TOFF //clk generation with OFF timeperiod = 5
|
clk_i = 'b0;
|
clk_i = 'b0;
|
#TON //clk generation with ON timeperiod = 5
|
#TON //clk generation with ON timeperiod = 5
|
clk_i = 'b1;
|
clk_i = 'b1;
|
end
|
end
|
// local memory in AHB slave model
|
// local memory in AHB slave model
|
reg [DWIDTH-1 : 0] ahb_mem [AWIDTH-1 : 0];
|
reg [DWIDTH-1 : 0] ahb_mem [AWIDTH-1 : 0];
|
reg [AWIDTH-1:0] haddr_temp;
|
reg [AWIDTH-1:0] haddr_temp;
|
reg [DWIDTH-1 :0] hrdata_temp;
|
reg [DWIDTH-1 :0] hrdata_temp;
|
reg hwrite_temp;
|
reg hwrite_temp;
|
|
|
// always@(posedge clk_i)
|
// always@(posedge clk_i)
|
// hrdata <= hrdata_temp;
|
// hrdata <= hrdata_temp;
|
//*************************************************
|
//*************************************************
|
// AHB slave model
|
// AHB slave model
|
//*************************************************
|
//*************************************************
|
|
|
always @(posedge clk_i) begin
|
always @(posedge clk_i) begin
|
if (hready) begin
|
if (hready) begin
|
haddr_temp <= #2 haddr;
|
haddr_temp <= #2 haddr;
|
hwrite_temp<=#2 hwrite;
|
hwrite_temp<=#2 hwrite;
|
if (hwrite_temp) begin
|
if (hwrite_temp) begin
|
ahb_mem[haddr_temp] <= #2 hwdata; // data stored in ahb slave
|
ahb_mem[haddr_temp] <= #2 hwdata; // data stored in ahb slave
|
end
|
end
|
else if (!hwrite) begin
|
else if (!hwrite) begin
|
hrdata <= #2 ahb_mem[haddr];
|
hrdata <= #2 ahb_mem[haddr];
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//*****************************************
|
//*****************************************
|
//Write operations with no wait states
|
//Write operations with no wait states
|
//*****************************************
|
//*****************************************
|
task write_data;
|
task write_data;
|
|
|
input [AWIDTH-1:0] addr;
|
input [AWIDTH-1:0] addr;
|
input [DWIDTH-1:0] Data;
|
input [DWIDTH-1:0] Data;
|
begin
|
begin
|
#2
|
#2
|
cyc_i=1'b1;
|
cyc_i=1'b1;
|
stb_i=1'b1;
|
stb_i=1'b1;
|
we_i=1'b1;
|
we_i=1'b1;
|
//if(ack_o) begin
|
//if(ack_o) begin
|
addr_i <= addr;
|
addr_i <= addr;
|
data_i <= Data;//Send Data
|
data_i <= Data;//Send Data
|
//end
|
//end
|
hready <= 'b1;
|
hready <= 'b1;
|
end
|
end
|
endtask
|
endtask
|
//************************************************
|
//************************************************
|
//Write operations with wait states from AHB Slave
|
//Write operations with wait states from AHB Slave
|
//************************************************
|
//************************************************
|
task write_data_WSAHB;
|
task write_data_WSAHB;
|
begin
|
begin
|
@(posedge clk_i) begin
|
@(posedge clk_i) begin
|
#2 cyc_i = 1'b1;
|
#2 cyc_i = 1'b1;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
we_i = 1'b1;
|
we_i = 1'b1;
|
hready = 1'b0; //AHB Master is in Wait State
|
hready = 1'b0; //AHB Master is in Wait State
|
end
|
end
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//***********************************************
|
//***********************************************
|
//Write operations with wait states from WB Master
|
//Write operations with wait states from WB Master
|
//***********************************************
|
//***********************************************
|
task write_data_WSWB;
|
task write_data_WSWB;
|
begin
|
begin
|
@(posedge clk_i) begin
|
@(posedge clk_i) begin
|
#2 cyc_i = 1'b1;
|
#2 cyc_i = 1'b1;
|
stb_i = 1'b0;//WB Master is in Wait State
|
stb_i = 1'b0;//WB Master is in Wait State
|
we_i = 1'b1;
|
we_i = 1'b1;
|
hready = 1'b1;
|
hready = 1'b1;
|
end
|
end
|
end
|
end
|
|
|
endtask
|
endtask
|
|
|
//*************************************
|
//*************************************
|
//Read operations without wait states
|
//Read operations without wait states
|
//*************************************
|
//*************************************
|
task read_data;
|
task read_data;
|
input [31:0] addr;
|
input [31:0] addr;
|
begin #2
|
begin #2
|
cyc_i=1'b1;
|
cyc_i=1'b1;
|
stb_i=1'b1;
|
stb_i=1'b1;
|
we_i=1'b0;
|
we_i=1'b0;
|
if (ack_o) begin
|
if (ack_o) begin
|
addr_i = addr;
|
addr_i = addr;
|
end
|
end
|
// else begin
|
// else begin
|
// hrdata_temp = ahb_mem[haddr];
|
// hrdata_temp = ahb_mem[haddr];
|
// end
|
// end
|
hready = 1'b1;
|
hready = 1'b1;
|
end
|
end
|
endtask
|
endtask
|
//**********************************************
|
//**********************************************
|
//Read operations with wait states from AHB Slave
|
//Read operations with wait states from AHB Slave
|
//**********************************************
|
//**********************************************
|
task read_data_WSAHB;
|
task read_data_WSAHB;
|
begin
|
begin
|
@(posedge clk_i) begin
|
@(posedge clk_i) begin
|
#2 cyc_i = 1'b1;
|
#2 cyc_i = 1'b1;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
we_i = 1'b0;
|
we_i = 1'b0;
|
hready = 1'b0; //AHB Master is in Wait State
|
hready = 1'b0; //AHB Master is in Wait State
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
//**********************************************
|
//**********************************************
|
//Read operations with wait states from WB Master
|
//Read operations with wait states from WB Master
|
//**********************************************
|
//**********************************************
|
task read_data_WSWB;
|
task read_data_WSWB;
|
begin
|
begin
|
@(posedge clk_i) begin
|
@(posedge clk_i) begin
|
#2 cyc_i = 1'b1;
|
#2 cyc_i = 1'b1;
|
stb_i = 1'b0; //WB Master in in Wait state
|
stb_i = 1'b0; //WB Master in in Wait state
|
we_i = 1'b0;
|
we_i = 1'b0;
|
hready = 1'b1;
|
hready = 1'b1;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
// Initialize Inputs
|
// Initialize Inputs
|
initial
|
initial
|
begin
|
begin
|
clk_i=1'b0;
|
clk_i=1'b0;
|
|
|
rst_i = 'b0;
|
rst_i = 'b0;
|
#2
|
#2
|
rst_i = 'b1;
|
rst_i = 'b1;
|
#23
|
#23
|
rst_i = 'b0; // reset for more than one clock cycle
|
rst_i = 'b0; // reset for more than one clock cycle
|
|
|
hready = 1'b1;
|
hready = 1'b1;
|
hresp = 2'b00;
|
hresp = 2'b00;
|
# 20 cyc_i='b0;
|
# 20 cyc_i='b0;
|
stb_i='b0;
|
stb_i='b0;
|
sel_i=4'b0000;
|
sel_i=4'b0000;
|
|
|
|
|
//*************************************
|
//*************************************
|
//Block Write cycle
|
//Block Write cycle
|
//*************************************
|
//*************************************
|
repeat(7) begin
|
repeat(7) begin
|
address = address + 1;
|
address = address + 1;
|
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
|
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
|
data = data +1;
|
data = data +1;
|
end
|
end
|
//*************************************
|
//*************************************
|
//Write cycle with wait states from AHB Slave
|
//Write cycle with wait states from AHB Slave
|
//*************************************
|
//*************************************
|
// #10;
|
// #10;
|
repeat(2)
|
repeat(2)
|
write_data_WSAHB;
|
write_data_WSAHB;
|
//*************************************
|
//*************************************
|
//Block Write cycle
|
//Block Write cycle
|
//*************************************
|
//*************************************
|
// #10;
|
// #10;
|
repeat(4) begin
|
repeat(4) begin
|
address = address + 1;
|
address = address + 1;
|
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
|
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
|
data = data +1;
|
data = data +1;
|
end
|
end
|
//*************************************
|
//*************************************
|
//Write cycle with wait states from WB Master
|
//Write cycle with wait states from WB Master
|
//*************************************
|
//*************************************
|
// #10;
|
// #10;
|
repeat(2)
|
repeat(2)
|
write_data_WSWB;
|
write_data_WSWB;
|
|
|
//*************************************
|
//*************************************
|
//Block Write cycle
|
//Block Write cycle
|
//*************************************
|
//*************************************
|
// #10;
|
// #10;
|
repeat(4) begin
|
repeat(4) begin
|
address = address + 1;
|
address = address + 1;
|
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
|
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
|
data = data +1;
|
data = data +1;
|
end
|
end
|
|
|
//*************************************
|
//*************************************
|
//Block Read cycle
|
//Block Read cycle
|
//*************************************
|
//*************************************
|
// #10;
|
// #10;
|
repeat(6) begin
|
repeat(6) begin
|
@(posedge clk_i) read_data(address);
|
@(posedge clk_i) read_data(address);
|
address = address -1;
|
address = address -1;
|
end
|
end
|
|
|
//*************************************
|
//*************************************
|
//Read cycle with Wait State from AHB Slave
|
//Read cycle with Wait State from AHB Slave
|
//*************************************
|
//*************************************
|
// #10;
|
// #10;
|
repeat(2)
|
repeat(2)
|
read_data_WSAHB;
|
read_data_WSAHB;
|
|
|
//*************************************
|
//*************************************
|
//Block Read cycle
|
//Block Read cycle
|
//*************************************
|
//*************************************
|
// #10;
|
// #10;
|
repeat(4) begin
|
repeat(4) begin
|
@(posedge clk_i) read_data(address);
|
@(posedge clk_i) read_data(address);
|
address = address -1;
|
address = address -1;
|
end
|
end
|
|
|
//*************************************
|
//*************************************
|
//Read cycle with Wait State from WB Master
|
//Read cycle with Wait State from WB Master
|
//*************************************
|
//*************************************
|
// #10;
|
// #10;
|
repeat(2)
|
repeat(2)
|
read_data_WSWB;
|
read_data_WSWB;
|
//*************************************
|
//*************************************
|
//Block Read cycle
|
//Block Read cycle
|
//*************************************
|
//*************************************
|
// #10;
|
// #10;
|
repeat(5) begin
|
repeat(5) begin
|
address = address + 1;
|
address = address + 1;
|
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
|
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
|
data = data +1;
|
data = data +1;
|
end
|
end
|
|
|
//*************************************
|
//*************************************
|
//Block Write cycle
|
//Block Write cycle
|
//*************************************
|
//*************************************
|
repeat(4) begin
|
repeat(4) begin
|
address = address + 1;
|
address = address + 1;
|
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
|
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
|
data = data +1;
|
data = data +1;
|
end
|
end
|
|
|
#20 stb_i='b0;
|
#20 stb_i='b0;
|
#5 cyc_i='b0;
|
#5 cyc_i='b0;
|
|
|
#200 $stop;
|
#200 $stop;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
