//******************************************************************************************************
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//******************************************************************************************************
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// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
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// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
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//File name : ahbmas_wbslv_top_tb.v
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//File name : ahbmas_wbslv_top_tb.v
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//Designer : Ravi S Gupta
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//Designer : Ravi S Gupta
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//Date : 23 May, 2007
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//Date : 23 May, 2007
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//Description : Wishbone to AHB interface protocol converter Testbench
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//Description : Wishbone to AHB interface protocol converter Testbench
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//Revision : 1.0
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//Revision : 1.0
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//******************************************************************************************************
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//******************************************************************************************************
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//DEFINES
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//DEFINES
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`define DEL 1 //Clock to output delay, zero time delays can cause problems
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`define DEL 1 //Clock to output delay, zero time delays can cause problems
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//TOP MODULE
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//TOP MODULE
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module AHBMAS_WBSLV_TOP_tb ;
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module AHBMAS_WBSLV_TOP_tb ;
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//PARAMETERS
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//PARAMETERS
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parameter DWIDTH = 32 ;
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parameter DWIDTH = 32 ;
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parameter AWIDTH = 32 ;
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parameter AWIDTH = 32 ;
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parameter TON = 5 ;
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parameter TON = 5 ;
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parameter TOFF = 5 ;
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parameter TOFF = 5 ;
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integer address = 0;
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integer address = 0;
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integer data = 0;
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integer data = 0;
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//SIGNAL DECLARATIONS
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//SIGNAL DECLARATIONS
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wire [1:0] htrans ;
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wire [1:0] htrans ;
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reg stb_i ;
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reg stb_i ;
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reg [DWIDTH-1:0] data_i ;
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reg [DWIDTH-1:0] data_i ;
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wire hwrite ;
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wire hwrite ;
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reg [3:0] sel_i ;
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reg [3:0] sel_i ;
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reg [DWIDTH-1:0] hrdata ;
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reg [DWIDTH-1:0] hrdata ;
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wire ack_o ;
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wire ack_o ;
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reg hready ;
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reg hready ;
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wire [DWIDTH-1:0] data_o ;
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wire [DWIDTH-1:0] data_o ;
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wire [2:0] hburst ;
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wire [2:0] hburst ;
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wire [31:0] hwdata ;
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wire [31:0] hwdata ;
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reg [1:0] hresp ;
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reg [1:0] hresp ;
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reg [AWIDTH-1:0] addr_i ;
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reg [AWIDTH-1:0] addr_i ;
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wire [AWIDTH-1:0] haddr ;
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wire [AWIDTH-1:0] haddr ;
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wire [2:0] hsize ;
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wire [2:0] hsize ;
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reg we_i ;
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reg we_i ;
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reg cyc_i ;
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reg cyc_i ;
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reg clk_i ;
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reg clk_i ;
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reg rst_i ;
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reg rst_i ;
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reg hclk;
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reg hclk;
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reg hresetn;
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reg hresetn;
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//MAIN CODE
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//MAIN CODE
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//Instantiate the DUT
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//Instantiate the DUT
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AHBMAS_WBSLV_TOP #( DWIDTH , AWIDTH )
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AHBMAS_WBSLV_TOP #( DWIDTH , AWIDTH )
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DUT (
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DUT (
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.htrans (htrans ) ,
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.htrans (htrans ) ,
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.stb_i (stb_i ) ,
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.stb_i (stb_i ) ,
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.data_i (data_i ) ,
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.data_i (data_i ) ,
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.hwrite (hwrite ) ,
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.hwrite (hwrite ) ,
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.sel_i (sel_i ) ,
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.sel_i (sel_i ) ,
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.hrdata (hrdata ) ,
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.hrdata (hrdata ) ,
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.ack_o (ack_o ) ,
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.ack_o (ack_o ) ,
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.hready (hready ) ,
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.hready (hready ) ,
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.data_o (data_o ) ,
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.data_o (data_o ) ,
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.hburst (hburst ) ,
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.hburst (hburst ) ,
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.hwdata (hwdata ) ,
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.hwdata (hwdata ) ,
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.hresp (hresp ) ,
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.hresp (hresp ) ,
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.addr_i (addr_i ) ,
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.addr_i (addr_i ) ,
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.haddr (haddr ) ,
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.haddr (haddr ) ,
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.hsize (hsize ) ,
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.hsize (hsize ) ,
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.we_i (we_i ) ,
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.we_i (we_i ) ,
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.cyc_i (cyc_i ) ,
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.cyc_i (cyc_i ) ,
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.clk_i (clk_i),
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.clk_i (clk_i),
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.rst_i (rst_i),
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.rst_i (rst_i),
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.hclk (hclk),
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.hclk (hclk),
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.hresetn(hresetn));
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.hresetn(hresetn));
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// Clock Generation
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// Clock Generation
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always begin
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always begin
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#TOFF //clk generation with OFF timeperiod = 5
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#TOFF //clk generation with OFF timeperiod = 5
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clk_i = 'b0;
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clk_i = 'b0;
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#TON //clk generation with ON timeperiod = 5
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#TON //clk generation with ON timeperiod = 5
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clk_i = 'b1;
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clk_i = 'b1;
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end
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end
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// local memory in AHB slave model
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// local memory in AHB slave model
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reg [DWIDTH-1 : 0] ahb_mem [AWIDTH-1 : 0];
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reg [DWIDTH-1 : 0] ahb_mem [AWIDTH-1 : 0];
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reg [AWIDTH-1:0] haddr_temp;
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reg [AWIDTH-1:0] haddr_temp;
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reg [DWIDTH-1 :0] hrdata_temp;
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reg [DWIDTH-1 :0] hrdata_temp;
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reg hwrite_temp;
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reg hwrite_temp;
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// always@(posedge clk_i)
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// always@(posedge clk_i)
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// hrdata <= hrdata_temp;
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// hrdata <= hrdata_temp;
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//*************************************************
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//*************************************************
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// AHB slave model
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// AHB slave model
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//*************************************************
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//*************************************************
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always @(posedge clk_i) begin
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always @(posedge clk_i) begin
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if (hready) begin
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if (hready) begin
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haddr_temp <= #2 haddr;
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haddr_temp <= #2 haddr;
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hwrite_temp<=#2 hwrite;
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hwrite_temp<=#2 hwrite;
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if (hwrite_temp) begin
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if (hwrite_temp) begin
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ahb_mem[haddr_temp] <= #2 hwdata; // data stored in ahb slave
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ahb_mem[haddr_temp] <= #2 hwdata; // data stored in ahb slave
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end
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end
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else if (!hwrite) begin
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else if (!hwrite) begin
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hrdata <= #2 ahb_mem[haddr];
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hrdata <= #2 ahb_mem[haddr];
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end
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end
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end
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end
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end
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end
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//*****************************************
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//*****************************************
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//Write operations with no wait states
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//Write operations with no wait states
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//*****************************************
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//*****************************************
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task write_data;
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task write_data;
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input [AWIDTH-1:0] addr;
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input [AWIDTH-1:0] addr;
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input [DWIDTH-1:0] Data;
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input [DWIDTH-1:0] Data;
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begin
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begin
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#2
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#2
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cyc_i=1'b1;
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cyc_i=1'b1;
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stb_i=1'b1;
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stb_i=1'b1;
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we_i=1'b1;
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we_i=1'b1;
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//if(ack_o) begin
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//if(ack_o) begin
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addr_i <= addr;
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addr_i <= addr;
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data_i <= Data;//Send Data
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data_i <= Data;//Send Data
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//end
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//end
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hready <= 'b1;
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hready <= 'b1;
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end
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end
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endtask
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endtask
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//************************************************
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//************************************************
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//Write operations with wait states from AHB Slave
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//Write operations with wait states from AHB Slave
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//************************************************
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//************************************************
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task write_data_WSAHB;
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task write_data_WSAHB;
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begin
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begin
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@(posedge clk_i) begin
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@(posedge clk_i) begin
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#2 cyc_i = 1'b1;
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#2 cyc_i = 1'b1;
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stb_i = 1'b1;
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stb_i = 1'b1;
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we_i = 1'b1;
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we_i = 1'b1;
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hready = 1'b0; //AHB Master is in Wait State
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hready = 1'b0; //AHB Master is in Wait State
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end
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end
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end
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end
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endtask
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endtask
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//***********************************************
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//***********************************************
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//Write operations with wait states from WB Master
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//Write operations with wait states from WB Master
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//***********************************************
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//***********************************************
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task write_data_WSWB;
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task write_data_WSWB;
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begin
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begin
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@(posedge clk_i) begin
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@(posedge clk_i) begin
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#2 cyc_i = 1'b1;
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#2 cyc_i = 1'b1;
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stb_i = 1'b0;//WB Master is in Wait State
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stb_i = 1'b0;//WB Master is in Wait State
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we_i = 1'b1;
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we_i = 1'b1;
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hready = 1'b1;
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hready = 1'b1;
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end
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end
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end
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end
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endtask
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endtask
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//*************************************
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//*************************************
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//Read operations without wait states
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//Read operations without wait states
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//*************************************
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//*************************************
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task read_data;
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task read_data;
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input [31:0] addr;
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input [31:0] addr;
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begin #2
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begin #2
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cyc_i=1'b1;
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cyc_i=1'b1;
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stb_i=1'b1;
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stb_i=1'b1;
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we_i=1'b0;
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we_i=1'b0;
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if (ack_o) begin
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if (ack_o) begin
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addr_i = addr;
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addr_i = addr;
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end
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end
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// else begin
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// else begin
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// hrdata_temp = ahb_mem[haddr];
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// hrdata_temp = ahb_mem[haddr];
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// end
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// end
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hready = 1'b1;
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hready = 1'b1;
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end
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end
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endtask
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endtask
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//**********************************************
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//**********************************************
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//Read operations with wait states from AHB Slave
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//Read operations with wait states from AHB Slave
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//**********************************************
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//**********************************************
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task read_data_WSAHB;
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task read_data_WSAHB;
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begin
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begin
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@(posedge clk_i) begin
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@(posedge clk_i) begin
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#2 cyc_i = 1'b1;
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#2 cyc_i = 1'b1;
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stb_i = 1'b1;
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stb_i = 1'b1;
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we_i = 1'b0;
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we_i = 1'b0;
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hready = 1'b0; //AHB Master is in Wait State
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hready = 1'b0; //AHB Master is in Wait State
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end
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end
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end
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end
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endtask
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endtask
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//**********************************************
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//**********************************************
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//Read operations with wait states from WB Master
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//Read operations with wait states from WB Master
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//**********************************************
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//**********************************************
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task read_data_WSWB;
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task read_data_WSWB;
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begin
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begin
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@(posedge clk_i) begin
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@(posedge clk_i) begin
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#2 cyc_i = 1'b1;
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#2 cyc_i = 1'b1;
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stb_i = 1'b0; //WB Master in in Wait state
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stb_i = 1'b0; //WB Master in in Wait state
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we_i = 1'b0;
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we_i = 1'b0;
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hready = 1'b1;
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hready = 1'b1;
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end
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end
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end
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end
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endtask
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endtask
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// Initialize Inputs
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// Initialize Inputs
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initial
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initial
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begin
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begin
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clk_i=1'b0;
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clk_i=1'b0;
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rst_i = 'b0;
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rst_i = 'b0;
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#2
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#2
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rst_i = 'b1;
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rst_i = 'b1;
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#23
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#23
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rst_i = 'b0; // reset for more than one clock cycle
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rst_i = 'b0; // reset for more than one clock cycle
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hready = 1'b1;
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hready = 1'b1;
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hresp = 2'b00;
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hresp = 2'b00;
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# 20 cyc_i='b0;
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# 20 cyc_i='b0;
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stb_i='b0;
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stb_i='b0;
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sel_i=4'b0000;
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sel_i=4'b0000;
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//*************************************
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//*************************************
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//Block Write cycle
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//Block Write cycle
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//*************************************
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//*************************************
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repeat(7) begin
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repeat(7) begin
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address = address + 1;
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address = address + 1;
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@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
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@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
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data = data +1;
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data = data +1;
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end
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end
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//*************************************
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//*************************************
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//Write cycle with wait states from AHB Slave
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//Write cycle with wait states from AHB Slave
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//*************************************
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//*************************************
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// #10;
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// #10;
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repeat(2)
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repeat(2)
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write_data_WSAHB;
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write_data_WSAHB;
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//*************************************
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//*************************************
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//Block Write cycle
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//Block Write cycle
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//*************************************
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//*************************************
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// #10;
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// #10;
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repeat(4) begin
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repeat(4) begin
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address = address + 1;
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address = address + 1;
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@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
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@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
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data = data +1;
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data = data +1;
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end
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end
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//*************************************
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//*************************************
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//Write cycle with wait states from WB Master
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//Write cycle with wait states from WB Master
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//*************************************
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//*************************************
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// #10;
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// #10;
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repeat(2)
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repeat(2)
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write_data_WSWB;
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write_data_WSWB;
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//*************************************
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//*************************************
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//Block Write cycle
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//Block Write cycle
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//*************************************
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//*************************************
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// #10;
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// #10;
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repeat(4) begin
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repeat(4) begin
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address = address + 1;
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address = address + 1;
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@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
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@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
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data = data +1;
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data = data +1;
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end
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end
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//*************************************
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//*************************************
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//Block Read cycle
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//Block Read cycle
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//*************************************
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//*************************************
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// #10;
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// #10;
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repeat(6) begin
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repeat(6) begin
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@(posedge clk_i) read_data(address);
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@(posedge clk_i) read_data(address);
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address = address -1;
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address = address -1;
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end
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end
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//*************************************
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//*************************************
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//Read cycle with Wait State from AHB Slave
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//Read cycle with Wait State from AHB Slave
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//*************************************
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//*************************************
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// #10;
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// #10;
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repeat(2)
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repeat(2)
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read_data_WSAHB;
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read_data_WSAHB;
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//*************************************
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//*************************************
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//Block Read cycle
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//Block Read cycle
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//*************************************
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//*************************************
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// #10;
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// #10;
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repeat(4) begin
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repeat(4) begin
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@(posedge clk_i) read_data(address);
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@(posedge clk_i) read_data(address);
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address = address -1;
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address = address -1;
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end
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end
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//*************************************
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//*************************************
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//Read cycle with Wait State from WB Master
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//Read cycle with Wait State from WB Master
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//*************************************
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//*************************************
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// #10;
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// #10;
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repeat(2)
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repeat(2)
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read_data_WSWB;
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read_data_WSWB;
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//*************************************
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//*************************************
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//Block Read cycle
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//Block Read cycle
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//*************************************
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//*************************************
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// #10;
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// #10;
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repeat(5) begin
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repeat(5) begin
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address = address + 1;
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address = address + 1;
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@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
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@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
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data = data +1;
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data = data +1;
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end
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end
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//*************************************
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//*************************************
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//Block Write cycle
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//Block Write cycle
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//*************************************
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//*************************************
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repeat(4) begin
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repeat(4) begin
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address = address + 1;
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address = address + 1;
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@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
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@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n])
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data = data +1;
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data = data +1;
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end
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end
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#20 stb_i='b0;
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#20 stb_i='b0;
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#5 cyc_i='b0;
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#5 cyc_i='b0;
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#200 $stop;
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#200 $stop;
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end
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end
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endmodule
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endmodule
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