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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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May 18,2010
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RTL - Fixed xlink synthesis warnings noted by Nachiket Jugade,
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missing else statment for chid_sm_ns line 393,
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missing default on shifter lines 2382 (Although all cases are covered).
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Testbench - No Change.
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Doc - No Change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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May 13,2010
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May 13,2010
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RTL - Code cleanup. Eliminated index [0] of "xgif" and "chan_req_i" output and
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RTL - Code cleanup. Eliminated index [0] of "xgif" and "chan_req_i" output and
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input pins along with assoicated status and and control registers. This
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input pins along with assoicated status and and control registers. This
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channel has never been usable.
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channel has never been usable.
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Testbench - Changes to match changes in RTL .
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Testbench - Changes to match changes in RTL .
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Doc - No Change.
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Doc - No Change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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May 12,2010
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May 12,2010
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RTL - Added new control registers for interrupt bypass function. Out of reset
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RTL - Added new control registers for interrupt bypass function. Out of reset
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all input interrupts are bypassed directly to the Xgate interrupt outputs.
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all input interrupts are bypassed directly to the Xgate interrupt outputs.
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The interrupts are also disabled from effecting the Xgate till the bypass
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The interrupts are also disabled from effecting the Xgate till the bypass
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is disabled. The interrupt priority has been flipped so that now the lowest
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is disabled. The interrupt priority has been flipped so that now the lowest
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index input interrupt has the highest priority.
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index input interrupt has the highest priority.
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Testbench - Added semaphore register and read only registers to observe irq
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Testbench - Added semaphore register and read only registers to observe irq
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outputs of Xgate to testbench slave module. Added parameters to support new
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outputs of Xgate to testbench slave module. Added parameters to support new
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Xgate registers and testbench registers. Added new test to checkout
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Xgate registers and testbench registers. Added new test to checkout
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bypass functionality and interrupt priority encoding.
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bypass functionality and interrupt priority encoding.
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Doc - Updated with additions of IRQ Bypass registers.
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Doc - Updated with additions of IRQ Bypass registers.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Apr 22,2010
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Apr 22,2010
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RTL - Fixed bug when entering DEBUG by command from the slave WISHBONE bus.
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RTL - Fixed bug when entering DEBUG by command from the slave WISHBONE bus.
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All tests now pass when the RAM wait states are set from zero to four. Five
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All tests now pass when the RAM wait states are set from zero to four. Five
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wait states times out in simulation while running the last test which is
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wait states times out in simulation while running the last test which is
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a simple register test otherwise I expect it would pass.
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a simple register test otherwise I expect it would pass.
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Testbench - Many of the failures while testing wait states were due to fixed
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Testbench - Many of the failures while testing wait states were due to fixed
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delays coded in the testbench. As necessary delays were changed to be a
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delays coded in the testbench. As necessary, delays were changed to be a
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function of a parameter that is based on the number of RAM wait states.
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function of a parameter that is based on the number of RAM wait states.
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Doc - No change.
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Doc - No change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Apr 5,2010
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Apr 5,2010
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RTL - First pass at fixing bug when entering DEBUG by command from the slave
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RTL - First pass at fixing bug when entering DEBUG by command from the slave
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WISHBONE bus. All tests now pass when the RAM wait states are set to zero,
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WISHBONE bus. All tests now pass when the RAM wait states are set to zero,
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although there are errors in DEBUG mode when RAM wait states are increased.
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although there are errors in DEBUG mode when RAM wait states are increased.
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Icarus Verilog version 0.9.2 now supports the "generate" command. This is
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Icarus Verilog version 0.9.2 now supports the "generate" command. This is
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now used to instantiate the semaphore registers.
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now used to instantiate the semaphore registers.
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Testbench - Added capability to insert wait states on RAM access.
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Testbench - Added capability to insert wait states on RAM access.
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Doc - No change.
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Doc - No change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Feb 12,2010
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Feb 12,2010
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RTL - Update to the WISHBONE interface when wait states are enabled to trade
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RTL - Update to the WISHBONE interface when wait states are enabled to trade
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16 data flops for 5 address registers. This change now also requires single
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16 data flops for 5 address registers. This change now also requires single
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cycle timing on the WISHBONE address bus, multi-cycle timing is still
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cycle timing on the WISHBONE address bus, multi-cycle timing is still
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allowed on the WISHBONE write data bus. In the old design WISHBONE read
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allowed on the WISHBONE write data bus. In the old design WISHBONE read
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cycles required the address to be decoded and the read data to be latched
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cycles required the address to be decoded and the read data to be latched
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in the first cycle and the there was a whole cycle to drive the read data
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in the first cycle and the there was a whole cycle to drive the read data
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bus. The new design latches the address in the first cycle then decodes the
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bus. The new design latches the address in the first cycle then decodes the
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address and outputs the data in the second cycle. (The WISHBONE bus doesn't
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address and outputs the data in the second cycle. (The WISHBONE bus doesn't
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require the address or data to be latched for multi-cycle operation but by
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require the address or data to be latched for multi-cycle operation but by
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doing this it is hoped some power will be saved in the combinational logic
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doing this it is hoped some power will be saved in the combinational logic
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by reducing the decoding activity at each address change.)
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by reducing the decoding activity at each address change.)
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Testbench - No change.
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Testbench - No change.
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Doc - No change.
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Doc - No change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Jan 27,2010
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Jan 27,2010
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RTL - 85% done -- Fixed error in wbs_ack_o signal when Xgate wait states were
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RTL - 85% done -- Fixed error in wbs_ack_o signal when Xgate wait states were
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enabled. If a slave bus transaction was started but not completed in the
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enabled. If a slave bus transaction was started but not completed in the
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second cycle a wbs_ack_o output was still generated. Added a wbs_err_o output
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second cycle a wbs_ack_o output was still generated. Added a wbs_err_o output
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signal to flag this input condition but not sure if it is really needed.
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signal to flag this input condition but not sure if it is really needed.
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The old testbench was "helping" the Xgate module by sending an almost
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The old testbench was "helping" the Xgate module by sending an almost
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continuous wbm_ack_i signal which allowed the RISC state machine to advance
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continuous wbm_ack_i signal which allowed the RISC state machine to advance
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when it shouldn't. Changes were made to the WISHBONE master bus interface
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when it shouldn't. Changes were made to the WISHBONE master bus interface
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and the RISC control logic.
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and the RISC control logic.
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Updates to testbench -- Extensive changes to testbench. The bus arbitration
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Updates to testbench -- Extensive changes to testbench. The bus arbitration
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module has been completely rewritten. It now completely controls access to the
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module has been completely rewritten. It now completely controls access to the
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system bus and RAM. It internally generates a WISHBONE ack signal for the RAM.
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system bus and RAM. It internally generates a WISHBONE ack signal for the RAM.
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The test control registers have been moved out of the top level and put into
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The test control registers have been moved out of the top level and put into
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a new WISHBONE slave module which also attaches to the system bus. The Xgate
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a new WISHBONE slave module which also attaches to the system bus. The Xgate
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modules master and slave buses are fully integrated with the bus arbitration
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modules master and slave buses are fully integrated with the bus arbitration
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module and the system bus. The new testbench looks a lot more like a real
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module and the system bus. The new testbench looks a lot more like a real
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system environment.
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system environment.
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To Do: Add back "random" wait state generation for RAM access.
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To Do: Add back "random" wait state generation for RAM access.
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Updates to User Guide -- Minor corrections to instruction set details. Needs more
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Updates to User Guide -- Minor corrections to instruction set details. Needs more
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review on condition code settings.
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review on condition code settings.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Jan 11,2010
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Jan 11,2010
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RTL - 85% done -- Fix error in Zero Flag calculation for ADC and SBC instructions
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RTL - 85% done -- Fix error in Zero Flag calculation for ADC and SBC instructions
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Fix Error in loading R2 durning cpu_state == BOOT_3.
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Fix Error in loading R2 durning cpu_state == BOOT_3.
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THere is a bug in DEBUG mode that is sensitive to number of preceding
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THere is a bug in DEBUG mode that is sensitive to number of preceding
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instructions and wait states that needs to be resolved.
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instructions and wait states that needs to be resolved.
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Updates to testbench --
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Updates to testbench --
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Updates to User Guide -- First pass with instruction set details. Needs more
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Updates to User Guide -- First pass with instruction set details. Needs more
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review on condition code settings.
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review on condition code settings.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Dec 08,2009
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Dec 08,2009
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RTL - 85% done -- Updated code so there is only one program counter adder.
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RTL - 85% done -- Updated code so there is only one program counter adder.
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Updated WISHBONE Slave bus for word addressability and byte selection.
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Updated WISHBONE Slave bus for word addressability and byte selection.
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Deleted two stack pointer registers.
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Deleted two stack pointer registers.
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Updates to testbench --
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Updates to testbench --
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Updates to User Guide -- Minor cleanup.
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Updates to User Guide -- Minor cleanup.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Nov 09,2009
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Nov 09,2009
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RTL - 85% done - Minor changes to Mastermode bus.
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RTL - 85% done - Minor changes to Mastermode bus.
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Updates to testbench, Moved RAM.to submodule, Added bus arbitration module
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Updates to testbench, Moved RAM.to submodule, Added bus arbitration module
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but this is not fully functional. Causes timing problems when master is
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but this is not fully functional. Causes timing problems when master is
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polling Xgate registers durning debug mode tests. Will probably change RAM
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polling Xgate registers durning debug mode tests. Will probably change RAM
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model to dual port in next revision.
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model to dual port in next revision.
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Updated master module to include WISHBONE select inputs.
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Updated master module to include WISHBONE select inputs.
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Updates to User Guide.
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Updates to User Guide.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Oct 07,2009
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Oct 07,2009
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RTL - 85% done
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RTL - 85% done
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All debug commands now working, including writes to XGCHID register.
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All debug commands now working, including writes to XGCHID register.
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Updates to testbench, added timeout and total error count.
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Updates to testbench, added timeout and total error count.
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Updates to User Guide --.
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Updates to User Guide --.
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Created the sw directory and copied over the software stuff from the bench
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Created the sw directory and copied over the software stuff from the bench
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directory.
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directory.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Sept 23,2009
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Sept 23,2009
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BRK instruction working. Single Step Command in debug mode working.
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BRK instruction working. Single Step Command in debug mode working.
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Software error interrupt added.
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Software error interrupt added.
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Updates to testbench.
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Updates to testbench.
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New assembly code directory: debug_test
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New assembly code directory: debug_test
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Sept 10,2009
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Sept 10,2009
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Added WISHBONE master bus submodule and some related top level signals but still
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Added WISHBONE master bus submodule and some related top level signals but still
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not much real functionality.
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not much real functionality.
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Added code to allow for memory access stalls.
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Added code to allow for memory access stalls.
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Upgraded testbench to insert memory wait states. Added more error detection
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Upgraded testbench to insert memory wait states. Added more error detection
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and summery.
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and summery.
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Improved instruction decoder. Still needs more work to remove redundant adders
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Improved instruction decoder. Still needs more work to remove redundant adders
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to improve synthesis results.
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to improve synthesis results.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Sept 1, 2009
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Sept 1, 2009
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This is a prerelease checkin and should be looked at as an incremental backup
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This is a prerelease checkin and should be looked at as an incremental backup
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and not representative of what may be in the final release.
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and not representative of what may be in the final release.
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RTL - 75% done
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RTL - 75% done
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What works:
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What works:
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Basic instruction set execution simulated and verified. Condition code
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Basic instruction set execution simulated and verified. Condition code
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operation on instructions partially verified.
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operation on instructions partially verified.
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Basic WISHBONE slave bus operation used, full functionality not verified.
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Basic WISHBONE slave bus operation used, full functionality not verified.
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What's broken or unimplemented:
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What's broken or unimplemented:
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All things related to debug mode.
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All things related to debug mode.
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WISHBONE master bus interface.
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WISHBONE master bus interface.
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User Documentation - 30% done
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User Documentation - 30% done
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