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Sept 10,2009
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Added WISHBONE master bus submodule and some related top level signals but still
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not much real functionality.
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Added code to allow for memory access stalls.
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Upgraded testbench to insert memory wait states. Added more error detection
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and summery.
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Improved instruction decoder. Still needs more work to remove redundant adders
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to improve synthesis results.
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Sept 1, 2009
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Sept 1, 2009
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This is a prerelease checkin and should be looked at as an incremental backup
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This is a prerelease checkin and should be looked at as an incremental backup
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and not representative of what may be in the final release.
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and not representative of what may be in the final release.
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RTL - 75% done
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RTL - 75% done
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What works:
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What works:
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Basic instruction set execution simulated and verified. Condition code
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Basic instruction set execution simulated and verified. Condition code
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operation on instructions partially verified.
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operation on instructions partially verified.
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Basic WISHBONE slave bus operation used, full functionality not verified.
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Basic WISHBONE slave bus operation used, full functionality not verified.
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What's broken or unimplemented:
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What's broken or unimplemented:
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All things related to debug mode.
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All things related to debug mode.
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WISHBONE master bus interface.
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WISHBONE master bus interface.
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User Documentation - 30% done
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User Documentation - 30% done
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