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Xgate Co-Processor (xgate) Specification
Author: Robert Hayes
rehayes@opencores.org
Rev. 0.1
TIME \@ "MMMM d, yyyy" October 7, 2009
This page has been intentionally left blank.
Revision History
Rev.DateAuthorDescription 0.109/29/09Robert Hayes
Contents
TOC \t "Heading 3,2,Index,1,Appendix A,1,Heading 2 name,1,Appendix B,1" Introduction PAGEREF _Toc115855036 \h 1
FEATURES PAGEREF _Toc115855037 \h 1
Architecture PAGEREF _Toc115855038 \h 3
2.1 WISHBONE Slave Interface PAGEREF _Toc115855039 \h 4
2.2 Control Registers PAGEREF _Toc115855040 \h 4
2.3 Interrupt Interface PAGEREF _Toc115855041 \h 4
2.4 WISHBONE Master Interface PAGEREF _Toc115855042 \h 5
2.5 RISC Processor Core PAGEREF _Toc115855043 \h 5
Operation PAGEREF _Toc115855044 \h 9
3.1 Software Example PAGEREF _Toc115855045 \h 9
3.2 Software Triggers PAGEREF _Toc115855046 \h 10
3.3 Program Memory Connection Options PAGEREF _Toc115855047 \h 10
3.4 Instruction Set Summary PAGEREF _Toc115855048 \h 10
3.4 Inconsistent Instruction Set Documentation PAGEREF _Toc115855049 \h 10
Registers PAGEREF _Toc115855050 \h 12
List of Registers PAGEREF _Toc115855051 \h 12
4.1 Xgate Module Control Register (XGMCTL) PAGEREF _Toc115855052 \h 13
4.2 Xgate Channel ID Register (XGCHID) PAGEREF _Toc115855053 \h 16
4.3 Xgate Stack Pointer Register (XGISPHI) PAGEREF _Toc115855054 \h 16
4.4 Xgate Stack Pointer Register (XGISPLO) PAGEREF _Toc115855055 \h 17
4.5 Xgate Vector Base Address Register (XGVBR) PAGEREF _Toc115855056 \h 17
4.6 Xgate Interrupt Flag Register 7 (XGIFR_7) PAGEREF _Toc115855057 \h 18
4.6 Xgate Software Trigger Register (XGSWT) PAGEREF _Toc115855058 \h 18
4.6 Xgate Semaphore Register (XGSEM) PAGEREF _Toc115855059 \h 19
4.6 Xgate Condition Code Register (XGCCR) PAGEREF _Toc115855060 \h 19
4.6 Xgate Program Counter Register (XGPC) PAGEREF _Toc115855061 \h 20
4.6 Xgate Register 1 (XGR1) PAGEREF _Toc115855062 \h 20
Clocks PAGEREF _Toc115855063 \h 22
IO Ports PAGEREF _Toc115855064 \h 23
6.1 WISHBONE Interface PAGEREF _Toc115855065 \h 24
6.2 Xgate signals PAGEREF _Toc115855066 \h 25
6.3 Xgate Core Parameters PAGEREF _Toc115855067 \h 27
Appendix A PAGEREF _Toc115855068 \h 28
Index PAGEREF _Toc115855069 \h 29
Introduction
The Xgate Co-processor Module, Xgate, is a 16 bit programmable RISC processor that is managed by a host CPU to reduce the host load in handling interrupts. Because the Xgate is user programmable there is a great deal of user control in how to preprocess data from peripheral modules. This module may be configured as a simple DMA controller to organize data such that the host only operates with whole messages and not individual words or bytes. The Xgate may also handle higher levels of messaging protocols than the peripheral hardware recognizes. Encryption algorithms are also supported by the instruction set.
The ideal application for the Xgate co-processor is in an ASIC environment where a specific host processor is required but the host as a standalone processor lacks sufficient computational resources to service the target application. Such a situation might occur in an existing application that has an extensive software base or the host processor has a significant history in similar applications. In this environment the Xgate provides the additional resources needed for the application while also providing the user programmability that may allow the ASIC to be used in other applications.
The use of an Xgate co-processor in an FPGA may not be as advantageous as in an ASIC environment because of the reprogramability of the FPGA hardware. Because the Xgate co-processor offers a generic solution to a variety of problems and the functionality can be changed by upgrading user software without changing the FPGA hardware implementation it may still be a valuable solution to certain problems. The use of the Xgate module may also reduce development time since the application can begin debug sooner and changes can be prototyped in user software.
FEATURES
Instruction set compatible with Freescale XGATE co-processor
Handles up to 127 interrupt inputs
Eight software triggerable interrupt channels.
Eight semaphore registers to coordinate host/Xgate shared memory.
Static synchronous design
Fully synthesizable
Architecture
The Xgate core is built around five primary blocks; the WISHBONE Slave Interface, WISHBONE Master Interface, the Control Registers, Interrupt Priority, and RISC Processor Core.
Fig. 2.1 Internal structure Xgate Core
2.1 WISHBONE Slave Interface
The host processor uses this bus to access the Xgate control and status registers. The WISHBONE Slave Interface isolates the Xgate functionality from the WISHBONE bus. This interface takes the bus specific signals and generates a generic set of control signals to drive the Xgate control registers. Isolating the WISHBONE bus should help promote Xgate module reusability by localizing the scope of changes needed to retarget the Xgate module to another bus environment.
2.2 Control Registers
This module receives the generic write signals from the WISHBONE Slave Interface and applies these signals to the registers that the host processor uses to control Xgate operation.
2.3 Interrupt Interface
The Interrupt Interface takes the input interrupts from other slave peripheral modules and prioritizes them for processing by the Xgate RISC Processor Core.
2.3.1 Simple Interrupt Interface
The current implementation uses the simplest interrupt interface with the least hardware and least functionality. This module takes the 127 interrupt inputs and does a simple encoding to generate the six bit bus that becomes the active channel select signal. The active interrupt input with the highest index number becomes the chosen channel select enable.
Because the Xgate module is in the signal path from the interrupt sources to the host CPU there must always be always be some code running in the Xgate module to activate the appropriate interrupt output to the CPU.
2.3.2 Bypass Interrupt Interface
This is a proposed functional improvement and is not currently implemented. This module will do the same basic interrupt encoding as the Simple Interrupt Interface except it will include the additional functionality to allow an interrupt input to be bypassed around the Xgate module and connected directly to the host CPU. This will eliminate the latency and software overhead when it is required for the host CPU to process some interrupts directly while still reserving the option to enable the Xgate module to preprocess those same interrupt sources at some other time. To implement this functionality additional control registers will need to be added to the WISHBONE slave interface.
2.3.3 Programmable Interrupt Interface
This is a proposed functional improvement and is not currently implemented. This module will include the functionality of the Bypass Interrupt Interface with additional functionality to allow interrupt priorities to be set by the host CPU. This will eliminate the latency and software overhead when it is required for the host CPU to process some interrupts directly while still reserving the option to enable the Xgate module to preprocess those same interrupt sources at some other time. To implement this functionality additional control registers will need to be added to the WISHBONE slave interface.
2.4 WISHBONE Master Interface
The Xgate module uses the WISHBONE Master Interface to access the shared memory space where its software code, data, and other slave peripheral registers may be accessed. The WISHBONE Master Interface isolates the Xgate functionality from the WISHBONE bus. This interface takes the bus specific signals and generates a generic set of control signals to drive the Xgate RISC Processor. Isolating the WISHBONE bus should help promote Xgate module reusability by localizing the scope of changes needed to retarget the Xgate module to another bus environment.
2.5 RISC Processor Core
The RISC Processor Core is the key element of the Xgate module. This module implements the Xgate instruction set.
2.5.1 Hardware Model
2.5.2 State Machine
Idle: The idle state is the condition where the xgate RISC processor waits to be enabled and an interrupt input to be activated.
Boot_1: State entered after an input interrupt is detected. Output the address stored in XGVBR + 2*XGCHID to fetch PC (Program Counter).
Boot_2: State entered after Boot_1. Load the PC and output the address of the variable pointer, XGVBR + 2*XGCHID + 2.
Boot_3: State entered after Boot_2. Load the variable pointer. Output the PC and prepare to load the first instruction.
Decode: In normal user operation this is the state entered after Boot_3 and the instruction is decoded and executed. For single cycle instructions, if Debug Mode is not active, then the Program Counter is incremented and the next instruction is loaded. For multi-cycle instructions one of the three instruction continue states is selected. If an RTS instruction is decoded then the state machine is returned to the Idle state to wait for the next change in XGCHID.
S_stall: Simple stall is the state that branch instructions use to change the PC when a change of flow is required. This state is also used for Store instructions.
W_stall: Word stall is the state Load instructions use to retrieve a word of RAM memory data.
B_stall: Byte stall is the state Load instructions use to retrieve a byte of RAM memory data.
Break: If the Decode state detects a BRK command then the Break state is entered. The RISC processor remains in the Break state till:
Single Step Command
XGEN is set to zero
XGCHID is set to zero
Break_2: After a Single Step Command is issued in the Break state the PC is incremented in this state.
Ld_inst: The Load Instruction state is used in debug mode to load the next instruction to be executed into the RISC instruction register.
Debug: debug is the state where the RISC processor waits for an input to execute the next command Exit conditions for this state are:
Single Step Command
XGEN is set to zero
XGCHID is set to zero
2.5.3 Semaphore Bit
Each semaphore bit is a simple state machine that is controlled by write commands from either the host or RISC processor. The first write command to set a semaphore bit takes control of the semaphore state until the bit is cleared by the setting processor. The host has priority if the host and RISC processor attempt to write the semaphore bit in the same clock cycle. Each processor has a different read view of the semaphore bit so it can determine if it has successfully set the bit.
Operation
The Xgate Module is a simple RISC CPU with an instruction set ..... then the cop_rst_o will become active to force a system reset.
The COP module also has the capability to generate an interrupt at a programmed number of cycles before the cop_rst_o initiates a system reset. This functionality is primarily intended as a debug feature.
A very readable article about watchdog timers and their use:
3.1 Software Example
The recommended software procedure for using the Xgate Module:
Initialize Xgate
Load RAM with Xgate software.
Set XGVBR register to base address of input interrupt vectors.
Enable Xgate by setting the XGE bit.
Enable host to accept interrupts.
Enable peripheral modules to output interrupts as required.
Normal Operation
Service Xgate interrupt requests as they are received by the host.
3.2 Software Triggers
3.3 Semaphore Bits
3.4 Program Memory Connection Options
3.5 Debug Mode
3.6 Instruction Set Summary
The RISC Processor Core is the key element of the Xgate module. This module implements the Xgate instruction set.
Function1514131211109876543210Return to Scheduler and otherBRK0000000000000000NOP0000000100000000
3.7 Inconsistent Instruction Set Documentation
The following instructions have problems in the Freescale documentation.
3.4.1 SUBL
Freescale Documentation:
V: Set if a twos complement overflow resulted from the 8-bit operation; cleared otherwise.
RD[15]old & !RD[15]new
C: Set if there is a carry from the bit 7 to bit 8 of the result; cleared otherwise.
!RD[15]old & RD[15]new
Xgate implementation:
For signed subtraction the rules for overflow are:
Negative number minus Positive number creates a Positive number OR
Positive number minus Negative number creates a Negative number
So the overflow calculation should be:
V = RD[7] & !IMM8[7] & !result[7] | !RD[7] & IMM8[7] & result[7]
The Carry calculation should be:
C = !RD[7] & IMM8[7] | !RD[7] & result[7] | IMM8[7] & result[7]
These calculations for setting the Carry and Overflow bits are also consistent with the calculations used to set the Carry and Overflow bits using the CMPL instruction.
3.4.2 ADDL
Freescale Documentation:
V: Set if a twos complement overflow resulted from the 8-bit operation; cleared otherwise.
RD[15]old & RD[15]new
C: Set if there is a carry from the bit 7 to bit 8 of the result; cleared otherwise.
RD[15]old & RD[15]new
Xgate implementation:
For signed addition the rules for overflow are:
Positive number plus Positive number creates a Negative number OR
Negative number plus Negative number creates a Positive number
So the overflow calculation should be:
V = !RD[7] & !IMM8[7] & result[7] | RD[7] & IMM8[7] & !result[7]
The Carry calculation should be:
C = !RD[7] & IMM8[7] | RD[7] & !result[7] | IMM8[7] & !result[7]
Registers
The Xgate Module has a WISHBONE bus interface configured for a 16-bit bus width 16-bit granularity.
This module address map will probably change to a byte addressable to be consistent with the byte addressable functionality of the Xgate RISC processor.
List of Registers
NameAddressWidthAccessDescriptionXGMCTL0x0016RWXgate Module Control RegisterXGCHID0x0116RWXgate Channel ID RegisterXGISPHI0x0216RWXgate Interrupt Stack Pointer HighXGISPLO0x0316RWXgate Interrupt Stack Pointer LowXGVBR0x0416RWXgate Vector Base AddressXGIF_70x0516RWXgate Interrupt Flag Register #7XGIF_60x0616RWXgate Interrupt Flag Register #6XGIF_50x0716RWXgate Interrupt Flag Register #5XGIF_40x0816RWXgate Interrupt Flag Register #4XGIF_30x0916RWXgate Interrupt Flag Register #3XGIF_20x0A16RWXgate Interrupt Flag Register #2XGIF_10x0B16RWXgate Interrupt Flag Register #1XGIF_00x0C16RWXgate Interrupt Flag Register #0XGSWT0x0D16RWXgate Software Trigger RegisterXGSEM0x0E16RWXgate Semaphore Register0x0F16RReservedXGCCR0x1016RWXgate Condition Code RegisterXGPC0x1116RWXgate Program Counter0x1216RReservedXGR10x1316RWXgate Register 1XGR20x1416RWXgate Register 2XGR30x1516RWXgate Register 3XGR40x1616RWXgate Register 4XGR50x1716RWXgate Register 5XGR60x1816RWXgate Register 6XGR70x1916RWXgate Register 7Table SEQ Table \* ARABIC 1: List of registers
4.1 Xgate Module Control Register (XGMCTL)
Bit #AccessDescription15WXGEM, XGE Mask The XGE bit can only be changed when the XGEM bit is set in the same register access.
0 No change allowed to XGE control bit.
1 Change allowed to XGE control bit.
Always reads as 0.14WXGFRZM, XGFRZ Mask The XGFRZ bit can only be changed when the XGEM bit is set in the same register access.
0 No change allowed to XGFRZ control bit.
1 Change allowed XGFRZ control bit.
Always reads as 0.13WXGDGBM, XGDGB Mask The XGDGB bit can only be changed when the XGDGBM bit is set in the same register access.
0 No change allowed to XGDBG control bit.
1 Change allowed to XGDBG Control bit.
Always reads as 0.12WXGSSM, XGSS Mask The XGSS bit can only be changed when the XGSSM bit is set in the same register access.
0 No change allowed to XGSS control bit.
1 Change allowed to XGSS control bit.
Always reads as 0.11WXGFACTM, XGFACT Mask The XGFACT bit can only be changed when the XGFACTM bit is set in the same register access.
0 No change allowed to XGFACT control bit.
1 Change allowed to XGFACT control bit.
Always reads as 0.10BRK_IRQ_ENM, BRK_IRQ_EN Mask The BRK_IRQ_EN bit can only be changed when the BRK_IRQ_ENM bit is set in the same register access.
0 No change allowed to BRK_IRQ_EN control bit.
1 Change allowed to BRK_IRQ_EN control bit.
Always reads as 0.9RWXGSWEIFM, XGSWEIF Mask The XGSWEIF bit can only be changed when the XGSWEIFM bit is set in the same register access.
0 No change allowed to XGSWEIF control bit.
1 Change allowed to XGSWEIF control bit.
Always reads as 0.8RWXGIEM, XGIE Mask The XGIE bit can only be changed when the XGIEM bit is set in the same register access.
0 No change allowed to XGIE control bit.
1 Change allowed to XGIE control bit.
Always reads as 0.7RWXGE, XG Enable The XGE bit can only be changed when the XGEM bit is set in the same register access.
0 The Xgate module is disabled. The currently active interrupt request will be completed and then no new interrupt processing requests will be accepted.
1 The Xgate module is enabled to start processing channel interrupts.6RWXGFRZ, XG Freeze Mode The XGE bit can only be changed when the XGEM bit is set in the same register access.
0 The Xgate module is disabled. The currently active channel interrupt will be completed and then no new interrupt channel processing requests will be accepted.
1 The Xgate module is enabled to start processing channel interrupts.5RWXGDBG, XG Debug Mode The XGDBG bit can only be changed when the XGDBGM bit is set in the same register access.
0 The Xgate module is not in DEBUG Mode.
1 The Xgate module is in DEBUG Mode. Along with writing to the XGGBG bit from the host interface DEBUG Mode can also be entered by executing the BRK instruction by the RISC Processor Core.4RWXGSS, XG Single Step The XGSS bit can only be changed when the XGSSM bit is set in the same register access.
0 The Xgate module is disabled. The currently active channel interrupt will be completed and then no new interrupt channel processing requests will be accepted.
1 Write - Xgate module should execute a single RISC instruction. Read A RISC instruction is being processed.3RWXGFACT, XG Fake Activity The XGFACT bit can only be changed when the XGFACTM bit is set in the same register access.
0 The Xgate module is disabled. The currently active channel interrupt will be completed and then no new interrupt channel processing requests will be accepted.
1 The Xgate module is enabled to start processing channel interrupts.2RWBRK_IRQ_EN, Break Interrupt Enable The BRK_IRQ_EN bit can only be changed when the BRK_IRQ_EN M bit is set in the same register access.
0 The Xgate module is operating in a mode compatible with the Freescale XGATE module. BRK instructions do not generate an Xgate error interrupt output.
1 The Xgate module is enabled to output an error interrupt whenever a BRK command is encountered. Set this bit whenever no BRK commands are expected to be used in the software.1RWXGSWEIF, XG Software Error Interrupt Flag The XGSWEIF bit can only be changed when the XGSWEIFM bit is set in the same register access.
0 The Xgate module is operating correctly. Writing 0 has no effect.
1 The Xgate RISC processor has detected an error condition. Writing 1 will clear a set XGSWEIF bit and terminate the current interrupt process. The Xgate module will go to an IDLE state if no other interrupt inputs are active.0RWXGIE, XG Interrupt Enable The XGIE bit can only be changed when the XGEM bit is set in the same register access.
0 All Xgate module interrupt outputs are disabled.
1 All Xgate module interrupt outputs are enabled.Reset Value: XGMCTL: 0004hTable SEQ Table \* ARABIC 2: CNTRL Register Bits
4.2 Xgate Channel ID Register (XGCHID)
Bit #AccessDescription15:7RReserved, write zeros for future compatibility.6:0RWXGCHID, XG Channel ID The XGCHID register reflects the value of the current interrupt channel being processed.
0 No interrupt currently being processed.
1 The encoded value of the input interrupt currently being processed.
The XGCHID can only be written in DEBUG Mode. When a value is written to the XGCHID register the RISC Processor Core will start executing the code associated with that interrupt input.Reset Value:
XGCHID: 0000h
Table 4: Channel ID Register Bits
4.3 Xgate Stack Pointer Register (XGISPHI)
Bit #AccessDescription15:0RWXGISPHI, Read returns the current state of the COP Watchdog Counter.
Writes to the CNT register access the COP service words. To reset the COP Watchdog Counter to the TOUT_VAL state two specific service words must be written in the correct order to prevent a COP reset.Reset Value:
XGISP74: 0000h
Table 5: XGIPS74 Register Bits
4.4 Xgate Stack Pointer Register (XGISPLO)
Bit #AccessDescription15:0RWXGISPLO, Read returns the current state of the COP Watchdog Counter.
Writes to the CNT register access the COP service words. To reset the COP Watchdog Counter to the TOUT_VAL state two specific service words must be written in the correct order to prevent a COP reset.Reset Value:
XGISP31: 0000h
Table 5: XGIPS31 Register Bits
4.5 Xgate Vector Base Address Register (XGVBR)
Bit #AccessDescription15:1RWXGVBR, Sets the vector base address that the Xgate RISC Core uses to determine where in the memory map the code and data space is for a specific interrupt is reserved.Reset Value:
XGVBR: FE00h
Table 5: XGVBR Register Bits
4.6 Xgate Interrupt Flag Register 7 (XGIFR_7)
The bits in this register reflect the state of interrupts that are being output from the Xgate module to the host CPU. A bit is set by the Xgate module with the SIF instruction usually at the end of a process and the host CPU clears the XGIF bit as part of its interrupt service routine.
Clear the interrupt output by writing a 1 to the corresponding XGIF register bit.
The highest numbered interrupt is in the MSB position of the register bank.
Some bits in this register may be unimplemented in a specific hardware design based on the setting of the MAX_CHANNEL parameter and will always read as 0.
Bit #AccessDescription15:0RWXGIF_127 XGIF_112
0 No interrupt.
1 Interrupt output active.Reset Value:
XGIFR_7: 0000h
Table 5: XGIF_7 Register Bits
4.6 Xgate Software Trigger Register (XGSWT)
Bit #AccessDescription15:8WXGSWTM[7:0], Read returns the current state of the COP Watchdog Counter.
XGSWTM, XGSWT Mask The XGSWT bit can only be changed when the XGSWTM bit is set in the same register access.
0 No change allowed to XGSWT control bit.
1 Change allowed to XGSWT control bit.
Always reads as 0.7:0RWXGSWT[7:0], XG Software Trigger The XGSWT bit can only be changed when the XGSWTM bit is set in the same register access.
0 The Xgate module is disabled. The currently active interrupt request will be completed and then no new interrupt processing requests will be accepted.
1 The Xgate module is enabled to start processing channel interrupts.Reset Value:
XGSWT: 0000h
Table 5: XGSWT Register Bits
4.6 Xgate Semaphore Register (XGSEM)
Bit #AccessDescription15:8WXGSEMM, XGSEM Mask The XGSEM bit can only be changed when the XGSEMM bit is set in the same register access.
0 No change allowed to XGSEM control bit.
1 Change allowed to XGSEM control bit.
Always reads as 0.7:0RWXGSWT[7:0], XG Software Trigger The XGSWT bit can only be changed when the XGSWTM bit is set in the same register access.
0 The semaphore bit is either unlocked or locked by the Xgate module. If the host attempts to set the bit by writing a 1 and a subsequent read of the bit returns a 0 the bit is locked by the Xgate module.
1 The semaphore bit is locked by the host processor. The host writes a 0 to clear the bit and unlock the semaphore.Reset Value:
XGSEM: 0000h
Table 5: XGSEM Register Bits
4.6 Xgate Condition Code Register (XGCCR)
Bit #AccessDescription15:4RReserved, write zeros for future compatibility.3RWXGN, Xgate Negative Reflects the current state of the Negative bit of the Xgate condition code register. 2RWXGZ, Xgate Zero Reflects the current state of the Zero bit of the Xgate condition code register.1RWXGV, Xgate Overflow Reflects the current state of the Overflow bit of the Xgate condition code register.0RWXGC, Xgate Carry Reflects the current state of the Carry bit of the Xgate condition code register.Reset Value:
XGCCR: 0000h
Table 5: XGCCR Register Bits
4.6 Xgate Program Counter Register (XGPC)
Bit #AccessDescription15:0RWXGPC, Read returns the current state of the Xgate Program Counter.
Writes to the XGPC register can only be done in Debug Mode.Reset Value:
XGPC: 0000h
Table 5: XGPC Register Bits
4.6 Xgate Register 1 (XGR1)
Bit #AccessDescription15:0RWXGR1, Read returns the current state of the Xgate General Purpose Register 1.
Writes to the XGR1 register can only be done in Debug Mode.Reset Value:
XGR1: 0000h
Table 5: XGR1 Register Bits
Clocks
NameSourceRates (MHz)RemarksDescriptionMaxMinResolutionwbs_clk_iSystem200--Master clock for all COP bus registers. Positive edge active.System clock.risc_clkSystemRISC Processor clockTable SEQ Table \* ARABIC 3: List of clocks
The wbs_clk_i has no timing constraints based on the RTL implementation although there may be constrains applied for synthesis results to be compatible with the target physical implementation. If the Xgate is targeted for an ASIC implementation then [wbs_clk_i] should be used as the scan clock, any clock multiplexing required to make [wbs_clk_i] the scan clock should be done at the system level external to the Xgate Module.
The risc_clk is the clock used to run the Xgate RISC processor submodule. The frequency of this clock should be the same as or 2X the frequency of the wbs_clk_i input. The risc_clk input is assumed to be in phase with the wbs_clk_i input.
IO Ports
PortWidthDirectionDescriptionwbs_clk_i1InputWISHBONE Bus Clock Input, Master Clockwbs_rst_i1InputWISHBONE Synchronous Resetwbs_adr_i3InputWISHBONE Lower address bitswbs_dat_i16InputWISHBONE Bus Datawbs_dat_o16OutputWISHBONE Bus Datawbs_we_i1InputWISHBONE Write enablewbs_stb_i1InputWISHBONE Strobe signal/Core selectwbs_cyc_i1InputWISHBONE Valid bus cyclewbs_sel_i2InputWISHBONE Data Bus Byte Selectwbs_ack_o1OutputWISHBONE Bus cycle acknowledge xgif_o128OutputXgate Interrupt signalxgswt8OutputXgate software triggerchan_req_i128InputXgate Interrupt requestrisc_clk1InputClock for RISC submodule1Inputdebug_mode_i1InputSystem is in DEBUG Mode1Inputarst_i1InputAsynchronous Resetscantestmode_i1InputScan Test Mode EnableTable SEQ Table \* ARABIC 4: List of IO ports
6.1 WISHBONE Interface
The core features a WISHBONE RevB.3 compliant WISHBONE Classic interface that operates in SLAVE mode. All output signals are registered. Each access takes 2 clock cycles. To limit a WISHBONE access to just two clock cycles the following synthesis rules should be used:
Single cycle timing for wbs_cyc_i and wbs_stb_i
Two cycle timing for wbs_adr_i, wbs_data_i, and wbs_data_o. (Single cycle timing could be used but it would be a waste of resources to meet an over constrained timing path.)
Note: Use the SINGLE_CYCLE parameter to do a WISHBONE bus access in one clock cycle.
WISHBONE DATASHEETDescriptionSpecificationGeneral description:8-bit SLAVESupported Cycles:SLAVE, READ/WRITEData port, size:
Data port, granularity:
Data port, maximum operand size:
Data transfer ordering:
Data transfer sequencing:Default: 16, option 8 bit
Default: 16, option to match 8 bit port size
Supported signal list and cross reference to equivalent WISHBONE signals:Signal NameWISHBONE Equiv.wbs_clk_iCLK_Iwbs_rst_iRST_Iwbs_adr_iADR_I()wbs_dat_iDAT_I()wbs_dat_oDAT_O()wbs_we_iWE_Iwbs_stb_iSTB_Iwbs_cyc_iCYC_Iwbs_sel_iSEL_Iwbs_ack_oACK_O
6.1.1 wbs_rst_i
The synchronous reset signal has a minimum pulse width requirement of one [wbs_clk_i] clock period. It will take two [wbs_clk_i] clock cycles for all registers in the COP Module to initialize. Also see information on pin [arst_i]. It is assumed that elsewhere in the system cop_rst_o will be ORed with this signal and it will be active for some time during and after a COP watchdog timeout.
6.1.2 wbs_adr_i
Connections to the WISHBONE address pin will depend on the size of the WISHBONE data bus that is set by the DWIDTH parameter. If DWIDTH=8 the all address pins should be connected, if DWIDTH=16 then [wbs_adr_i(2)] should be tied low.
6.1.3 wbs_sel_i
The [wbs_sel_i] is the WISHBONE byte lane select signal. It is currently unimplemented in the PIT module and should be tied hi.
6.2 Xgate signals
6.2.1 xgif[127:0]
The Xgate output signal. This output is the result of executing the SIF command by the Xgate RISC processor. The normal connection is to the interrupt inputs of the host processor.
6.2.2 chan_req_i[127:0]
These signals are the interrupt inputs from the prepherial modules that the Xgate services. The eight outputs of the xgswt bus may also connect to these inputs.
6.2.3 xgswt[7:0]
The [por_reset_i] signal is active low. This signal is used to initialize a limited number flip-flops that need to maintain state when [arst_i] or [wb_rst_i] are active. A separate reset signal is required for these flip_flops because it is assumed that [cop_rst_o] will effect [arst_i] and [wb_rst_i] and may cause a shortening of the [cop_rst_o] pulse width because of a combinational feedback path.
6.2.4 arst_i
The signal [arst_i] is an asynchronous reset signal that goes to all flops in the COP. It is provided for FPGA implementations and test methodologies that require this function for initialization. Using [arst_i] instead of [wb_rst_i] can result in lower cell-usage and higher performance for a FPGAs implementation because the standard FPGA cell already provides a dedicated asynchronous reset path. Using [wb_rst_i] for an ASIC implementation might synthesize to a smaller module because smaller non_reset flops can be used. Use either [arst_i] or [wb_rst_i], tie the other to a negated state. The active level of [arst_i] is determined by the parameter ARST_LVL that defaults to active low.
6.2.6 stop_mode_i
The Watchdog Counter can be frozen in its current state if this signal is active and the STOP_ENA bit is set to zero. If there is no stop mode signal available from the system then this input signal should be tied low.
6.2.7 wait_mode_i
The Watchdog Counter can be frozen in its current state if this signal is active and the WAIT_ENA bit is set to zero. If there is no stop mode signal available from the system then this input signal should be tied low.
6.2.8 debug_mode_i
The Watchdog Counter can be frozen in its current state if this signal is active and the DEBUG_ENA bit is set to zero. If there is no stop mode signal available from the system then this input signal should be tied low.
6.2.9 scantestmode_i
The [scantestmode_i] input is an optional signal used to put the module into scan test mode. When [scantestmode_i] is active the [startup_osc_clk_i] is replaced by the [wb_clk_i] clock so all register are clocked by a common clock source.
6.3 Xgate Core Parameters
ParameterTypeDefaultDescriptionARST_LVLBit1b0Asynchronous reset levelMAX_CHANNELInteger127Number of input an output interruptsSINGLE_CYCLEBit1b0WISHBONE wait state
6.3.1 ARST_LVL
The asynchronous reset level can be set to either active high (1b1) or active low (1b0).
Allowed values: 1b0, 1b1
6.3.2 MAX_CHANNEL
The maximun index value for chan_req_i and xgif.
Allowed values: any integer value between 1 and 127
6.3.3 SINGLE_CYCLE
The default operation of the COP WISHBONE bus interface is to insert one wait state by delaying the assertion of the wb_ack_o by one wb_clk_i period. Setting the SINGLE_CYCLE parameter generates the wb_ack_o combinationaly so a WISHBONE bus cycle can be completed in one wb_clk_i period.
Allowed values: 1b0, 1b1
Name
[This section may be added to outline different specifications.]
[This section contains an alphabetical list of helpful document entries with their corresponding page numbers.]
OpenCores TITLE \* MERGEFORMAT Xgate Co-Processor (Xgate) Module DATE \* MERGEFORMAT 10/7/09
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.1 Preliminary PAGE ii
OpenCores TITLE \* MERGEFORMAT Xgate Co-Processor (Xgate) Module DATE \* MERGEFORMAT 10/7/09
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.1 Preliminary PAGE iv
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.1 Preliminary PAGE 29 of SECTIONPAGES29
wrt_semp=1
wrt_semp=0
CSEM
SSEM
WISHBONE Master Interface
Interrupt Priority
RISC Core
Command Registers
WISHBONE Slave Interface
chan_req_i
xgif_o
Figure STYLEREF 2 \s 2 SEQ Figure \* ARABIC \s 2 1 Internal Structure Xgate Core
debug
ld_inst
break_2
break
b_stall
s_stall
BRK
RTS
Load instruction
Increment PC
Load instruction
Increment PC
Load initial variable pointer (R1)
Output PC
Load PC
Output address for initial variable pointer fetch
Output address for PC initial address data fetch
boot_3
decode
w_stall
boot_2
boot_1
idle
3
2
1
0
15
15
0
0
Condition Code Register
Program Counter
General Purpose Registers
N
V
Z
C
15
Programmers Model
PC
R7
R6
R5
R4
R3
R2
R1 Variable Address
R0=0
no_lock
risc_lock
host_lock
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Xgate Co-Processor (xgate) Specification
Author: Robert Hayes
rehayes@opencores.org
Rev. 0.1
TIME \@ "MMMM d, yyyy" October 19, 2009
This page has been intentionally left blank.
Revision History
Rev.DateAuthorDescription 0.109/29/09Robert Hayes
Contents
TOC \t "Heading 3,2,Index,1,Appendix A,1,Heading 2 name,1,Appendix B,1" Introduction PAGEREF _Toc115855036 \h 1
FEATURES PAGEREF _Toc115855037 \h 1
Architecture PAGEREF _Toc115855038 \h 3
2.1 WISHBONE Slave Interface PAGEREF _Toc115855039 \h 4
2.2 Control Registers PAGEREF _Toc115855040 \h 4
2.3 Interrupt Interface PAGEREF _Toc115855041 \h 4
2.4 WISHBONE Master Interface PAGEREF _Toc115855042 \h 5
2.5 RISC Processor Core PAGEREF _Toc115855043 \h 5
Operation PAGEREF _Toc115855044 \h 9
3.1 Software Example PAGEREF _Toc115855045 \h 9
3.2 Software Triggers PAGEREF _Toc115855046 \h 10
3.3 Program Memory Connection Options PAGEREF _Toc115855047 \h 10
3.4 Instruction Set Summary PAGEREF _Toc115855048 \h 10
3.4 Inconsistent Instruction Set Documentation PAGEREF _Toc115855049 \h 10
Registers PAGEREF _Toc115855050 \h 12
List of Registers PAGEREF _Toc115855051 \h 12
4.1 Xgate Module Control Register (XGMCTL) PAGEREF _Toc115855052 \h 13
4.2 Xgate Channel ID Register (XGCHID) PAGEREF _Toc115855053 \h 16
4.3 Xgate Stack Pointer Register (XGISPHI) PAGEREF _Toc115855054 \h 16
4.4 Xgate Stack Pointer Register (XGISPLO) PAGEREF _Toc115855055 \h 17
4.5 Xgate Vector Base Address Register (XGVBR) PAGEREF _Toc115855056 \h 17
4.6 Xgate Interrupt Flag Register 7 (XGIFR_7) PAGEREF _Toc115855057 \h 18
4.6 Xgate Software Trigger Register (XGSWT) PAGEREF _Toc115855058 \h 18
4.6 Xgate Semaphore Register (XGSEM) PAGEREF _Toc115855059 \h 19
4.6 Xgate Condition Code Register (XGCCR) PAGEREF _Toc115855060 \h 19
4.6 Xgate Program Counter Register (XGPC) PAGEREF _Toc115855061 \h 20
4.6 Xgate Register 1 (XGR1) PAGEREF _Toc115855062 \h 20
Clocks PAGEREF _Toc115855063 \h 22
IO Ports PAGEREF _Toc115855064 \h 23
6.1 WISHBONE Interface PAGEREF _Toc115855065 \h 24
6.2 Xgate signals PAGEREF _Toc115855066 \h 25
6.3 Xgate Core Parameters PAGEREF _Toc115855067 \h 27
Appendix A PAGEREF _Toc115855068 \h 28
Index PAGEREF _Toc115855069 \h 29
Introduction
The Xgate Co-processor Module, Xgate, is a 16 bit programmable RISC processor that is managed by a host CPU to reduce the host load in handling interrupts. Because the Xgate is user programmable there is a great deal of user control in how to preprocess data from peripheral modules. This module may be configured as a simple DMA controller to organize data such that the host only operates with whole messages and not individual words or bytes. The Xgate may also handle higher levels of messaging protocols than the peripheral hardware recognizes. Encryption algorithms are also supported by the instruction set.
The ideal application for the Xgate co-processor is in an ASIC environment where a specific host processor is required but the host as a standalone processor lacks sufficient computational resources to service the target application. Such a situation might occur in an existing application that has an extensive software base or the host processor has a significant history in similar applications. In this environment the Xgate provides the additional resources needed for the application while also providing the user programmability that may allow the ASIC to be used in other applications.
The use of an Xgate co-processor in an FPGA may not be as advantageous as in an ASIC environment because of the reprogramability of the FPGA hardware. Because the Xgate co-processor offers a generic solution to a variety of problems and the functionality can be changed by upgrading user software without changing the FPGA hardware implementation it may still be a valuable solution to certain problems. The use of the Xgate module may also reduce development time since the application can begin debug sooner and changes can be prototyped in user software.
FEATURES
Instruction set compatible with Freescale XGATE co-processor
Handles up to 127 interrupt inputs
Eight software triggerable interrupt channels.
Eight semaphore registers to coordinate host/Xgate shared memory.
Static synchronous design
Fully synthesizable
Architecture
The Xgate core is built around five primary blocks; the WISHBONE Slave Interface, WISHBONE Master Interface, the Control Registers, Interrupt Priority, and RISC Processor Core.
Fig. 2.1 Internal structure Xgate Core
2.1 WISHBONE Slave Interface
The host processor uses this bus to access the Xgate control and status registers. The WISHBONE Slave Interface isolates the Xgate functionality from the WISHBONE bus. This interface takes the bus specific signals and generates a generic set of control signals to drive the Xgate control registers. Isolating the WISHBONE bus should help promote Xgate module reusability by localizing the scope of changes needed to retarget the Xgate module to another bus environment.
2.2 Control Registers
This module receives the generic write signals from the WISHBONE Slave Interface and applies these signals to the registers that the host processor uses to control Xgate operation.
2.3 Interrupt Interface
The Interrupt Interface takes the input interrupts from other slave peripheral modules and prioritizes them for processing by the Xgate RISC Processor Core.
2.3.1 Simple Interrupt Interface
The current implementation uses the simplest interrupt interface with the least hardware and least functionality. This module takes the 127 interrupt inputs and does a simple encoding to generate the six bit bus that becomes the active channel select signal. The active interrupt input with the highest index number becomes the chosen channel select enable.
Because the Xgate module is in the signal path from the interrupt sources to the host CPU there must always be always be some code running in the Xgate module to activate the appropriate interrupt output to the CPU.
2.3.2 Bypass Interrupt Interface
This is a proposed functional improvement and is not currently implemented. This module will do the same basic interrupt encoding as the Simple Interrupt Interface except it will include the additional functionality to allow an interrupt input to be bypassed around the Xgate module and connected directly to the host CPU. This will eliminate the latency and software overhead when it is required for the host CPU to process some interrupts directly while still reserving the option to enable the Xgate module to preprocess those same interrupt sources at some other time. To implement this functionality additional control registers will need to be added to the WISHBONE slave interface.
2.3.3 Programmable Interrupt Interface
This is a proposed functional improvement and is not currently implemented. This module will include the functionality of the Bypass Interrupt Interface with additional functionality to allow interrupt priorities to be set by the host CPU. This will eliminate the latency and software overhead when it is required for the host CPU to process some interrupts directly while still reserving the option to enable the Xgate module to preprocess those same interrupt sources at some other time. To implement this functionality additional control registers will need to be added to the WISHBONE slave interface.
2.4 WISHBONE Master Interface
The Xgate module uses the WISHBONE Master Interface to access the shared memory space where its software code, data, and other slave peripheral registers may be accessed. The WISHBONE Master Interface isolates the Xgate functionality from the WISHBONE bus. This interface takes the bus specific signals and generates a generic set of control signals to drive the Xgate RISC Processor. Isolating the WISHBONE bus should help promote Xgate module reusability by localizing the scope of changes needed to retarget the Xgate module to another bus environment.
2.5 RISC Processor Core
The RISC Processor Core is the key element of the Xgate module. This module implements the Xgate instruction set.
2.5.1 Hardware Model
2.5.2 State Machine
Idle: The idle state is the condition where the xgate RISC processor waits to be enabled and an interrupt input to be activated.
Boot_1: State entered after an input interrupt is detected. Output the address stored in XGVBR + 2*XGCHID to fetch PC (Program Counter).
Boot_2: State entered after Boot_1. Load the PC and output the address of the variable pointer, XGVBR + 2*XGCHID + 2.
Boot_3: State entered after Boot_2. Load the variable pointer. Output the PC and prepare to load the first instruction.
Decode: In normal user operation this is the state entered after Boot_3 and the instruction is decoded and executed. For single cycle instructions, if Debug Mode is not active, then the Program Counter is incremented and the next instruction is loaded. For multi-cycle instructions one of the three instruction continue states is selected. If an RTS instruction is decoded then the state machine is returned to the Idle state to wait for the next change in XGCHID.
S_stall: Simple stall is the state that branch instructions use to change the PC when a change of flow is required. This state is also used for Store instructions.
W_stall: Word stall is the state Load instructions use to retrieve a word of RAM memory data.
B_stall: Byte stall is the state Load instructions use to retrieve a byte of RAM memory data.
Break: If the Decode state detects a BRK command then the Break state is entered. The RISC processor remains in the Break state till:
Single Step Command
XGEN is set to zero
XGCHID is set to zero
Break_2: After a Single Step Command is issued in the Break state the PC is incremented in this state.
Ld_inst: The Load Instruction state is used in debug mode to load the next instruction to be executed into the RISC instruction register.
Debug: debug is the state where the RISC processor waits for an input to execute the next command Exit conditions for this state are:
Single Step Command
XGEN is set to zero
XGCHID is set to zero
2.5.3 Semaphore Bit
Each semaphore bit is a simple state machine that is controlled by write commands from either the host or RISC processor. The first write command to set a semaphore bit takes control of the semaphore state until the bit is cleared by the setting processor. The host has priority if the host and RISC processor attempt to write the semaphore bit in the same clock cycle. Each processor has a different read view of the semaphore bit so it can determine if it has successfully set the bit.
// Semaphore states
NO_LOCK = 2'b00
RISC_LOCK = 2'b10
HOST_LOCK = 2'b11
These are the states for the semaphore bits. Only three of the four possible states are required to cover all the real things that can happen. For decoding the state of a semaphore bit the MSB is equivalent to "locked" and the LSB isequivalentto which processor is the one that owns the lock. Therefore state 2'b01 doesn't make sense because it implies there is no "lock" but the bit is owned by the host. In terms of the actual logic it probably makes little if any difference how the states are encoded but from the mental perspective it maybe helpful in understanding and debug to have the individual bits of the state be connected to a unique meaning.
Operation
The Xgate Module is a simple RISC CPU with an instruction set ..... then the cop_rst_o will become active to force a system reset.
The COP module also has the capability to generate an interrupt at a programmed number of cycles before the cop_rst_o initiates a system reset. This functionality is primarily intended as a debug feature.
A very readable article about watchdog timers and their use:
3.1 Software Example
The recommended software procedure for using the Xgate Module:
Initialize Xgate
Load RAM with Xgate software.
Set XGVBR register to base address of input interrupt vectors.
Enable Xgate by setting the XGE bit.
Enable host to accept interrupts.
Enable peripheral modules to output interrupts as required.
Normal Operation
Service Xgate interrupt requests as they are received by the host.
3.2 Software Triggers
3.3 Semaphore Bits
3.4 Program Memory Connection Options
3.5 Debug Mode
3.6 Instruction Set Summary
The RISC Processor Core is the key element of the Xgate module. This module implements the Xgate instruction set.
Function1514131211109876543210Return to Scheduler and otherBRK0000000000000000NOP0000000100000000
3.7 Inconsistent Instruction Set Documentation
The following instructions have problems in the Freescale documentation.
3.4.1 SUBL
Freescale Documentation:
V: Set if a twos complement overflow resulted from the 8-bit operation; cleared otherwise.
RD[15]old & !RD[15]new
C: Set if there is a carry from the bit 7 to bit 8 of the result; cleared otherwise.
!RD[15]old & RD[15]new
Xgate implementation:
For signed subtraction the rules for overflow are:
Negative number minus Positive number creates a Positive number OR
Positive number minus Negative number creates a Negative number
So the overflow calculation should be:
V = RD[7] & !IMM8[7] & !result[7] | !RD[7] & IMM8[7] & result[7]
The Carry calculation should be:
C = !RD[7] & IMM8[7] | !RD[7] & result[7] | IMM8[7] & result[7]
These calculations for setting the Carry and Overflow bits are also consistent with the calculations used to set the Carry and Overflow bits using the CMPL instruction.
3.4.2 ADDL
Freescale Documentation:
V: Set if a twos complement overflow resulted from the 8-bit operation; cleared otherwise.
RD[15]old & RD[15]new
C: Set if there is a carry from the bit 7 to bit 8 of the result; cleared otherwise.
RD[15]old & RD[15]new
Xgate implementation:
For signed addition the rules for overflow are:
Positive number plus Positive number creates a Negative number OR
Negative number plus Negative number creates a Positive number
So the overflow calculation should be:
V = !RD[7] & !IMM8[7] & result[7] | RD[7] & IMM8[7] & !result[7]
The Carry calculation should be:
C = !RD[7] & IMM8[7] | RD[7] & !result[7] | IMM8[7] & !result[7]
Registers
The Xgate Module has a WISHBONE bus interface configured for a 16-bit bus width 16-bit granularity.
This module address map will probably change to a byte addressable to be consistent with the byte addressable functionality of the Xgate RISC processor.
List of Registers
NameAddressWidthAccessDescriptionXGMCTL0x0016RWXgate Module Control RegisterXGCHID0x0116RWXgate Channel ID RegisterXGISPHI0x0216RWXgate Interrupt Stack Pointer HighXGISPLO0x0316RWXgate Interrupt Stack Pointer LowXGVBR0x0416RWXgate Vector Base AddressXGIF_70x0516RWXgate Interrupt Flag Register #7XGIF_60x0616RWXgate Interrupt Flag Register #6XGIF_50x0716RWXgate Interrupt Flag Register #5XGIF_40x0816RWXgate Interrupt Flag Register #4XGIF_30x0916RWXgate Interrupt Flag Register #3XGIF_20x0A16RWXgate Interrupt Flag Register #2XGIF_10x0B16RWXgate Interrupt Flag Register #1XGIF_00x0C16RWXgate Interrupt Flag Register #0XGSWT0x0D16RWXgate Software Trigger RegisterXGSEM0x0E16RWXgate Semaphore Register0x0F16RReservedXGCCR0x1016RWXgate Condition Code RegisterXGPC0x1116RWXgate Program Counter0x1216RReservedXGR10x1316RWXgate Register 1XGR20x1416RWXgate Register 2XGR30x1516RWXgate Register 3XGR40x1616RWXgate Register 4XGR50x1716RWXgate Register 5XGR60x1816RWXgate Register 6XGR70x1916RWXgate Register 7Table SEQ Table \* ARABIC 1: List of registers
4.1 Xgate Module Control Register (XGMCTL)
Bit #AccessDescription15WXGEM, XGE Mask The XGE bit can only be changed when the XGEM bit is set in the same register access.
0 No change allowed to XGE control bit.
1 Change allowed to XGE control bit.
Always reads as 0.14WXGFRZM, XGFRZ Mask The XGFRZ bit can only be changed when the XGEM bit is set in the same register access.
0 No change allowed to XGFRZ control bit.
1 Change allowed XGFRZ control bit.
Always reads as 0.13WXGDGBM, XGDGB Mask The XGDGB bit can only be changed when the XGDGBM bit is set in the same register access.
0 No change allowed to XGDBG control bit.
1 Change allowed to XGDBG Control bit.
Always reads as 0.12WXGSSM, XGSS Mask The XGSS bit can only be changed when the XGSSM bit is set in the same register access.
0 No change allowed to XGSS control bit.
1 Change allowed to XGSS control bit.
Always reads as 0.11WXGFACTM, XGFACT Mask The XGFACT bit can only be changed when the XGFACTM bit is set in the same register access.
0 No change allowed to XGFACT control bit.
1 Change allowed to XGFACT control bit.
Always reads as 0.10BRK_IRQ_ENM, BRK_IRQ_EN Mask The BRK_IRQ_EN bit can only be changed when the BRK_IRQ_ENM bit is set in the same register access.
0 No change allowed to BRK_IRQ_EN control bit.
1 Change allowed to BRK_IRQ_EN control bit.
Always reads as 0.9RWXGSWEIFM, XGSWEIF Mask The XGSWEIF bit can only be changed when the XGSWEIFM bit is set in the same register access.
0 No change allowed to XGSWEIF control bit.
1 Change allowed to XGSWEIF control bit.
Always reads as 0.8RWXGIEM, XGIE Mask The XGIE bit can only be changed when the XGIEM bit is set in the same register access.
0 No change allowed to XGIE control bit.
1 Change allowed to XGIE control bit.
Always reads as 0.7RWXGE, XG Enable The XGE bit can only be changed when the XGEM bit is set in the same register access.
0 The Xgate module is disabled. The currently active interrupt request will be completed and then no new interrupt processing requests will be accepted.
1 The Xgate module is enabled to start processing channel interrupts.6RWXGFRZ, XG Freeze Mode The XGE bit can only be changed when the XGEM bit is set in the same register access.
0 The Xgate module is disabled. The currently active channel interrupt will be completed and then no new interrupt channel processing requests will be accepted.
1 The Xgate module is enabled to start processing channel interrupts.5RWXGDBG, XG Debug Mode The XGDBG bit can only be changed when the XGDBGM bit is set in the same register access.
0 The Xgate module is not in DEBUG Mode.
1 The Xgate module is in DEBUG Mode. Along with writing to the XGGBG bit from the host interface DEBUG Mode can also be entered by executing the BRK instruction by the RISC Processor Core.4RWXGSS, XG Single Step The XGSS bit can only be changed when the XGSSM bit is set in the same register access.
0 The Xgate module is disabled. The currently active channel interrupt will be completed and then no new interrupt channel processing requests will be accepted.
1 Write - Xgate module should execute a single RISC instruction. Read A RISC instruction is being processed.3RWXGFACT, XG Fake Activity The XGFACT bit can only be changed when the XGFACTM bit is set in the same register access.
0 The Xgate module is disabled. The currently active channel interrupt will be completed and then no new interrupt channel processing requests will be accepted.
1 The Xgate module is enabled to start processing channel interrupts.2RWBRK_IRQ_EN, Break Interrupt Enable The BRK_IRQ_EN bit can only be changed when the BRK_IRQ_EN M bit is set in the same register access.
0 The Xgate module is operating in a mode compatible with the Freescale XGATE module. BRK instructions do not generate an Xgate error interrupt output.
1 The Xgate module is enabled to output an error interrupt whenever a BRK command is encountered. Set this bit whenever no BRK commands are expected to be used in the software.1RWXGSWEIF, XG Software Error Interrupt Flag The XGSWEIF bit can only be changed when the XGSWEIFM bit is set in the same register access.
0 The Xgate module is operating correctly. Writing 0 has no effect.
1 The Xgate RISC processor has detected an error condition. Writing 1 will clear a set XGSWEIF bit and terminate the current interrupt process. The Xgate module will go to an IDLE state if no other interrupt inputs are active.0RWXGIE, XG Interrupt Enable The XGIE bit can only be changed when the XGEM bit is set in the same register access.
0 All Xgate module interrupt outputs are disabled.
1 All Xgate module interrupt outputs are enabled.Reset Value: XGMCTL: 0004hTable SEQ Table \* ARABIC 2: CNTRL Register Bits
4.2 Xgate Channel ID Register (XGCHID)
Bit #AccessDescription15:7RReserved, write zeros for future compatibility.6:0RWXGCHID, XG Channel ID The XGCHID register reflects the value of the current interrupt channel being processed.
0 No interrupt currently being processed.
1 The encoded value of the input interrupt currently being processed.
The XGCHID can only be written in DEBUG Mode. When a value is written to the XGCHID register the RISC Processor Core will start executing the code associated with that interrupt input.Reset Value:
XGCHID: 0000h
Table 4: Channel ID Register Bits
4.3 Xgate Stack Pointer Register (XGISPHI)
Bit #AccessDescription15:0RWXGISPHI, Read returns the current state of the COP Watchdog Counter.
Writes to the CNT register access the COP service words. To reset the COP Watchdog Counter to the TOUT_VAL state two specific service words must be written in the correct order to prevent a COP reset.Reset Value:
XGISP74: 0000h
Table 5: XGIPS74 Register Bits
4.4 Xgate Stack Pointer Register (XGISPLO)
Bit #AccessDescription15:0RWXGISPLO, Read returns the current state of the COP Watchdog Counter.
Writes to the CNT register access the COP service words. To reset the COP Watchdog Counter to the TOUT_VAL state two specific service words must be written in the correct order to prevent a COP reset.Reset Value:
XGISP31: 0000h
Table 5: XGIPS31 Register Bits
4.5 Xgate Vector Base Address Register (XGVBR)
Bit #AccessDescription15:1RWXGVBR, Sets the vector base address that the Xgate RISC Core uses to determine where in the memory map the code and data space is for a specific interrupt is reserved.Reset Value:
XGVBR: FE00h
Table 5: XGVBR Register Bits
4.6 Xgate Interrupt Flag Register 7 (XGIFR_7)
The bits in this register reflect the state of interrupts that are being output from the Xgate module to the host CPU. A bit is set by the Xgate module with the SIF instruction usually at the end of a process and the host CPU clears the XGIF bit as part of its interrupt service routine.
Clear the interrupt output by writing a 1 to the corresponding XGIF register bit.
The highest numbered interrupt is in the MSB position of the register bank.
Some bits in this register may be unimplemented in a specific hardware design based on the setting of the MAX_CHANNEL parameter and will always read as 0.
Bit #AccessDescription15:0RWXGIF_127 XGIF_112
0 No interrupt.
1 Interrupt output active.Reset Value:
XGIFR_7: 0000h
Table 5: XGIF_7 Register Bits
4.6 Xgate Software Trigger Register (XGSWT)
Bit #AccessDescription15:8WXGSWTM[7:0], Read always returns zero.
XGSWTM, XGSWT Mask The XGSWT bits can only be changed when the XGSWTM bit is set in the same register access.
0 No change allowed to XGSWT control bit.
1 Change allowed to XGSWT control bit.
Always reads as 0.7:0RWXGSWT[7:0], XG Software Trigger The XGSWT bit can only be changed when the XGSWTM bit is set in the same register access.
0 The Xgate module is disabled. The currently active interrupt request will be completed and then no new interrupt processing requests will be accepted.
1 The Xgate module is enabled to start processing channel interrupts.Reset Value:
XGSWT: 0000h
Table 5: XGSWT Register Bits
4.6 Xgate Semaphore Register (XGSEM)
Bit #AccessDescription15:8WXGSEMM, XGSEM Mask The XGSEM bit can only be changed when the XGSEMM bit is set in the same register access.
0 No change allowed to XGSEM control bit.
1 Change allowed to XGSEM control bit.
Always reads as 0.7:0RWXGSWT[7:0], XG Software Trigger The XGSWT bit can only be changed when the XGSWTM bit is set in the same register access.
0 The semaphore bit is either unlocked or locked by the Xgate module. If the host attempts to set the bit by writing a 1 and a subsequent read of the bit returns a 0 the bit is locked by the Xgate module.
1 The semaphore bit is locked by the host processor. The host writes a 0 to clear the bit and unlock the semaphore.Reset Value:
XGSEM: 0000h
Table 5: XGSEM Register Bits
4.6 Xgate Condition Code Register (XGCCR)
Bit #AccessDescription15:4RReserved, write zeros for future compatibility.3RWXGN, Xgate Negative Reflects the current state of the Negative bit of the Xgate condition code register. 2RWXGZ, Xgate Zero Reflects the current state of the Zero bit of the Xgate condition code register.1RWXGV, Xgate Overflow Reflects the current state of the Overflow bit of the Xgate condition code register.0RWXGC, Xgate Carry Reflects the current state of the Carry bit of the Xgate condition code register.Reset Value:
XGCCR: 0000h
Table 5: XGCCR Register Bits
4.6 Xgate Program Counter Register (XGPC)
Bit #AccessDescription15:0RWXGPC, Read returns the current state of the Xgate Program Counter.
Writes to the XGPC register can only be done in Debug Mode.Reset Value:
XGPC: 0000h
Table 5: XGPC Register Bits
4.6 Xgate Register 1 (XGR1)
Bit #AccessDescription15:0RWXGR1, Read returns the current state of the Xgate General Purpose Register 1.
Writes to the XGR1 register can only be done in Debug Mode.Reset Value:
XGR1: 0000h
Table 5: XGR1 Register Bits
Clocks
NameSourceRates (MHz)RemarksDescriptionMaxMinResolutionwbs_clk_iSystem200--Master clock for all Xgate bus registers. Positive edge active.System clock.risc_clk_iSystemRISC Processor clockTable SEQ Table \* ARABIC 3: List of clocks
The wbs_clk_i has no timing constraints based on the RTL implementation although there may be constrains applied for synthesis results to be compatible with the target physical implementation. If the Xgate is targeted for an ASIC implementation then [wbs_clk_i] should be used as the scan clock, any clock multiplexing required to make [wbs_clk_i] the scan clock should be done at the system level external to the Xgate Module.
The risc_clk_i is the clock used to run the Xgate RISC processor submodule. The frequency of this clock should be the same as or 2X the frequency of the wbs_clk_i input. The risc_clk_i input is assumed to be in phase with the wbs_clk_i input.
IO Ports
PortWidthDirectionDescriptionwbs_clk_i1InputWISHBONE Bus Clock Input, Master Clockwbs_rst_i1InputWISHBONE Slave Synchronous Resetwbs_adr_i5InputWISHBONE Slave Lower address bitswbs_dat_i16InputWISHBONE Slave Bus Datawbs_dat_o16OutputWISHBONE Slave Bus Datawbs_we_i1InputWISHBONE Slave Write enablewbs_stb_i1InputWISHBONE Slave Strobe signal/Core selectwbs_cyc_i1InputWISHBONE Slave Valid bus cyclewbs_sel_i2InputWISHBONE Slave Data Bus Byte Selectwbs_ack_o1OutputWISHBONE Slave Bus cycle acknowledge wbm_adr_o16OutputWISHBONE Master address bitswbm_dat_i16InputWISHBONE Master Bus Datawbm_dat_o16OutputWISHBONE Master Bus Datawbm_we_o1OutputWISHBONE Master Write enablewbm_stb_o1OutputWISHBONE Master Strobe signal/Core selectwbm_cyc_o1OutputWISHBONE Master Valid bus cyclewbm_sel_o2OutputWISHBONE Master Data Bus Byte Selectwbm_ack_i1InputWISHBONE Master Bus cycle acknowledge arst_i1InputAsynchronous Resetrisc_clk_i1InputClock signal for the RISC Core Processorchan_req_i127InputXgate Interrupt Request xgif_o127OutputXgate Interrupt Requextxg_sw_irq1OutputXgate Software Error Interruptxgswt8OutputXgate Software Triggerdebug_mode_i1InputForce Xgate into debug modesecure_mode_i1InputLimit host access to RISC core registersscantestmode_i1InputScan Test Mode EnableTable SEQ Table \* ARABIC 4: List of IO ports
6.1 WISHBONE Slave Interface
The core features a WISHBONE RevB.3 compliant WISHBONE Classic interface that operates in SLAVE mode. All output signals are registered. Each access takes 2 clock cycles. To limit a WISHBONE access to just two clock cycles the following synthesis rules should be used:
Single cycle timing for wbs_cyc_i and wbs_stb_i
Two cycle timing for wbs_adr_i, wbs_data_i, and wbs_data_o. (Single cycle timing could be used but it would be a waste of resources to meet an over constrained timing path.)
Note: Use the SINGLE_CYCLE parameter to do a WISHBONE bus access in one clock cycle.
WISHBONE DATASHEETDescriptionSpecificationGeneral description:8-bit SLAVESupported Cycles:SLAVE, READ/WRITEData port, size:
Data port, granularity:
Data port, maximum operand size:
Data transfer ordering:
Data transfer sequencing:Default: 16, option 8 bit
Default: 16, option to match 8 bit port size
Supported signal list and cross reference to equivalent WISHBONE signals:Signal NameWISHBONE Equiv.wbs_clk_iCLK_Iwbs_rst_iRST_Iwbs_adr_iADR_I()wbs_dat_iDAT_I()wbs_dat_oDAT_O()wbs_we_iWE_Iwbs_stb_iSTB_Iwbs_cyc_iCYC_Iwbs_sel_iSEL_I()wbs_ack_oACK_O
6.1.1 wbs_rst_i
The synchronous reset signal has a minimum pulse width requirement of one [wbs_clk_i] clock period. It will take two [wbs_clk_i] clock cycles for all registers in the Xgate Module to initialize. Also see information on pin [arst_i].
6.1.2 wbs_adr_i
Connections to the WISHBONE address pins will depend on the size of the WISHBONE data bus that is set by the DWIDTH parameter. If DWIDTH=8 the all address pins should be connected, if DWIDTH=16 then [wbs_adr_i(2)] should be tied low.
6.1.3 wbs_sel_i
The [wbs_sel_i] is the WISHBONE byte lane select signal. It is currently unimplemented in the Xgate module and should be tied hi.
6.2 Xgate signals
6.2.1 xgif_o[127:0]
The Xgate output signal. This output is the result of executing the SIF command by the Xgate RISC processor. The normal connection is to the interrupt inputs of the host processor.
6.2.2 chan_req_i[127:0]
These signals are the interrupt inputs from the prepherial modules that the Xgate services. The eight outputs of the xgswt_o bus may also connect to some subset these inputs.
6.2.3 xgswt_o[7:0]
The [xgswt_o] signal is active low. These signals are activated by the host processor writing to the XGSWT register. These signals are connected to a user selected subset of the [chan_req_i] inputs to trigger the Xgate coprocessor to execute a software routine associated with the selected XGSWT register bit. The host should respond the the setting of one of the [xgif_o] outputs by clearing the set bit in the XGSWT register. Priority of the software routine executed is determined by which [chan_req_i] input the [xgswt_o] signal is connected to.
6.2.4 arst_i
The signal [arst_i] is an asynchronous reset signal that goes to all flops in the COP. It is provided for FPGA implementations and test methodologies that require this function for initialization. Using [arst_i] instead of [wb_rst_i] can result in lower cell-usage and higher performance for a FPGAs implementation because the standard FPGA cell already provides a dedicated asynchronous reset path. Using [wb_rst_i] for an ASIC implementation might synthesize to a smaller module because smaller non_reset flops can be used. Use either [arst_i] or [wb_rst_i], tie the other to a negated state. The active level of [arst_i] is determined by the parameter ARST_LVL that defaults to active low.
6.2.6 xg_sw_irq_o
This output signal is activated whenever the Xgate is activated whenever the encounters a software error. These errors are:
Instruction error
Instruction Address error
Load/Store Word Address error
6.2.7 risc_clk_i
The [risc_clk_i] is the clock input signal used by the RISC core processor.
6.2.8 debug_mode_i
The [debug_mode_i] input can be used by an external source such as a debug module to force the Xgate RISC core processor into debug mode. The exact number of clock cycles between the [debug_mode_i] signal going active and the RISC core stopping instruction execution may vary between one and several clock cycles. If no external debug activation is required then the [debug_mode_i] signal should be tied low.
6.2.9 secure_mode_i
The [secure_mode_i] input is used to limit host read access to the RISC core registers for software security reasons. In an ASIC implementation this pin would be tied to a non-volatile memory bit that is only cleared when all of the Xgate program memory is also cleared. In an FPGA implementation the signal may be tied to a level consistent with the desired application security level. If no software security is required then the [secure_mode_i] signal should be tied low.
6.2.10 scantestmode_i
The [scantestmode_i] input is an optional signal used to put the module into scan test mode. When [scantestmode_i] is active the [startup_osc_clk_i] is replaced by the [wb_clk_i] clock so all register are clocked by a common clock source.
6.3 Xgate Core Parameters
ParameterTypeDefaultDescriptionARST_LVLBit1b0Asynchronous reset levelMAX_CHANNELInteger127Number of input an output interruptsSINGLE_CYCLEBit1b0WISHBONE wait state
6.3.1 ARST_LVL
The asynchronous reset level can be set to either active high (1b1) or active low (1b0).
Allowed values: 1b0, 1b1
6.3.2 MAX_CHANNEL
The maximun index value for chan_req_i and xgif.
Allowed values: any integer value between 1 and 127
6.3.3 SINGLE_CYCLE
The default operation of the Xgate WISHBONE bus interface is to insert one wait state by delaying the assertion of the wb_ack_o by one wb_clk_i period. Setting the SINGLE_CYCLE parameter generates the wb_ack_o combinationaly so a WISHBONE bus cycle can be completed in one wb_clk_i period.
Allowed values: 1b0, 1b1
Name
[This section may be added to outline different specifications.]
[This section contains an alphabetical list of helpful document entries with their corresponding page numbers.]
OpenCores TITLE \* MERGEFORMAT Xgate Co-Processor (Xgate) Module DATE \* MERGEFORMAT 10/19/09
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.1 Preliminary PAGE ii
OpenCores TITLE \* MERGEFORMAT Xgate Co-Processor (Xgate) Module DATE \* MERGEFORMAT 10/19/09
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.1 Preliminary PAGE iii
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.1 Preliminary PAGE 9 of SECTIONPAGES29
wrt_semp=1
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CSEM
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Figure STYLEREF 2 \s 2 SEQ Figure \* ARABIC \s 2 1 Internal Structure Xgate Core
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