////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// WISHBONE revB.2 compliant Xgate Coprocessor - Master Bus interface
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// WISHBONE revB.2 compliant Xgate Coprocessor - Master Bus interface
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//
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//
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// Author: Bob Hayes
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// Author: Bob Hayes
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// rehayes@opencores.org
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// rehayes@opencores.org
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//
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//
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// Downloaded from: http://www.opencores.org/projects/xgate.....
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// Downloaded from: http://www.opencores.org/projects/xgate.....
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2009, Robert Hayes
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// Copyright (c) 2009, Robert Hayes
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// Supplemental terms.
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// Supplemental terms.
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// * Redistributions of source code must retain the above copyright
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// notice, this list of conditions and the following disclaimer.
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// * Neither the name of the <organization> nor the
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// * Neither the name of the <organization> nor the
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// names of its contributors may be used to endorse or promote products
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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// derived from this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module xgate_wbm_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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module xgate_wbm_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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parameter DWIDTH = 16,
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parameter DWIDTH = 16,
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parameter SINGLE_CYCLE = 1'b0)
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parameter SINGLE_CYCLE = 1'b0)
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(
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(
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// Wishbone Signals
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// Wishbone Signals
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output [DWIDTH-1:0] wbm_dat_o, // databus output
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output [DWIDTH-1:0] wbm_dat_o, // databus output
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output wbm_we_o, // write enable output
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output wbm_we_o, // write enable output
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output wbm_stb_o, // stobe/core select signal
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output wbm_stb_o, // stobe/core select signal
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output wbm_cyc_o, // valid bus cycle output
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output wbm_cyc_o, // valid bus cycle output
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output [ 1:0] wbm_sel_o, // Select byte in word bus transaction
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output [ 1:0] wbm_sel_o, // Select byte in word bus transaction
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output [15:0] wbm_adr_o, // Address bits
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output [15:0] wbm_adr_o, // Address bits
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input [DWIDTH-1:0] wbm_dat_i, // databus input
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input [DWIDTH-1:0] wbm_dat_i, // databus input
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input wbm_ack_i, // bus cycle acknowledge input
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input wbm_ack_i, // bus cycle acknowledge input
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input wbs_clk_i, // master clock input
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input wbs_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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// XGATE Control Signals
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// XGATE Control Signals
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output [DWIDTH-1:0] read_mem_data, // Data from system memory
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output [DWIDTH-1:0] read_mem_data, // Data from system memory
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output mem_req_ack, // Memory bus transaction complete
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output mem_req_ack, // Memory bus transaction complete
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input risc_clk, //
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input risc_clk, //
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input async_rst_b, //
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input async_rst_b, //
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input xge, // XGATE Enabled
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input xge, // XGATE Enabled
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input single_step, // Pulse to trigger a single instruction execution in debug mode
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input single_step, // Pulse to trigger a single instruction execution in debug mode
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output ss_mem_ack, // WISHBONE Bus has granted single step memory access
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output ss_mem_ack, // WISHBONE Bus has granted single step memory access
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input [15:0] xgate_address, // Address to system memory
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input [15:0] xgate_address, // Address to system memory
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input mem_access, //
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input mem_access, //
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input write_mem_strb_l, // Strobe for writing low data byte
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input write_mem_strb_l, // Strobe for writing low data byte
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input write_mem_strb_h, // Strobe for writing high data bye
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input write_mem_strb_h, // Strobe for writing high data bye
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input [DWIDTH-1:0] write_mem_data // Data to system memory
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input [DWIDTH-1:0] write_mem_data // Data to system memory
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);
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);
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// Wires and Registers
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// Wires and Registers
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wire module_sel; // This module is selected for bus transaction
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wire module_sel; // This module is selected for bus transaction
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reg ss_mem_req; // Bus request for single step memory access
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reg ss_mem_req; // Bus request for single step memory access
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//
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//
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// Module body
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// Module body
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//
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//
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// Latch Single Step Request and ask for memory access
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// Latch Single Step Request and ask for memory access
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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ss_mem_req <= 1'b0;
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ss_mem_req <= 1'b0;
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else
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else
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ss_mem_req <= (single_step || ss_mem_req) && !wbm_ack_i && xge;
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ss_mem_req <= (single_step || ss_mem_req) && !wbm_ack_i && xge;
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assign ss_mem_ack = ss_mem_req && wbm_ack_i;
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assign ss_mem_ack = ss_mem_req && wbm_ack_i;
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assign wbm_dat_o = write_mem_data;
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assign wbm_dat_o = write_mem_data;
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assign read_mem_data = wbm_dat_i;
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assign read_mem_data = wbm_dat_i;
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assign wbm_adr_o = xgate_address;
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assign wbm_adr_o = xgate_address;
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assign mem_req_ack = wbm_ack_i;
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assign mem_req_ack = wbm_ack_i;
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assign wbm_we_o = write_mem_strb_h || write_mem_strb_l;
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assign wbm_we_o = write_mem_strb_h || write_mem_strb_l;
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assign wbm_sel_o = {write_mem_strb_h, write_mem_strb_l};
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assign wbm_sel_o = {write_mem_strb_h, write_mem_strb_l};
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assign wbm_cyc_o = xge && (mem_access || ss_mem_req);
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assign wbm_cyc_o = xge && (mem_access || ss_mem_req);
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assign wbm_stb_o = xge && (mem_access || ss_mem_req);
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assign wbm_stb_o = xge && (mem_access || ss_mem_req);
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endmodule // xgate_wbm_bus
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endmodule // xgate_wbm_bus
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