URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [sim/] [verilog/] [run/] [run_iverilog] - Diff between revs 5 and 32

Rev 5	Rev 32
`#!/bin/csh`	`#!/bin/csh`

`set xgate = ../../..`	`set xgate = ../../..`
`set bench = $xgate/bench`	`set bench = $xgate/bench`
`set wave_dir = $xgate/sim/rtl_sim/xgate_verilog/waves`	`set wave_dir = $xgate/sim/rtl_sim/xgate_verilog/waves`

`iverilog \`	`iverilog \`
`\`	`\`
`-I $bench/verilog \`	`-I $bench/verilog \`
`-I $xgate/rtl/verilog \`	`-I $xgate/rtl/verilog \`
`\`	`\`
`-o xgate_compiled \`	`-o xgate_compiled \`
`-D WAVES_V \`	`-D WAVES_V \`
`\`	`\`
`$xgate/rtl/verilog/xgate_top.v \`	`$xgate/rtl/verilog/xgate_top.v \`
`$xgate/rtl/verilog/xgate_wbs_bus.v \`	`$xgate/rtl/verilog/xgate_wbs_bus.v \`
`$xgate/rtl/verilog/xgate_wbm_bus.v \`	`$xgate/rtl/verilog/xgate_wbm_bus.v \`
`$xgate/rtl/verilog/xgate_regs.v \`	`$xgate/rtl/verilog/xgate_regs.v \`
`$xgate/rtl/verilog/xgate_risc.v \`	`$xgate/rtl/verilog/xgate_risc.v \`
`$xgate/rtl/verilog/xgate_irq_encode.v \`	`$xgate/rtl/verilog/xgate_irq_encode.v \`
`\`	`\`
`$bench/verilog/wb_master_model.v \`	`$bench/verilog/wb_master_model.v \`
	`$bench/verilog/ram.v \`
`$bench/verilog/tst_bench_top.v`	`$bench/verilog/tst_bench_top.v`

`@ good_compile = $status`	`@ good_compile = $status`

`if ($good_compile == 0) then`	`if ($good_compile == 0) then`
`echo "Compile was Good"`	`echo "Compile was Good"`
`vvp xgate_compiled -lxt2`	`vvp xgate_compiled -lxt2`
`else`	`else`
`echo "Compile Failed"`	`echo "Compile Failed"`
`endif`	`endif`