; 345678901234567890123456789012345678901234567890123456789012345678901234567890
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; 345678901234567890123456789012345678901234567890123456789012345678901234567890
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; Instruction set test for xgate RISC processor core
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; Instruction set test for xgate RISC processor core
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; Bob Hayes - Sept 23 2009
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; Bob Hayes - Sept 23 2009
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; Version 0.1 Basic tests of Debug Mode
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; Version 0.1 Basic tests of Debug Mode
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CPU XGATE
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CPU XGATE
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ORG $fe00
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ORG $fe00
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DS.W 2 ; reserve two words at channel 0
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DS.W 2 ; reserve two words at channel 0
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; channel 1
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; channel 1
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DC.W _START ; point to start address
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DC.W _START ; point to start address
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DC.W V_PTR ; point to initial variables
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DC.W V_PTR ; point to initial variables
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; channel 2
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; channel 2
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DC.W _START2 ; point to start address
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DC.W _START2 ; point to start address
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DC.W V_PTR ; point to initial variables
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DC.W V_PTR ; point to initial variables
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; channel 3
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; channel 3
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DC.W _START3 ; point to start address
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DC.W _START3 ; point to start address
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DC.W V_PTR ; point to initial variables
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DC.W V_PTR ; point to initial variables
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; channel 4
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; channel 4
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DC.W _START4 ; point to start address
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DC.W _START4 ; point to start address
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DC.W V_PTR ; point to initial variables
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DC.W V_PTR ; point to initial variables
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; channel 5
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; channel 5
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DC.W _START5 ; point to start address
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DC.W _START5 ; point to start address
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DC.W V_PTR ; point to initial variables
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DC.W V_PTR ; point to initial variables
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; channel 6
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; channel 6
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DC.W _START6 ; point to start address
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DC.W _START6 ; point to start address
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DC.W V_PTR ; point to initial variables
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DC.W V_PTR ; point to initial variables
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; channel 7
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; channel 7
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DC.W _ERROR ; point to start address
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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DC.W V_PTR ; point to initial variables
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; channel 8
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; channel 8
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DC.W _ERROR ; point to start address
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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DC.W V_PTR ; point to initial variables
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; channel 9
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; channel 9
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DC.W _ERROR ; point to start address
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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DC.W V_PTR ; point to initial variables
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; channel 10
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; channel 10
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DC.W _ERROR ; point to start address
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DC.W _ERROR ; point to start address
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DC.W V_PTR ; point to initial variables
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DC.W V_PTR ; point to initial variables
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ORG $2000 ; with comment
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ORG $2000 ; with comment
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V_PTR EQU 123
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V_PTR EQU 123
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DC.W BACK_
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DC.W BACK_
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DS.W 8
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DS.W 8
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DC.B $56
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DC.B $56
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DS.B 11
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DS.B 11
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ALIGN 1
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ALIGN 1
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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; Place where undefined interrupts go
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; Place where undefined interrupts go
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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_ERROR
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_ERROR
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$ff
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LDL R3,#$ff
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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SIF
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SIF
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RTS
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RTS
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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; Test Debug Mode and Single Step instructions
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; Test Debug Mode and Single Step instructions
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;
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;
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; Note: The testbench checks the PC values so adding or removing instructions
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; Note: The testbench checks the PC values so adding or removing instructions
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; from this test will also require a change to the testbench
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; from this test will also require a change to the testbench
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; expected values.
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; expected values.
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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_START
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_START
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$01
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LDL R3,#$01
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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; Test
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; Test
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LDL R4,#$c3 ;
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LDL R4,#$c3 ;
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STW R4,(R0,#$08) ;
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STW R4,(R0,#$08) ;
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LDL R3,#$01 ; R3 = $01
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LDL R7,#$01 ; R3 = $01; R7 = $01
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BRK ; Enter Debug mode and start doing Single Step Commands
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BRK ; Enter Debug mode and start doing Single Step Commands
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; from the testbench. Verify PC and R3 values.
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; from the testbench. Verify PC and R3 values.
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ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $02)
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ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $02)
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NOP
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NOP
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BRA _BRA_OK1 ; Do Foward Branch Single Step
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BRA _BRA_OK1 ; Do Foward Branch Single Step
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ADDL R3,#$40 ; For error detection
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ADDL R3,#$40 ; For error detection
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NOP
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NOP
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ADDL R3,#$60 ; For error detection
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ADDL R3,#$60 ; For error detection
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_BRA_OK2
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_BRA_OK2
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STW R3,(R0,#$0c) ;
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STW R3,(R0,#$0c) ;
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ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $04)
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ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $04)
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; Testbench Clears Debug mode
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; Testbench Clears Debug mode
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CMP R4,R7 ; Check Load and Store commands received correct data
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CMP R4,R7 ; Check Load and Store commands received correct data
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BNE _FAIL
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BNE _FAIL
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LDW R5,(R0,#$0c) ;
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LDW R5,(R0,#$0c) ;
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ADDL R5,#$01 ; R5 + $01 => R5 (R5 = $04) Catch up to latest R3 value
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ADDL R5,#$01 ; R5 + $01 => R5 (R5 = $04) Catch up to latest R3 value
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CMP R3,R5 ;
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CMP R3,R5 ;
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BNE _FAIL
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BNE _FAIL
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$02
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LDL R3,#$02
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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SIF
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SIF
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RTS
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RTS
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_BRA_OK1
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_BRA_OK1
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ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $03)
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ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $03)
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LDW R7,(R0,#$08) ;
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LDW R7,(R0,#$08) ;
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BRA _BRA_OK2 ; Do Backward Branch
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BRA _BRA_OK2 ; Do Backward Branch
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_FAIL
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_FAIL
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$01
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LDL R3,#$01
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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SIF
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SIF
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RTS
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RTS
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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; Test Debug Command
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; Test Debug Command
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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_START2
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_START2
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$03
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LDL R3,#$03
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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LDL R3,#$02 ; Thread Value
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LDL R3,#$02 ; Thread Value
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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; Test
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; Test
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LDL R3,#$01 ; R3 = $01
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LDL R3,#$01 ; R3 = $01
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LDL R4,#$01 ; R4 = $01
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LDL R4,#$01 ; R4 = $01
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LDL R7,#$03 ; R7 = $03
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LDL R7,#$03 ; R7 = $03
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_T2_LOOP
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_T2_LOOP
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ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $02)
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ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $02)
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NOP
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COM R6 ; Toggle R6
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BRA _T2_LOOP ; Create an infinate loop. The testbench will
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BRA _T2_LOOP ; Create an infinate loop. The testbench will
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; take control using the Debug bit and change
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; take control using the Debug bit and change
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; the PC to exit the loop.
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; the PC to exit the loop.
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NOP
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NOP
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NOP
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NOP
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ADDL R4,#$60 ; For error detection
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ADDL R4,#$60 ; For error detection
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ADDL R4,#$01 ; Test bench will set the PC to here
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ADDL R4,#$01 ; Test bench will set the PC to here
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ADDL R4,#$01 ;
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ADDL R4,#$01 ;
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CMP R4,R7 ; Check Load and Store commands received correct data
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CMP R4,R7 ; Check Load and Store commands received correct data
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BNE _FAIL2
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BNE _FAIL2
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_END_2 LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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_END_2 LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$04
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LDL R3,#$04
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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SIF
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SIF
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RTS
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RTS
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_FAIL2
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_FAIL2
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$02
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LDL R3,#$02
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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SIF
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SIF
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RTS
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RTS
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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; Test Debug and Change Channel ID Command
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; Test Debug and Change Channel ID Command
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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_START3
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_START3
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$05
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LDL R3,#$05
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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LDL R3,#$03 ; Thread Value
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LDL R3,#$03 ; Thread Value
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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; Test
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; Test
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LDL R3,#$01 ; R3 = $01
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LDL R3,#$01 ; R3 = $01
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LDL R4,#$01 ; R4 = $01
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LDL R4,#$01 ; R4 = $01
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LDL R7,#$03 ; R7 = $03
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LDL R7,#$03 ; R7 = $03
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BRK ; Enter Debug mode
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BRK ; Enter Debug mode
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; The testbench will use writes to the XGCHID reg to move to another
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; The testbench will use writes to the XGCHID reg to move to another
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; channel to complete the test.
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; channel to complete the test.
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_FAIL3
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_FAIL3
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$03
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LDL R3,#$03
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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SIF
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SIF
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RTS
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RTS
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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; Target for debug mode change CHID Command
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; Target for debug mode change CHID Command
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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_START4
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_START4
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$06
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LDL R3,#$06
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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; Test
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; Test
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BRK
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BRK
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_END_4 LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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_END_4 LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$07
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LDL R3,#$07
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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SIF
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SIF
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RTS
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RTS
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_FAIL4
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_FAIL4
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$04
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LDL R3,#$04
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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SIF
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SIF
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RTS
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RTS
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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; False Target for debug mode change CHID Command
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; False Target for debug mode change CHID Command
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; Verify that when the CHID command is issued that a higher poririty interrup
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; Verify that when the CHID command is issued that a higher poririty interrup
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; dosn't slip in.
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; dosn't slip in.
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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_START5
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_START5
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$08
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LDL R3,#$08
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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LDL R3,#$05 ; Thread Value
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LDL R3,#$05 ; Thread Value
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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; Test
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; Test
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BRK
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BRK
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_END_5 LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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_END_5 LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$09
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LDL R3,#$09
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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SIF
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SIF
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RTS
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RTS
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_FAIL5
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_FAIL5
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$05
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LDL R3,#$05
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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SIF
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SIF
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RTS
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RTS
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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; Test Debug and Change Channel ID Command
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; Test Debug and Change Channel ID Command
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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_START6
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_START6
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BRK ; Enter Debug mode
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BRK ; Enter Debug mode
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BRA _GO6
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BRA _GO6
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BRA _FAIL6
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BRA _FAIL6
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_GO6
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_GO6
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$0a
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LDL R3,#$0a
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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LDL R3,#$06 ; Thread Value
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LDL R3,#$06 ; Thread Value
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
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; Test
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; Test
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_END_6 LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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_END_6 LDL R2,#$00 ; Sent Message to Testbench Check Point Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$0b
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LDL R3,#$0b
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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SIF
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SIF
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RTS
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RTS
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_FAIL6
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_FAIL6
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDL R2,#$04 ; Sent Message to Testbench Error Register
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LDH R2,#$80
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LDH R2,#$80
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LDL R3,#$06
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LDL R3,#$06
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STB R3,(R2,#0)
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STB R3,(R2,#0)
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SIF
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SIF
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RTS
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RTS
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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;empty line
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;empty line
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BACK_
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BACK_
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SIF R7
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SIF R7
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BRK
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BRK
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ORG $8000 ; Special Testbench Addresses
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ORG $8000 ; Special Testbench Addresses
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_BENCH DS.W 8
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_BENCH DS.W 8
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