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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [tx_hold_fifo.v] - Diff between revs 7 and 12

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  File name "tx_hold_fifo.v"                                  ////
////  File name "tx_hold_fifo.v"                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the "10GE MAC" project                 ////
////  This file is part of the "10GE MAC" project                 ////
////  http://www.opencores.org/cores/xge_mac/                     ////
////  http://www.opencores.org/cores/xge_mac/                     ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - A. Tanguay (antanguay@opencores.org)                  ////
////      - A. Tanguay (antanguay@opencores.org)                  ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
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//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
 
 
`include "defines.v"
`include "defines.v"
 
 
module tx_hold_fifo(/*AUTOARG*/
module tx_hold_fifo(/*AUTOARG*/
  // Outputs
  // Outputs
  txhfifo_wfull, txhfifo_walmost_full, txhfifo_rdata,
  txhfifo_wfull, txhfifo_walmost_full, txhfifo_rdata, txhfifo_rstatus,
  txhfifo_rstatus, txhfifo_rempty, txhfifo_ralmost_empty,
  txhfifo_rempty, txhfifo_ralmost_empty,
  // Inputs
  // Inputs
  clk_xgmii_tx, reset_xgmii_tx_n, txhfifo_wdata, txhfifo_wstatus,
  clk_xgmii_tx, reset_xgmii_tx_n, txhfifo_wdata, txhfifo_wstatus,
  txhfifo_wen, txhfifo_ren
  txhfifo_wen, txhfifo_ren
  );
  );
 
 
input         clk_xgmii_tx;
input         clk_xgmii_tx;
input         reset_xgmii_tx_n;
input         reset_xgmii_tx_n;
 
 
input [63:0]  txhfifo_wdata;
input [63:0]  txhfifo_wdata;
input [7:0]   txhfifo_wstatus;
input [7:0]   txhfifo_wstatus;
input         txhfifo_wen;
input         txhfifo_wen;
 
 
input         txhfifo_ren;
input         txhfifo_ren;
 
 
output        txhfifo_wfull;
output        txhfifo_wfull;
output        txhfifo_walmost_full;
output        txhfifo_walmost_full;
 
 
output [63:0] txhfifo_rdata;
output [63:0] txhfifo_rdata;
output [7:0]  txhfifo_rstatus;
output [7:0]  txhfifo_rstatus;
output        txhfifo_rempty;
output        txhfifo_rempty;
output        txhfifo_ralmost_empty;
output        txhfifo_ralmost_empty;
 
 
generic_fifo #(
generic_fifo #(
  .DWIDTH (72),
  .DWIDTH (72),
  .AWIDTH (`TX_HOLD_FIFO_AWIDTH),
  .AWIDTH (`TX_HOLD_FIFO_AWIDTH),
  .REGISTER_READ (1),
  .REGISTER_READ (1),
  .EARLY_READ (1),
  .EARLY_READ (1),
  .CLOCK_CROSSING (0),
  .CLOCK_CROSSING (0),
  .ALMOST_EMPTY_THRESH (7),
  .ALMOST_EMPTY_THRESH (7),
  .ALMOST_FULL_THRESH (4),
  .ALMOST_FULL_THRESH (4),
  .MEM_TYPE (`MEM_AUTO_SMALL)
  .MEM_TYPE (`MEM_AUTO_SMALL)
)
)
fifo0(
fifo0(
    .wclk (clk_xgmii_tx),
    .wclk (clk_xgmii_tx),
    .wrst_n (reset_xgmii_tx_n),
    .wrst_n (reset_xgmii_tx_n),
    .wen (txhfifo_wen),
    .wen (txhfifo_wen),
    .wdata ({txhfifo_wstatus, txhfifo_wdata}),
    .wdata ({txhfifo_wstatus, txhfifo_wdata}),
    .wfull (txhfifo_wfull),
    .wfull (txhfifo_wfull),
    .walmost_full (txhfifo_walmost_full),
    .walmost_full (txhfifo_walmost_full),
 
 
    .rclk (clk_xgmii_tx),
    .rclk (clk_xgmii_tx),
    .rrst_n (reset_xgmii_tx_n),
    .rrst_n (reset_xgmii_tx_n),
    .ren (txhfifo_ren),
    .ren (txhfifo_ren),
    .rdata ({txhfifo_rstatus, txhfifo_rdata}),
    .rdata ({txhfifo_rstatus, txhfifo_rdata}),
    .rempty (txhfifo_rempty),
    .rempty (txhfifo_rempty),
    .ralmost_empty (txhfifo_ralmost_empty)
    .ralmost_empty (txhfifo_ralmost_empty)
);
);
 
 
endmodule
endmodule
 
 
 
 

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