// $Id: sc_main.cpp,v 1.3 2008-06-07 02:59:55 antanguay Exp $ -*- SystemC -*-
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// $Id: sc_main.cpp,v 1.3 2008-06-07 02:59:55 antanguay Exp $ -*- SystemC -*-
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// DESCRIPTION: Verilator Example: Top level main for invoking SystemC model
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// DESCRIPTION: Verilator Example: Top level main for invoking SystemC model
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//
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//
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// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
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// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// redistribute it and/or modify it under the terms of either the GNU
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// General Public License or the Perl Artistic License.
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// General Public License or the Perl Artistic License.
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//====================================================================
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//====================================================================
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name "sc_main.cpp" ////
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//// File name "sc_main.cpp" ////
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//// ////
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//// ////
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//// This file is part of the "10GE MAC" project ////
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//// This file is part of the "10GE MAC" project ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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#include <stdio.h>
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#include <stdio.h>
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#include <iostream>
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#include <iostream>
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#include <sys/times.h>
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#include <sys/times.h>
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#include <sys/stat.h>
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#include <sys/stat.h>
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#include "systemc.h" // SystemC global header
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#include "systemc.h" // SystemC global header
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//#include "SpTraceVcd.h"
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//#include "SpTraceVcd.h"
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#include "verilated_vcd_sc.h" // Tracing
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#include "verilated_vcd_sc.h" // Tracing
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#include "crc.h"
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#include "crc.h"
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#include "Vxge_mac.h" // Top level header, generated from verilog
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#include "Vxge_mac.h" // Top level header, generated from verilog
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#include "sc_defines.h"
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#include "sc_testbench.h"
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#include "sc_testbench.h"
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#include "sc_testcases.h"
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#include "sc_testcases.h"
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int sc_main(int argc, char* argv[]) {
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int sc_main(int argc, char* argv[]) {
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chksum_crc32gentab();
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chksum_crc32gentab();
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Verilated::randReset(2);
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Verilated::randReset(2);
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Verilated::debug(0); // We compiled with it on for testing, turn it back off
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Verilated::debug(0); // We compiled with it on for testing, turn it back off
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// General logfile
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// General logfile
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ios::sync_with_stdio();
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ios::sync_with_stdio();
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cout << ("Defining Clocks\n");
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cout << ("Defining Clocks\n");
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sc_clock clk_156m25 ("clk_156m25", 10, SC_NS, 0.5);
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sc_clock clk_156m25 ("clk_156m25", 10, SC_NS, 0.5);
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sc_clock clk_wb ("clk_wb", 29, SC_NS, 0.5);
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sc_clock clk_wb ("clk_wb", 29, SC_NS, 0.5);
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sc_clock clk_xgmii ("clk_xgmii", 10, SC_NS, 0.5);
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sc_clock clk_xgmii ("clk_xgmii", 10, SC_NS, 0.5);
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sc_signal<bool> pkt_rx_ren;
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sc_signal<bool> pkt_rx_ren;
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sc_signal<unsigned long long > pkt_tx_data;
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sc_signal<vluint64_t > pkt_tx_data;
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sc_signal<bool> pkt_tx_eop;
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sc_signal<bool> pkt_tx_eop;
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sc_signal<unsigned int> pkt_tx_mod;
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sc_signal<unsigned int> pkt_tx_mod;
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sc_signal<bool> pkt_tx_sop;
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sc_signal<bool> pkt_tx_sop;
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sc_signal<bool> pkt_tx_val;
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sc_signal<bool> pkt_tx_val;
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sc_signal<bool> reset_156m25_n;
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sc_signal<bool> reset_156m25_n;
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sc_signal<bool> reset_xgmii_n;
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sc_signal<bool> reset_xgmii_n;
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sc_signal<unsigned int> wb_adr_i;
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sc_signal<unsigned int> wb_adr_i;
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sc_signal<bool> wb_cyc_i;
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sc_signal<bool> wb_cyc_i;
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sc_signal<unsigned int > wb_dat_i;
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sc_signal<unsigned int > wb_dat_i;
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sc_signal<bool> wb_rst_i;
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sc_signal<bool> wb_rst_i;
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sc_signal<bool> wb_stb_i;
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sc_signal<bool> wb_stb_i;
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sc_signal<bool> wb_we_i;
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sc_signal<bool> wb_we_i;
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sc_signal<unsigned int> xgmii_rxc;
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sc_signal<unsigned int> xgmii_rxc;
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sc_signal<unsigned long long > xgmii_rxd;
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sc_signal<vluint64_t > xgmii_rxd;
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sc_signal<bool> pkt_rx_avail;
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sc_signal<bool> pkt_rx_avail;
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sc_signal<unsigned long long > pkt_rx_data;
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sc_signal<vluint64_t > pkt_rx_data;
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sc_signal<bool> pkt_rx_eop;
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sc_signal<bool> pkt_rx_eop;
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sc_signal<unsigned int> pkt_rx_mod;
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sc_signal<unsigned int> pkt_rx_mod;
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sc_signal<bool> pkt_rx_sop;
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sc_signal<bool> pkt_rx_sop;
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sc_signal<bool> pkt_rx_val;
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sc_signal<bool> pkt_rx_val;
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sc_signal<bool> pkt_rx_err;
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sc_signal<bool> pkt_rx_err;
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sc_signal<bool> pkt_tx_full;
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sc_signal<bool> pkt_tx_full;
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sc_signal<bool> wb_ack_o;
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sc_signal<bool> wb_ack_o;
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sc_signal<unsigned int> wb_dat_o;
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sc_signal<unsigned int> wb_dat_o;
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sc_signal<bool> wb_int_o;
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sc_signal<bool> wb_int_o;
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sc_signal<unsigned int> xgmii_txc;
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sc_signal<unsigned int> xgmii_txc;
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sc_signal<unsigned long long > xgmii_txd;
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sc_signal<vluint64_t > xgmii_txd;
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//==========
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//==========
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// Part under test
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// Part under test
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Vxge_mac* top = new Vxge_mac("top");
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Vxge_mac* top = new Vxge_mac("top");
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top->clk_156m25 (clk_156m25);
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top->clk_156m25 (clk_156m25);
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top->clk_xgmii_rx (clk_xgmii);
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top->clk_xgmii_rx (clk_xgmii);
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top->clk_xgmii_tx (clk_xgmii);
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top->clk_xgmii_tx (clk_xgmii);
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top->pkt_rx_ren (pkt_rx_ren);
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top->pkt_rx_ren (pkt_rx_ren);
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top->pkt_tx_data (pkt_tx_data);
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top->pkt_tx_data (pkt_tx_data);
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top->pkt_tx_eop (pkt_tx_eop);
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top->pkt_tx_eop (pkt_tx_eop);
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top->pkt_tx_mod (pkt_tx_mod);
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top->pkt_tx_mod (pkt_tx_mod);
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top->pkt_tx_sop (pkt_tx_sop);
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top->pkt_tx_sop (pkt_tx_sop);
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top->pkt_tx_val (pkt_tx_val);
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top->pkt_tx_val (pkt_tx_val);
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top->reset_156m25_n (reset_156m25_n);
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top->reset_156m25_n (reset_156m25_n);
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top->reset_xgmii_rx_n (reset_xgmii_n);
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top->reset_xgmii_rx_n (reset_xgmii_n);
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top->reset_xgmii_tx_n (reset_xgmii_n);
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top->reset_xgmii_tx_n (reset_xgmii_n);
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top->wb_adr_i (wb_adr_i);
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top->wb_adr_i (wb_adr_i);
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top->wb_clk_i (clk_wb);
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top->wb_clk_i (clk_wb);
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top->wb_cyc_i (wb_cyc_i);
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top->wb_cyc_i (wb_cyc_i);
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top->wb_dat_i (wb_dat_i);
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top->wb_dat_i (wb_dat_i);
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top->wb_rst_i (wb_rst_i);
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top->wb_rst_i (wb_rst_i);
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top->wb_stb_i (wb_stb_i);
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top->wb_stb_i (wb_stb_i);
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top->wb_we_i (wb_we_i);
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top->wb_we_i (wb_we_i);
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top->xgmii_rxc (xgmii_rxc);
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top->xgmii_rxc (xgmii_rxc);
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top->xgmii_rxd (xgmii_rxd);
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top->xgmii_rxd (xgmii_rxd);
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top->pkt_rx_avail (pkt_rx_avail);
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top->pkt_rx_avail (pkt_rx_avail);
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top->pkt_rx_data (pkt_rx_data);
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top->pkt_rx_data (pkt_rx_data);
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top->pkt_rx_eop (pkt_rx_eop);
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top->pkt_rx_eop (pkt_rx_eop);
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top->pkt_rx_mod (pkt_rx_mod);
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top->pkt_rx_mod (pkt_rx_mod);
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top->pkt_rx_err (pkt_rx_err);
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top->pkt_rx_err (pkt_rx_err);
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top->pkt_rx_sop (pkt_rx_sop);
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top->pkt_rx_sop (pkt_rx_sop);
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top->pkt_rx_val (pkt_rx_val);
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top->pkt_rx_val (pkt_rx_val);
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top->pkt_tx_full (pkt_tx_full);
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top->pkt_tx_full (pkt_tx_full);
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top->wb_ack_o (wb_ack_o);
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top->wb_ack_o (wb_ack_o);
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top->wb_dat_o (wb_dat_o);
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top->wb_dat_o (wb_dat_o);
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top->wb_int_o (wb_int_o);
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top->wb_int_o (wb_int_o);
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top->xgmii_txc (xgmii_txc);
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top->xgmii_txc (xgmii_txc);
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top->xgmii_txd (xgmii_txd);
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top->xgmii_txd (xgmii_txd);
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//==========
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//==========
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// Testbench
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// Testbench
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testbench* tb = new testbench("tb");
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testbench* tb = new testbench("tb");
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tb->clk_156m25 (clk_156m25);
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tb->clk_156m25 (clk_156m25);
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tb->clk_xgmii (clk_xgmii);
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tb->clk_xgmii (clk_xgmii);
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tb->wb_clk_i (clk_wb);
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tb->wb_clk_i (clk_wb);
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tb->reset_156m25_n (reset_156m25_n);
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tb->reset_156m25_n (reset_156m25_n);
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tb->reset_xgmii_n (reset_xgmii_n);
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tb->reset_xgmii_n (reset_xgmii_n);
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tb->wb_rst_i (wb_rst_i);
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tb->wb_rst_i (wb_rst_i);
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tb->wb_ack_o (wb_ack_o);
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tb->wb_ack_o (wb_ack_o);
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tb->wb_dat_o (wb_dat_o);
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tb->wb_dat_o (wb_dat_o);
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tb->wb_int_o (wb_int_o);
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tb->wb_int_o (wb_int_o);
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tb->wb_adr_i (wb_adr_i);
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tb->wb_adr_i (wb_adr_i);
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tb->wb_cyc_i (wb_cyc_i);
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tb->wb_cyc_i (wb_cyc_i);
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tb->wb_dat_i (wb_dat_i);
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tb->wb_dat_i (wb_dat_i);
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tb->wb_stb_i (wb_stb_i);
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tb->wb_stb_i (wb_stb_i);
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tb->wb_we_i (wb_we_i);
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tb->wb_we_i (wb_we_i);
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tb->xgmii_rxc (xgmii_rxc);
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tb->xgmii_rxc (xgmii_rxc);
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tb->xgmii_rxd (xgmii_rxd);
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tb->xgmii_rxd (xgmii_rxd);
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tb->xgmii_txc (xgmii_txc);
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tb->xgmii_txc (xgmii_txc);
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tb->xgmii_txd (xgmii_txd);
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tb->xgmii_txd (xgmii_txd);
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tb->pkt_tx_data (pkt_tx_data);
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tb->pkt_tx_data (pkt_tx_data);
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tb->pkt_tx_eop (pkt_tx_eop);
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tb->pkt_tx_eop (pkt_tx_eop);
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tb->pkt_tx_mod (pkt_tx_mod);
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tb->pkt_tx_mod (pkt_tx_mod);
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tb->pkt_tx_sop (pkt_tx_sop);
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tb->pkt_tx_sop (pkt_tx_sop);
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tb->pkt_tx_val (pkt_tx_val);
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tb->pkt_tx_val (pkt_tx_val);
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tb->pkt_tx_full (pkt_tx_full);
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tb->pkt_tx_full (pkt_tx_full);
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tb->pkt_rx_avail (pkt_rx_avail);
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tb->pkt_rx_avail (pkt_rx_avail);
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tb->pkt_rx_data (pkt_rx_data);
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tb->pkt_rx_data (pkt_rx_data);
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tb->pkt_rx_eop (pkt_rx_eop);
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tb->pkt_rx_eop (pkt_rx_eop);
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tb->pkt_rx_mod (pkt_rx_mod);
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tb->pkt_rx_mod (pkt_rx_mod);
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tb->pkt_rx_err (pkt_rx_err);
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tb->pkt_rx_err (pkt_rx_err);
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tb->pkt_rx_sop (pkt_rx_sop);
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tb->pkt_rx_sop (pkt_rx_sop);
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tb->pkt_rx_val (pkt_rx_val);
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tb->pkt_rx_val (pkt_rx_val);
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tb->pkt_rx_ren (pkt_rx_ren);
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tb->pkt_rx_ren (pkt_rx_ren);
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//==========
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//==========
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// Testcases
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// Testcases
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testcases* tc = new testcases("tc");
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testcases* tc = new testcases("tc");
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tc->connect_testbench(tb);
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tc->connect_testbench(tb);
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#if WAVES
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#if WAVES
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// Before any evaluation, need to know to calculate those signals only used for tracing
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// Before any evaluation, need to know to calculate those signals only used for tracing
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Verilated::traceEverOn(true);
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Verilated::traceEverOn(true);
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#endif
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#endif
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// You must do one evaluation before enabling waves, in order to allow
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// You must do one evaluation before enabling waves, in order to allow
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// SystemC to interconnect everything for testing.
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// SystemC to interconnect everything for testing.
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cout <<("Test initialization...\n");
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cout <<("Test initialization...\n");
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sc_start(1, SC_NS);
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sc_start(1, SC_NS);
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reset_156m25_n = 0;
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reset_156m25_n = 0;
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wb_rst_i = 1;
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wb_rst_i = 1;
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reset_xgmii_n = 0;
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reset_xgmii_n = 0;
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sc_start(1, SC_NS);
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sc_start(1, SC_NS);
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#if WAVES
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#if WAVES
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cout << "Enabling waves...\n";
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cout << "Enabling waves...\n";
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VerilatedVcdSc* tfp = new VerilatedVcdSc;
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VerilatedVcdSc* tfp = new VerilatedVcdSc;
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top->trace (tfp, 99);
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top->trace (tfp, 99);
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tfp->open ("vl_dump.vcd");
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tfp->open ("vl_dump.vcd");
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#endif
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#endif
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//==========
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//==========
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// Start of Test
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// Start of Test
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cout <<("Test beginning...\n");
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cout <<("Test beginning...\n");
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reset_156m25_n = 0;
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reset_156m25_n = 0;
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wb_rst_i = 1;
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wb_rst_i = 1;
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reset_xgmii_n = 0;
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reset_xgmii_n = 0;
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while (!tc->done) {
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while (!tc->done) {
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#if WAVES
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#if WAVES
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tfp->flush();
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tfp->flush();
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#endif
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#endif
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if (VL_TIME_Q() > 10) {
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if (VL_TIME_Q() > 10) {
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reset_156m25_n = 1;
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reset_156m25_n = 1;
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wb_rst_i = 0;
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wb_rst_i = 0;
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reset_xgmii_n = 1;
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reset_xgmii_n = 1;
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}
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}
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sc_start(1, SC_NS);
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sc_start(1, SC_NS);
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}
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}
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top->final();
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top->final();
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#if WAVES
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#if WAVES
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tfp->close();
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tfp->close();
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#endif
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#endif
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cout << "*-* All Finished *-*\n";
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cout << "*-* All Finished *-*\n";
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return(0);
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return(0);
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}
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}
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