LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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USE work.S2LIB.ALL;
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USE work.S2LIB.ALL;
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ENTITY S2 IS
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ENTITY S2 IS
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PORT (
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PORT (
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CLOCK : IN STD_LOGIC;
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CLOCK : IN STD_LOGIC;
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RESET : IN STD_LOGIC;
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RESET : IN STD_LOGIC;
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LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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SWITCH : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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SWITCH : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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BUTTON : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
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BUTTON : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
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END ENTITY S2;
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END ENTITY S2;
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ARCHITECTURE Structural OF S2 IS
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ARCHITECTURE Structural OF S2 IS
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SIGNAL CLK : STD_LOGIC;
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SIGNAL CLK : STD_LOGIC;
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SIGNAL RST : STD_LOGIC;
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SIGNAL RST : STD_LOGIC;
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SIGNAL DATA_BUS : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL DATA_BUS : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL ADDRESS_BUS : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL ADDRESS_BUS : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL RD : STD_LOGIC;
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SIGNAL RD : STD_LOGIC;
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SIGNAL WR : STD_LOGIC;
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SIGNAL WR : STD_LOGIC;
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SIGNAL BA_ADDR_SEL : STD_LOGIC;
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SIGNAL BA_ADDR_SEL : STD_LOGIC;
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SIGNAL BA_ICC_ACK : STD_LOGIC;
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SIGNAL BA_ICC_ACK : STD_LOGIC;
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SIGNAL BA_DCC_ACK : STD_LOGIC;
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SIGNAL BA_DCC_ACK : STD_LOGIC;
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SIGNAL ICC_RD : STD_LOGIC;
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SIGNAL ICC_RD : STD_LOGIC;
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SIGNAL ICC_WR : STD_LOGIC;
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SIGNAL ICC_WR : STD_LOGIC;
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SIGNAL ICC_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL ICC_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL ICC_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL ICC_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL DCC_RD : STD_LOGIC;
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SIGNAL DCC_RD : STD_LOGIC;
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SIGNAL DCC_WR : STD_LOGIC;
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SIGNAL DCC_WR : STD_LOGIC;
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SIGNAL DCC_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL DCC_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL DCC_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL DCC_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL CPU_IF : STD_LOGIC;
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SIGNAL CPU_IF : STD_LOGIC;
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SIGNAL CPU_INSTR_ADDR : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL CPU_INSTR_ADDR : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL CPU_INSTRUCTION : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL CPU_INSTRUCTION : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL CPU_RD : STD_LOGIC;
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SIGNAL CPU_RD : STD_LOGIC;
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SIGNAL CPU_WR : STD_LOGIC;
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SIGNAL CPU_WR : STD_LOGIC;
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SIGNAL CPU_DATA_ADDR : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL CPU_DATA_ADDR : STD_LOGIC_VECTOR(14 DOWNTO 0);
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SIGNAL CPU_DATA_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL CPU_DATA_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL CPU_DATA_IN : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL CPU_DATA_IN : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL MEM_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL MEM_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
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BEGIN -- ARCHITECTURE Structural
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BEGIN -- ARCHITECTURE Structural
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BA1 : S2ARB
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BA1 : S2ARB
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PORT MAP (
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PORT MAP (
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-- Main component connections
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-- Main component connections
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CLK => CLK,
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CLK => CLK,
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RST => RST,
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RST => RST,
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-- Bus requests from ICC
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-- Bus requests from ICC
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I_RD_ICC => ICC_RD,
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I_RD_ICC => ICC_RD,
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I_WR_ICC => ICC_WR,
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I_WR_ICC => ICC_WR,
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-- Bus requests from DCC
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-- Bus requests from DCC
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I_RD_DCC => DCC_RD,
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I_RD_DCC => DCC_RD,
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I_WR_DCC => DCC_WR,
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I_WR_DCC => DCC_WR,
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-- Arbiter control signals
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-- Arbiter control signals
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O_ADDRESS_MUX_SEL => BA_ADDR_SEL,
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O_ADDRESS_MUX_SEL => BA_ADDR_SEL,
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O_ACK_ICC => BA_ICC_ACK,
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O_ACK_ICC => BA_ICC_ACK,
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O_ACK_DCC => BA_DCC_ACK);
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O_ACK_DCC => BA_DCC_ACK);
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ICC1 : S2ICC
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ICC1 : S2ICC
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PORT MAP (
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PORT MAP (
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-- Main component connections
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-- Main component connections
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CLK => CLK,
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CLK => CLK,
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RST => RST,
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RST => RST,
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-- To main bus
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-- To main bus
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O_ADDRESS => ICC_ADDRESS,
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O_ADDRESS => ICC_ADDRESS,
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O_DATA => ICC_DATA,
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O_DATA => ICC_DATA,
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O_RD => ICC_RD,
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O_RD => ICC_RD,
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O_WR => ICC_WR,
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O_WR => ICC_WR,
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-- From bus arbiter
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-- From bus arbiter
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I_ACK => BA_ICC_ACK,
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I_ACK => BA_ICC_ACK,
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-- From main bus
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-- From main bus
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I_ADDRESS => ADDRESS_BUS,
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I_ADDRESS => ADDRESS_BUS,
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I_DATA => DATA_BUS,
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I_DATA => DATA_BUS,
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I_RD => RD,
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I_RD => RD,
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I_WR => WR,
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I_WR => WR,
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-- CPU specific connections
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-- CPU specific connections
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I_CPU_IF => CPU_IF,
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I_CPU_IF => CPU_IF,
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I_CPU_INSTR_ADDR => CPU_INSTR_ADDR,
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I_CPU_INSTR_ADDR => CPU_INSTR_ADDR,
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I_CPU_INSTRUCTION => CPU_INSTRUCTION);
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O_CPU_INSTRUCTION => CPU_INSTRUCTION);
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DCC1 : S2DCC
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DCC1 : S2DCC
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PORT MAP (
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PORT MAP (
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-- Main component connections
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-- Main component connections
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CLK => CLK,
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CLK => CLK,
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RST => RST,
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RST => RST,
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-- To main bus
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-- To main bus
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O_ADDRESS => DCC_ADDRESS,
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O_ADDRESS => DCC_ADDRESS,
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O_DATA => DCC_DATA,
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O_DATA => DCC_DATA,
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O_RD => DCC_RD,
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O_RD => DCC_RD,
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O_WR => DCC_WR,
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O_WR => DCC_WR,
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-- From bus arbiter
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-- From bus arbiter
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I_ACK => BA_DCC_ACK,
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I_ACK => BA_DCC_ACK,
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-- From main bus
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-- From main bus
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I_ADDRESS => ADDRESS_BUS,
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I_ADDRESS => ADDRESS_BUS,
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I_DATA => DATA_BUS,
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I_DATA => DATA_BUS,
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I_RD => RD,
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I_RD => RD,
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I_WR => WR,
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I_WR => WR,
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-- CPU specific connections
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-- CPU specific connections
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I_CPU_RD => CPU_RD,
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I_CPU_RD => CPU_RD,
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I_CPU_WR => CPU_WR,
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I_CPU_WR => CPU_WR,
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I_CPU_DATA_ADDR => CPU_DATA_ADDRESS,
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I_CPU_DATA_ADDR => CPU_DATA_ADDR,
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I_CPU_DATA => CPU_DATA_OUT,
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I_CPU_DATA => CPU_DATA_OUT,
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O_CPU_DATA => CPU_DATA_IN);
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O_CPU_DATA => CPU_DATA_IN);
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CPU1 : S2CPU
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CPU1 : S2CPU
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PORT MAP (
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PORT MAP (
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-- Main component connections
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-- Main component connections
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CLK => CLK,
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CLK => CLK,
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RST => RST,
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RST => RST,
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-- Instruction cache connections
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-- Instruction cache connections
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O_IF => CPU_IF,
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O_IF => CPU_IF,
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O_INSTR_ADDR => CPU_INSTR_ADDR,
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O_INSTR_ADDR => CPU_INSTR_ADDR,
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I_INSTRUCTION => CPU_INSTRUCTION,
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I_INSTRUCTION => CPU_INSTRUCTION,
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-- Data cache connections
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-- Data cache connections
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O_RD => CPU_RD,
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O_RD => CPU_RD,
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O_WR => CPU_WR,
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O_WR => CPU_WR,
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O_DATA_ADDR => CPU_DATA_ADDRESS,
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O_DATA_ADDR => CPU_DATA_ADDR,
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O_DATA => CPU_DATA_OUT,
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O_DATA => CPU_DATA_OUT,
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I_DATA => CPU_DATA_IN);
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I_DATA => CPU_DATA_IN);
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MEM1 : S2MEM
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MEM1 : S2MEM
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PORT MAP (
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PORT MAP (
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CLK => CLK,
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CLK => CLK,
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RST => RST,
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RST => RST,
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I_RD => RD,
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I_RD => RD,
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I_WR => WR,
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I_WR => WR,
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I_ADDRESS => ADDRESS_BUS,
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I_ADDRESS => ADDRESS_BUS,
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I_DATA => DATA_BUS,
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I_DATA => DATA_BUS,
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O_DATA => MEM_DATA);
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O_DATA => MEM_DATA);
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END ARCHITECTURE Structural;
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END ARCHITECTURE Structural;
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