//
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//
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//
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//
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// Filename: busmaster_tb.cpp
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// Filename: busmaster_tb.cpp
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//
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//
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// Project: FPGA library development (XuLA2 development board)
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// Project: FPGA library development (XuLA2 development board)
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//
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//
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// Purpose: This is piped version of the testbench for the busmaster
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// Purpose: This is piped version of the testbench for the busmaster
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// verilog code. The busmaster code is designed to be a complete
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// verilog code. The busmaster code is designed to be a complete
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// code set implementing all of the functionality of the XESS
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// code set implementing all of the functionality of the XESS
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// XuLA2 development board. If done well, the programs talking to
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// XuLA2 development board. If done well, the programs talking to
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// this one should be able to talk to the board and apply the
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// this one should be able to talk to the board and apply the
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// same tests to the board itself.
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// same tests to the board itself.
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//
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//
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// Creator: Dan Gisselquist
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// Creator: Dan Gisselquist
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// Gisselquist Tecnology, LLC
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// Gisselquist Tecnology, LLC
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//
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//
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// Copyright: 2015
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// Copyright: 2015
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//
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//
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//
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//
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#include <signal.h>
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#include <signal.h>
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#include <time.h>
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#include <time.h>
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#include "verilated.h"
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#include "verilated.h"
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#include "Vbusmaster.h"
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#include "Vbusmaster.h"
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#include "testb.h"
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#include "testb.h"
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// #include "twoc.h"
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// #include "twoc.h"
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#include "pipecmdr.h"
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#include "pipecmdr.h"
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#include "qspiflashsim.h"
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#include "qspiflashsim.h"
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#include "sdramsim.h"
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#include "sdramsim.h"
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#include "port.h"
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#include "port.h"
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// Add a reset line, since Vbusmaster doesn't have one
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// Add a reset line, since Vbusmaster doesn't have one
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class Vbusmasterr : public Vbusmaster {
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class Vbusmasterr : public Vbusmaster {
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public:
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public:
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int i_rst;
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int i_rst;
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virtual ~Vbusmasterr() {}
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virtual ~Vbusmasterr() {}
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};
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};
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// No particular "parameters" need definition or redefinition here.
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// No particular "parameters" need definition or redefinition here.
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class BUSMASTER_TB : public PIPECMDR<Vbusmasterr> {
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class BUSMASTER_TB : public PIPECMDR<Vbusmasterr> {
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public:
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public:
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unsigned long m_tx_busy_count;
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unsigned long m_tx_busy_count;
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QSPIFLASHSIM m_flash;
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QSPIFLASHSIM m_flash;
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SDRAMSIM m_sdram;
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SDRAMSIM m_sdram;
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unsigned m_last_led;
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unsigned m_last_led;
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time_t m_start_time;
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time_t m_start_time;
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BUSMASTER_TB(void) : PIPECMDR(FPGAPORT) {
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BUSMASTER_TB(void) : PIPECMDR(FPGAPORT) {
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m_start_time = time(NULL);
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m_start_time = time(NULL);
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}
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}
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void reset(void) {
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void reset(void) {
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m_core->i_clk = 1;
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m_core->i_clk = 1;
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m_core->eval();
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m_core->eval();
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}
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}
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void tick(void) {
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void tick(void) {
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if ((m_tickcount & ((1<<28)-1))==0) {
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if ((m_tickcount & ((1<<28)-1))==0) {
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double ticks_per_second = m_tickcount;
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double ticks_per_second = m_tickcount;
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ticks_per_second /= (double)(time(NULL) - m_start_time);
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ticks_per_second /= (double)(time(NULL) - m_start_time);
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printf(" ******** %.6f TICKS PER SECOND\n",
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printf(" ******** %.6f TICKS PER SECOND\n",
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ticks_per_second);
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ticks_per_second);
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}
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}
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// Set up the bus before any clock tick
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// Set up the bus before any clock tick
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m_core->i_clk = 1;
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m_core->i_clk = 1;
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m_core->i_spi_miso = m_flash(m_core->o_sf_cs_n,
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m_core->i_spi_miso = m_flash(m_core->o_sf_cs_n,
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m_core->o_spi_sck,
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m_core->o_spi_sck,
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m_core->o_spi_mosi)&0x02;
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m_core->o_spi_mosi)&0x02;
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m_core->i_ram_data = m_sdram(1,
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m_core->i_ram_data = m_sdram(1,
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m_core->o_ram_cke, m_core->o_ram_cs_n,
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m_core->o_ram_cke, m_core->o_ram_cs_n,
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m_core->o_ram_ras_n, m_core->o_ram_cas_n,
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m_core->o_ram_ras_n, m_core->o_ram_cas_n,
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m_core->o_ram_we_n, m_core->o_ram_bs,
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m_core->o_ram_we_n, m_core->o_ram_bs,
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m_core->o_ram_addr, m_core->o_ram_drive_data,
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m_core->o_ram_addr, m_core->o_ram_drive_data,
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m_core->o_ram_data);
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m_core->o_ram_data);
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PIPECMDR::tick();
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PIPECMDR::tick();
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bool writeout = false;
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bool writeout = false;
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/*
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/*
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if (m_core->v__DOT__runio__DOT__themouse__DOT__driver__DOT__rx_stb)
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if (m_core->v__DOT__sdram__DOT__r_pending)
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writeout = true;
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writeout = true;
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else if (m_core->v__DOT__runio__DOT__themouse__DOT__driver__DOT__ps2iface__DOT__state != m_last_ps2_state)
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else if (m_core->v__DOT__sdram__DOT__bank_active[0])
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writeout = true;
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writeout = true;
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else if (m_core->v__DOT__runio__DOT__themouse__DOT__m_state != m_last_mouse_state)
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else if (m_core->v__DOT__sdram__DOT__bank_active[1])
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writeout = true;
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writeout = true;
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else if (m_core->i_ps2 != m_last_ps2)
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else if (m_core->v__DOT__sdram__DOT__bank_active[2])
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writeout = true;
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writeout = true;
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else if (m_core->o_ps2 != m_last_ops2)
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else if (m_core->v__DOT__sdram__DOT__bank_active[3])
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writeout = true;
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else if (m_core->v__DOT__runio__DOT__themouse__DOT__driver__DOT__ps2_perr)
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writeout = true;
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else if (m_core->v__DOT__runio__DOT__themouse__DOT__driver__DOT__ps2_ferr)
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writeout = true;
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writeout = true;
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*/
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*/
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// if ((m_core->v__DOT__genbus__DOT__runwb__DOT__o_wb_cyc)||(m_core->v__DOT__bus_cyc))
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// writeout = true;
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// else if (m_last_cyc)
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// writeout = true;
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if ((m_tickcount > 0x5010)&&(m_core->v__DOT__sdram__DOT__r_state != 0))
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writeout = true;
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else if ((m_core->v__DOT__dwb_cyc)&&((m_core->v__DOT__wb_stb)
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||(m_core->v__DOT__dwb_stall)
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||(m_core->v__DOT__dwb_ack)))
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writeout = true;
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else if (m_core->v__DOT__dwb_cyc)
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writeout = true;
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else if (m_core->v__DOT__sdram__DOT__need_refresh)
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writeout = true;
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else if ((m_core->v__DOT__wbu_cyc)&&((m_core->v__DOT__wbu_addr == 0x106)||(m_core->v__DOT__wbu_addr == 0x0107)))
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writeout = true;
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if (m_tickcount < 0x05010)
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writeout = false;
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if (writeout) {
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if (writeout) {
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printf("%08lx:", m_tickcount);
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printf("%08lx:", m_tickcount);
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printf("(%d,%d->%d),(%d,%d->%d)|%c[%08x/%08x]@%08x %d%d%c",
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printf("(%d,%d->%d),(%d,%d->%d)|%c[%08x/%08x]@%08x %d%d%c",
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m_core->v__DOT__wbu_cyc,
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m_core->v__DOT__wbu_cyc,
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m_core->v__DOT__dwb_cyc, // was zip_cyc
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m_core->v__DOT__dwb_cyc, // was zip_cyc
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m_core->v__DOT__wb_cyc,
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m_core->v__DOT__wb_cyc,
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//
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//
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m_core->v__DOT__wbu_stb,
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m_core->v__DOT__wbu_stb,
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// 0, // m_core->v__DOT__dwb_stb, // was zip_stb
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// 0, // m_core->v__DOT__dwb_stb, // was zip_stb
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m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_stb_gbl,
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m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_stb_gbl,
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m_core->v__DOT__wb_stb,
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m_core->v__DOT__wb_stb,
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//
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//
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(m_core->v__DOT__wb_we)?'W':'R',
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(m_core->v__DOT__wb_we)?'W':'R',
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m_core->v__DOT__wb_data,
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m_core->v__DOT__wb_data,
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m_core->v__DOT__dwb_idata,
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m_core->v__DOT__dwb_idata,
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m_core->v__DOT__wb_addr,
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m_core->v__DOT__wb_addr,
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m_core->v__DOT__dwb_ack,
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m_core->v__DOT__dwb_ack,
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m_core->v__DOT__dwb_stall,
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m_core->v__DOT__dwb_stall,
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(m_core->v__DOT__wb_err)?'E':'.');
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(m_core->v__DOT__wb_err)?'E':'.');
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printf("%c[%d%d%d%d,%d:%04x%c]@%06x(%d) ->%06x%c",
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printf("%c[%d%d%d%d,%d:%04x%c]@%06x(%d) ->%06x%c",
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(m_core->v__DOT__sdram_sel)?'!':' ',
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(m_core->v__DOT__sdram_sel)?'!':' ',
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m_core->o_ram_cs_n, m_core->o_ram_ras_n,
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m_core->o_ram_cs_n, m_core->o_ram_ras_n,
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m_core->o_ram_cas_n, m_core->o_ram_we_n,
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m_core->o_ram_cas_n, m_core->o_ram_we_n,
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m_core->o_ram_bs, m_core->o_ram_data,
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m_core->o_ram_bs, m_core->o_ram_data,
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(m_core->o_ram_drive_data)?'D':'-',
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(m_core->o_ram_drive_data)?'D':'-',
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m_core->o_ram_addr,
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m_core->o_ram_addr,
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(m_core->o_ram_addr>>10)&1,
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(m_core->o_ram_addr>>10)&1,
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m_core->i_ram_data,
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m_core->i_ram_data,
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(m_core->o_ram_drive_data)?'-':'V');
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(m_core->o_ram_drive_data)?'-':'V');
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printf(" SD[%d,%d-%3x%d]",
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printf(" SD[%d,%d-%3x%d]",
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m_core->v__DOT__sdram__DOT__r_state,
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m_core->v__DOT__sdram__DOT__r_state,
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m_sdram.pwrup(),
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m_sdram.pwrup(),
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m_core->v__DOT__sdram__DOT__refresh_clk,
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m_core->v__DOT__sdram__DOT__refresh_clk,
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m_core->v__DOT__sdram__DOT__need_refresh);
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m_core->v__DOT__sdram__DOT__need_refresh);
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printf(" BNK[%d:%6x,%d:%6x,%d:%6x,%d:%6x],%x%d",
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printf(" BNK[%d:%6x,%d:%6x,%d:%6x,%d:%6x],%x%d",
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m_core->v__DOT__sdram__DOT__bank_active[0],
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m_core->v__DOT__sdram__DOT__bank_active[0],
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m_core->v__DOT__sdram__DOT__bank_row[0],
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m_core->v__DOT__sdram__DOT__bank_row[0],
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m_core->v__DOT__sdram__DOT__bank_active[1],
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m_core->v__DOT__sdram__DOT__bank_active[1],
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m_core->v__DOT__sdram__DOT__bank_row[1],
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m_core->v__DOT__sdram__DOT__bank_row[1],
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m_core->v__DOT__sdram__DOT__bank_active[2],
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m_core->v__DOT__sdram__DOT__bank_active[2],
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m_core->v__DOT__sdram__DOT__bank_row[2],
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m_core->v__DOT__sdram__DOT__bank_row[2],
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m_core->v__DOT__sdram__DOT__bank_active[3],
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m_core->v__DOT__sdram__DOT__bank_active[3],
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m_core->v__DOT__sdram__DOT__bank_row[3],
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m_core->v__DOT__sdram__DOT__bank_row[3],
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m_core->v__DOT__sdram__DOT__clocks_til_idle,
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m_core->v__DOT__sdram__DOT__clocks_til_idle,
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m_core->v__DOT__sdram__DOT__r_barrell_ack);
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m_core->v__DOT__sdram__DOT__r_barrell_ack);
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printf(" %s%s%c[%08x@%06x]",
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printf(" %s%s%c[%08x@%06x]",
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(m_core->v__DOT__sdram__DOT__bus_cyc)?"C":" ",
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(m_core->v__DOT__sdram__DOT__bus_cyc)?"C":" ",
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(m_core->v__DOT__sdram__DOT__r_pending)?"PND":" ",
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(m_core->v__DOT__sdram__DOT__r_pending)?"PND":" ",
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(m_core->v__DOT__sdram__DOT__r_we)?'W':'R',
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(m_core->v__DOT__sdram__DOT__r_we)?'W':'R',
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(m_core->v__DOT__sdram__DOT__r_data),
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(m_core->v__DOT__sdram__DOT__r_we)
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?(m_core->v__DOT__sdram__DOT__r_data)
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:(m_core->v__DOT__sdram_data),
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(m_core->v__DOT__sdram__DOT__r_addr));
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(m_core->v__DOT__sdram__DOT__r_addr));
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printf("%s%s%s%s%s%s%s%s%s%s%s%s%s%s%2x",
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printf("%s%s%s%s%s%s%s%s%s%s%s%2x",
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(m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-",
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// (m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-",
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(m_core->v__DOT__zippy__DOT__dbg_stall)?"S":"-",
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// (m_core->v__DOT__zippy__DOT__dbg_stall)?"S":"-",
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(m_core->v__DOT__zippy__DOT__sys_dbg_cyc)?"D":"-",
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// (m_core->v__DOT__zippy__DOT__sys_dbg_cyc)?"D":"-",
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(m_core->v__DOT__zippy__DOT__cpu_lcl_cyc)?"L":"-",
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(m_core->v__DOT__zippy__DOT__cpu_lcl_cyc)?"L":"-",
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(m_core->v__DOT__zippy__DOT__cpu_dbg_stall)?"Z":"-",
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(m_core->v__DOT__zippy__DOT__cpu_dbg_stall)?"Z":"-",
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(m_core->v__DOT__zippy__DOT__cmd_halt)?"H":"-",
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(m_core->v__DOT__zippy__DOT__cmd_halt)?"H":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_cyc)?"P":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__pf_cyc)?"P":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_gbl)?"G":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_gbl)?"G":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_lcl)?"L":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__mem_cyc_lcl)?"L":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_ce)?"k":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__dcd_ce)?"k":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid)?"O":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__opvalid)?"O":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_ce)?"k":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__op_ce)?"k":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__new_pc)?"N":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__new_pc)?"N":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__clear_pipeline)?"C":"-",
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(m_core->v__DOT__zippy__DOT__thecpu__DOT__clear_pipeline)?"C":"-",
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(m_core->v__DOT__zippy__DOT__cmd_addr));
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(m_core->v__DOT__zippy__DOT__cmd_addr));
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printf("\n");
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printf("\n");
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}
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}
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}
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}
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};
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};
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BUSMASTER_TB *tb;
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BUSMASTER_TB *tb;
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void busmaster_kill(int v) {
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void busmaster_kill(int v) {
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tb->kill();
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tb->kill();
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exit(0);
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exit(0);
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}
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}
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int main(int argc, char **argv) {
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int main(int argc, char **argv) {
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Verilated::commandArgs(argc, argv);
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Verilated::commandArgs(argc, argv);
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tb = new BUSMASTER_TB;
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tb = new BUSMASTER_TB;
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// signal(SIGINT, busmaster_kill);
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// signal(SIGINT, busmaster_kill);
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tb->reset();
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tb->reset();
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while(1)
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while(1)
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tb->tick();
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tb->tick();
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exit(0);
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exit(0);
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}
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}
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