`define XULA25
|
`define XULA25
|
///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: busmaster.v
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// Filename: busmaster.v
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//
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//
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// Project: XuLA2 board
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// Project: XuLA2 board
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//
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//
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// Purpose: This is the highest level, Verilator simulatable, portion of
|
// Purpose: This is the highest level, Verilator simulatable, portion of
|
// the XuLA2 core. You should be able to successfully Verilate
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// the XuLA2 core. You should be able to successfully Verilate
|
// this file, and then build a test bench that tests and proves the
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// this file, and then build a test bench that tests and proves the
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// capability of anything within here.
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// capability of anything within here.
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//
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//
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// In general, this means the file is little more than a wishbone
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// In general, this means the file is little more than a wishbone
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// interconnect that connects multiple devices together. User-JTAG
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// interconnect that connects multiple devices together. User-JTAG
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// commands come in via i_rx_stb and i_rx_data. These are converted into
|
// commands come in via i_rx_stb and i_rx_data. These are converted into
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// wishbone bus interactions, the results of which come back out via
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// wishbone bus interactions, the results of which come back out via
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// o_tx_data and o_tx_stb.
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// o_tx_data and o_tx_stb.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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|
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//
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//
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// Configuration question #1
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// Configuration question #1
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//
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//
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// What innate capabilities are built into the board?
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// What innate capabilities are built into the board?
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//
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//
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`define INCLUDE_ZIPCPU
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`define INCLUDE_ZIPCPU
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|
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// Without the ZipCPU competing for the bus, we don't need to delay it by a
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// Without the ZipCPU competing for the bus, we don't need to delay it by a
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// cycle.
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// cycle.
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`ifndef INCLUDE_ZIPCPU
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`ifndef INCLUDE_ZIPCPU
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`define NO_ZIP_WBU_DELAY
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`define NO_ZIP_WBU_DELAY
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`endif
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`endif
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`ifdef VERILATOR
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`ifdef VERILATOR
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`define NO_ZIP_WBU_DELAY
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`define NO_ZIP_WBU_DELAY
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`endif
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`endif
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|
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`define IMPLEMENT_ONCHIP_RAM
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`define IMPLEMENT_ONCHIP_RAM
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`ifndef VERILATOR
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`ifndef VERILATOR
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`ifndef XULA25
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`ifndef XULA25
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// `define FANCY_ICAP_ACCESS
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// `define FANCY_ICAP_ACCESS
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`endif
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`endif
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`endif
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`endif
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`define FLASH_ACCESS
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`define FLASH_ACCESS
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`ifdef XULA25
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`ifdef XULA25
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`define SDCARD_ACCESS
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`define SDCARD_ACCESS
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`endif
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`endif
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//
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//
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|
|
|
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//
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//
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// Configuration question #2
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// Configuration question #2
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//
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//
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// Are any scopes built in to the board?
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// Are any scopes built in to the board?
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//
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//
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|
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//
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//
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// Position #1: The flash scope, or perhaps the wishbone bus/uart/jtag scope
|
// Position #1: The flash scope, or perhaps the wishbone bus/uart/jtag scope
|
//
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//
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// `define FLASH_SCOPE
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// `define FLASH_SCOPE
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`ifndef FLASH_SCOPE
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`ifndef FLASH_SCOPE
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// `define WBUS_SCOPE // Occupies the FLASH_SCOPE location, so both cannot be active
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// `define WBUS_SCOPE // Occupies the FLASH_SCOPE location, so both cannot be active
|
`endif
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`endif
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//
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//
|
// Position #2: The ICAP configuration scope, could also be the SDCard scope
|
// Position #2: The ICAP configuration scope, could also be the SDCard scope
|
// depending on how we configure ourselves here
|
// depending on how we configure ourselves here
|
//
|
//
|
`ifdef XULA25
|
`ifdef XULA25
|
`ifdef FANCY_ICAP_ACCESS
|
`ifdef FANCY_ICAP_ACCESS
|
`define CFG_SCOPE // Only defined if we have the access ...
|
// `define CFG_SCOPE // Only defined if we have the access ...
|
`else
|
`else
|
`ifdef SDCARD_ACCESS
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`ifdef SDCARD_ACCESS
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`define SDCARD_SCOPE
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// `define SDCARD_SCOPE
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
//
|
//
|
// Position #3: The SDRAM scope / UART scope (never both)
|
// Position #3: The SDRAM scope / UART scope (never both)
|
//
|
//
|
// `define SDRAM_SCOPE
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// `define SDRAM_SCOPE
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// `define UART_SCOPE
|
// `define UART_SCOPE
|
//
|
//
|
// Position #4: The Zip CPU scope
|
// Position #4: The Zip CPU scope
|
//
|
//
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`ifdef INCLUDE_ZIPCPU
|
`ifdef INCLUDE_ZIPCPU
|
`ifdef VERILATOR
|
`ifdef VERILATOR
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`define ZIP_SCOPE
|
`define ZIP_SCOPE
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`else // VERILATOR
|
`else // VERILATOR
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`ifdef XULA25
|
`ifdef XULA25
|
`define ZIP_SCOPE
|
// `define ZIP_SCOPE
|
`endif // XULA25
|
`endif // XULA25
|
`endif // VERILATOR
|
`endif // VERILATOR
|
`endif // INCLUDE_ZIPCPU
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`endif // INCLUDE_ZIPCPU
|
|
|
module busmaster(i_clk, i_rst,
|
module busmaster(i_clk, i_rst,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
// The SPI Flash lines
|
// The SPI Flash lines
|
o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
|
o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
|
// The SDRAM lines
|
// The SDRAM lines
|
o_ram_cs_n, o_ram_cke, o_ram_ras_n, o_ram_cas_n,
|
o_ram_cs_n, o_ram_cke, o_ram_ras_n, o_ram_cas_n,
|
o_ram_we_n, o_ram_bs, o_ram_addr,
|
o_ram_we_n, o_ram_bs, o_ram_addr,
|
o_ram_drive_data, i_ram_data, o_ram_data,
|
o_ram_drive_data, i_ram_data, o_ram_data,
|
o_ram_dqm,
|
o_ram_dqm,
|
// Generic GPIO
|
// Generic GPIO
|
i_gpio, o_gpio, o_pwm,
|
i_gpio, o_gpio, o_pwm,
|
i_rx_uart, o_tx_uart);
|
i_rx_uart, o_tx_uart);
|
parameter ZIP_ADDRESS_WIDTH=24, NGPO=15, NGPI=15,
|
parameter ZIP_ADDRESS_WIDTH=24, NGPO=15, NGPI=15,
|
ZA=ZIP_ADDRESS_WIDTH;
|
ZA=ZIP_ADDRESS_WIDTH;
|
input i_clk, i_rst;
|
input i_clk, i_rst;
|
// The bus commander, via an external JTAG port
|
// The bus commander, via an external JTAG port
|
input i_rx_stb;
|
input i_rx_stb;
|
input [7:0] i_rx_data;
|
input [7:0] i_rx_data;
|
output wire o_tx_stb;
|
output wire o_tx_stb;
|
output wire [7:0] o_tx_data;
|
output wire [7:0] o_tx_data;
|
input i_tx_busy;
|
input i_tx_busy;
|
// SPI flash control
|
// SPI flash control
|
output wire o_sf_cs_n, o_sd_cs_n;
|
output wire o_sf_cs_n, o_sd_cs_n;
|
output wire o_spi_sck, o_spi_mosi;
|
output wire o_spi_sck, o_spi_mosi;
|
input i_spi_miso;
|
input i_spi_miso;
|
// SDRAM control
|
// SDRAM control
|
output wire o_ram_cs_n, o_ram_cke;
|
output wire o_ram_cs_n, o_ram_cke;
|
output wire o_ram_ras_n, o_ram_cas_n, o_ram_we_n;
|
output wire o_ram_ras_n, o_ram_cas_n, o_ram_we_n;
|
output wire [12:0] o_ram_addr;
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output wire [12:0] o_ram_addr;
|
output wire [1:0] o_ram_bs;
|
output wire [1:0] o_ram_bs;
|
output wire o_ram_drive_data;
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output wire o_ram_drive_data;
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input [15:0] i_ram_data;
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input [15:0] i_ram_data;
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output wire [15:0] o_ram_data;
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output wire [15:0] o_ram_data;
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output wire [1:0] o_ram_dqm;
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output wire [1:0] o_ram_dqm;
|
input [(NGPI-1):0] i_gpio;
|
input [(NGPI-1):0] i_gpio;
|
output wire [(NGPO-1):0] o_gpio;
|
output wire [(NGPO-1):0] o_gpio;
|
output wire o_pwm;
|
output wire o_pwm;
|
input i_rx_uart;
|
input i_rx_uart;
|
output wire o_tx_uart;
|
output wire o_tx_uart;
|
|
|
|
|
//
|
//
|
//
|
//
|
// Master wishbone wires
|
// Master wishbone wires
|
//
|
//
|
//
|
//
|
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
|
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
|
wire [31:0] wb_data, wb_idata, wb_addr;
|
wire [31:0] wb_data, wb_idata, wb_addr;
|
|
|
//
|
//
|
//
|
//
|
// First BUS master source: The JTAG
|
// First BUS master source: The JTAG
|
//
|
//
|
//
|
//
|
wire [31:0] dwb_idata;
|
wire [31:0] dwb_idata;
|
|
|
// Wires going to devices
|
// Wires going to devices
|
wire wbu_cyc, wbu_stb, wbu_we;
|
wire wbu_cyc, wbu_stb, wbu_we;
|
wire [31:0] wbu_addr, wbu_data;
|
wire [31:0] wbu_addr, wbu_data;
|
// and then coming from devices
|
// and then coming from devices
|
wire wbu_ack, wbu_stall, wbu_err;
|
wire wbu_ack, wbu_stall, wbu_err;
|
wire [31:0] wbu_idata;
|
wire [31:0] wbu_idata;
|
// And then headed back home
|
// And then headed back home
|
wire w_interrupt;
|
wire w_interrupt;
|
// Oh, and the debug control for the ZIP CPU
|
// Oh, and the debug control for the ZIP CPU
|
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
|
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
|
assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]));
|
assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]));
|
wire [31:0] zip_dbg_data;
|
wire [31:0] zip_dbg_data;
|
wire wbu_dbg;
|
wire wbu_dbg;
|
wbubus genbus(i_clk, i_rx_stb, i_rx_data,
|
wbubus genbus(i_clk, i_rx_stb, i_rx_data,
|
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
|
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
|
`ifdef INCLUDE_ZIPCPU
|
`ifdef INCLUDE_ZIPCPU
|
((~wbu_zip_sel)&&(wbu_ack))
|
((~wbu_zip_sel)&&(wbu_ack))
|
||((wbu_zip_sel)&&(zip_dbg_ack)),
|
||((wbu_zip_sel)&&(zip_dbg_ack)),
|
((~wbu_zip_sel)&&(wbu_stall))
|
((~wbu_zip_sel)&&(wbu_stall))
|
||((wbu_zip_sel)&&(zip_dbg_stall)),
|
||((wbu_zip_sel)&&(zip_dbg_stall)),
|
wbu_err, (wbu_zip_sel)?zip_dbg_data:dwb_idata,
|
wbu_err, (wbu_zip_sel)?zip_dbg_data:dwb_idata,
|
`else
|
`else
|
wbu_ack, wbu_stall,
|
wbu_ack, wbu_stall,
|
wbu_err, dwb_idata,
|
wbu_err, dwb_idata,
|
`endif
|
`endif
|
w_interrupt,
|
w_interrupt,
|
o_tx_stb, o_tx_data, i_tx_busy,
|
o_tx_stb, o_tx_data, i_tx_busy,
|
wbu_dbg);
|
wbu_dbg);
|
|
|
|
|
//
|
//
|
//
|
//
|
// Second BUS master source: The ZipCPU
|
// Second BUS master source: The ZipCPU
|
//
|
//
|
//
|
//
|
wire zip_cyc, zip_stb, zip_we, zip_cpu_int;
|
wire zip_cyc, zip_stb, zip_we, zip_cpu_int;
|
wire [(ZA-1):0] w_zip_addr;
|
wire [(ZA-1):0] w_zip_addr;
|
wire [31:0] zip_addr, zip_data;
|
wire [31:0] zip_addr, zip_data;
|
// and then coming from devices
|
// and then coming from devices
|
wire zip_ack, zip_stall, zip_err;
|
wire zip_ack, zip_stall, zip_err;
|
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
|
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
|
wire [31:0] dwb_addr, dwb_odata;
|
wire [31:0] dwb_addr, dwb_odata;
|
wire [8:0] w_ints_to_zip_cpu;
|
wire [8:0] w_ints_to_zip_cpu;
|
`ifdef INCLUDE_ZIPCPU
|
`ifdef INCLUDE_ZIPCPU
|
`ifdef ZIP_SCOPE
|
`ifdef ZIP_SCOPE
|
wire [31:0] zip_debug;
|
wire [31:0] zip_debug;
|
`endif
|
`endif
|
`ifdef XULA25
|
`ifdef XULA25
|
zipsystem #(24'h2000,ZA,10,1,9)
|
zipsystem #(24'h2000,ZA,10,1,9)
|
zippy(i_clk, 1'b0,
|
zippy(i_clk, 1'b0,
|
// Zippys wishbone interface
|
// Zippys wishbone interface
|
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
|
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
|
zip_ack, zip_stall, dwb_idata, zip_err,
|
zip_ack, zip_stall, dwb_idata, zip_err,
|
w_ints_to_zip_cpu, zip_cpu_int,
|
w_ints_to_zip_cpu, zip_cpu_int,
|
// Debug wishbone interface
|
// Debug wishbone interface
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
wbu_data,
|
wbu_data,
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
`ifdef ZIP_SCOPE
|
`ifdef ZIP_SCOPE
|
, zip_debug
|
, zip_debug
|
`endif
|
`endif
|
);
|
);
|
`else
|
`else
|
zipbones #(24'h2000,ZA,8,1)
|
zipbones #(24'h2000,ZA,10,1)
|
zippy(i_clk, 1'b0,
|
zippy(i_clk, 1'b0,
|
// Zippys wishbone interface
|
// Zippys wishbone interface
|
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
|
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
|
zip_ack, zip_stall, dwb_idata, zip_err,
|
zip_ack, zip_stall, dwb_idata, zip_err,
|
w_interrupt, zip_cpu_int,
|
w_interrupt, zip_cpu_int,
|
// Debug wishbone interface
|
// Debug wishbone interface
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
wbu_data,
|
wbu_data,
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
`ifdef ZIP_SCOPE
|
`ifdef ZIP_SCOPE
|
, zip_debug
|
, zip_debug
|
`endif
|
`endif
|
);
|
);
|
`endif
|
`endif
|
generate
|
generate
|
if (ZA < 32)
|
if (ZA < 32)
|
assign zip_addr = { {(32-ZA){1'b0}}, w_zip_addr };
|
assign zip_addr = { {(32-ZA){1'b0}}, w_zip_addr };
|
else
|
else
|
assign zip_addr = w_zip_addr;
|
assign zip_addr = w_zip_addr;
|
endgenerate
|
endgenerate
|
|
|
|
|
//
|
//
|
//
|
//
|
// And an arbiter to decide who gets to access the bus
|
// And an arbiter to decide who gets to access the bus
|
//
|
//
|
//
|
//
|
/*
|
/*
|
wbarbiter #(32,32) wbu_zip_arbiter(i_clk, i_rst,
|
wbarbiter #(32,32) wbu_zip_arbiter(i_clk, i_rst,
|
// The UART interface Master
|
// The UART interface Master
|
wbu_addr, wbu_data, wbu_we, (wbu_stb)&&(~wbu_zip_sel),
|
wbu_addr, wbu_data, wbu_we, (wbu_stb)&&(~wbu_zip_sel),
|
(wbu_cyc)&&(~wbu_zip_sel), wbu_ack, wbu_stall, wbu_err,
|
(wbu_cyc)&&(~wbu_zip_sel), wbu_ack, wbu_stall, wbu_err,
|
// The ZIP CPU Master
|
// The ZIP CPU Master
|
zip_addr, zip_data, zip_we, zip_stb,
|
zip_addr, zip_data, zip_we, zip_stb,
|
zip_cyc, zip_ack, zip_stall, zip_err,
|
zip_cyc, zip_ack, zip_stall, zip_err,
|
// Common bus returns
|
// Common bus returns
|
dwb_addr,dwb_odata,dwb_we,dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err);
|
dwb_addr,dwb_odata,dwb_we,dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err);
|
*/
|
*/
|
wbpriarbiter #(32,32) wbu_zip_arbiter(i_clk,
|
wbpriarbiter #(32,32) wbu_zip_arbiter(i_clk,
|
// The ZIP CPU Master -- gets priority in the arbiter
|
// The ZIP CPU Master -- gets priority in the arbiter
|
zip_cyc, zip_stb, zip_we, zip_addr, zip_data,
|
zip_cyc, zip_stb, zip_we, zip_addr, zip_data,
|
zip_ack, zip_stall, zip_err,
|
zip_ack, zip_stall, zip_err,
|
// The JTAG interface Master, secondary priority,
|
// The JTAG interface Master, secondary priority,
|
// will suffer a 1clk delay in arbitration
|
// will suffer a 1clk delay in arbitration
|
(wbu_cyc)&&(~wbu_zip_sel), (wbu_stb)&&(~wbu_zip_sel), wbu_we,
|
(wbu_cyc)&&(~wbu_zip_sel), (wbu_stb)&&(~wbu_zip_sel), wbu_we,
|
wbu_addr, wbu_data,
|
wbu_addr, wbu_data,
|
wbu_ack, wbu_stall, wbu_err,
|
wbu_ack, wbu_stall, wbu_err,
|
// Common bus returns
|
// Common bus returns
|
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
|
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
|
dwb_ack, dwb_stall, dwb_err);
|
dwb_ack, dwb_stall, dwb_err);
|
|
|
//
|
//
|
//
|
//
|
// And because the ZIP CPU and the Arbiter create an unacceptable
|
// And because the ZIP CPU and the Arbiter create an unacceptable
|
// delay, we fail timing. So we add in a delay cycle ...
|
// delay, we fail timing. So we add in a delay cycle ...
|
//
|
//
|
//
|
//
|
`ifdef NO_ZIP_WBU_DELAY
|
`ifdef NO_ZIP_WBU_DELAY
|
assign wb_cyc = dwb_cyc;
|
assign wb_cyc = dwb_cyc;
|
assign wb_stb = dwb_stb;
|
assign wb_stb = dwb_stb;
|
assign wb_we = dwb_we;
|
assign wb_we = dwb_we;
|
assign wb_addr = dwb_addr;
|
assign wb_addr = dwb_addr;
|
assign wb_data = dwb_odata;
|
assign wb_data = dwb_odata;
|
assign dwb_idata = wb_idata;
|
assign dwb_idata = wb_idata;
|
assign dwb_ack = wb_ack;
|
assign dwb_ack = wb_ack;
|
assign dwb_stall = wb_stall;
|
assign dwb_stall = wb_stall;
|
assign dwb_err = wb_err;
|
assign dwb_err = wb_err;
|
`else
|
`else
|
busdelay wbu_zip_delay(i_clk,
|
busdelay wbu_zip_delay(i_clk,
|
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
|
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
|
dwb_ack, dwb_stall, dwb_idata, dwb_err,
|
dwb_ack, dwb_stall, dwb_idata, dwb_err,
|
wb_cyc, wb_stb, wb_we, wb_addr, wb_data,
|
wb_cyc, wb_stb, wb_we, wb_addr, wb_data,
|
wb_ack, wb_stall, wb_idata, wb_err);
|
wb_ack, wb_stall, wb_idata, wb_err);
|
`endif
|
`endif
|
|
|
|
|
`else // if no ZIP_CPU
|
`else // if no ZIP_CPU
|
assign zip_cyc = 1'b0;
|
assign zip_cyc = 1'b0;
|
assign zip_stb = 1'b0;
|
assign zip_stb = 1'b0;
|
assign zip_we = 1'b0;
|
assign zip_we = 1'b0;
|
assign zip_cpu_int = 1'b0;
|
assign zip_cpu_int = 1'b0;
|
assign zip_addr = 32'h000;
|
assign zip_addr = 32'h000;
|
assign zip_data = 32'h000;
|
assign zip_data = 32'h000;
|
|
|
reg r_zip_dbg_ack;
|
reg r_zip_dbg_ack;
|
initial r_zip_dbg_ack = 1'b0;
|
initial r_zip_dbg_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_zip_dbg_ack <= ((wbu_cyc)&&(wbu_zip_sel)&(wbu_stb));
|
r_zip_dbg_ack <= ((wbu_cyc)&&(wbu_zip_sel)&(wbu_stb));
|
assign zip_dbg_ack = r_zip_dbg_ack;
|
assign zip_dbg_ack = r_zip_dbg_ack;
|
assign zip_dbg_stall = 1'b0;
|
assign zip_dbg_stall = 1'b0;
|
assign zip_dbg_data = 32'h000;
|
assign zip_dbg_data = 32'h000;
|
|
|
assign dwb_addr = wbu_addr;
|
assign dwb_addr = wbu_addr;
|
assign dwb_odata = wbu_data;
|
assign dwb_odata = wbu_data;
|
assign dwb_we = wbu_we;
|
assign dwb_we = wbu_we;
|
assign dwb_stb = (wbu_stb);
|
assign dwb_stb = (wbu_stb);
|
assign dwb_cyc = (wbu_cyc);
|
assign dwb_cyc = (wbu_cyc);
|
|
assign wb_cyc = dwb_cyc;
|
|
assign wb_stb = dwb_stb;
|
|
assign wb_we = dwb_we;
|
|
assign wb_addr = dwb_addr;
|
|
assign wb_data = dwb_odata;
|
assign wbu_ack = dwb_ack;
|
assign wbu_ack = dwb_ack;
|
assign wbu_stall = dwb_stall;
|
assign wbu_stall = dwb_stall;
|
assign dwb_idata = wb_idata;
|
assign dwb_idata = wb_idata;
|
assign wbu_err = dwb_err;
|
assign wbu_err = dwb_err;
|
`endif
|
`endif
|
|
|
|
|
|
|
wire io_sel, pwm_sel, uart_sel, flash_sel, flctl_sel, scop_sel,
|
wire io_sel, pwm_sel, uart_sel, flash_sel, flctl_sel, scop_sel,
|
cfg_sel, mem_sel, sdram_sel, sdcard_sel,
|
cfg_sel, mem_sel, sdram_sel, sdcard_sel,
|
none_sel, many_sel, io_bank;
|
none_sel, many_sel, io_bank;
|
wire io_ack, flash_ack, scop_ack, cfg_ack, mem_ack,
|
wire io_ack, flash_ack, scop_ack, cfg_ack, mem_ack,
|
sdram_ack, sdcard_ack, uart_ack, pwm_ack;
|
sdram_ack, sdcard_ack, uart_ack, pwm_ack;
|
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall,
|
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall,
|
sdram_stall, sdcard_stall, uart_stall, pwm_stall;
|
sdram_stall, sdcard_stall, uart_stall, pwm_stall;
|
|
|
wire [31:0] io_data, flash_data, scop_data, cfg_data, mem_data,
|
wire [31:0] io_data, flash_data, scop_data, cfg_data, mem_data,
|
sdram_data, sdcard_data, uart_data, pwm_data;
|
sdram_data, sdcard_data, uart_data, pwm_data;
|
reg [31:0] bus_err_addr;
|
reg [31:0] bus_err_addr;
|
|
|
assign wb_ack = (wb_cyc)&&((io_ack)||(uart_ack)||(pwm_ack)
|
assign wb_ack = (wb_cyc)&&((io_ack)||(uart_ack)||(pwm_ack)
|
||(scop_ack)||(cfg_ack)
|
||(scop_ack)||(cfg_ack)
|
||(mem_ack)||(flash_ack)||(sdram_ack)
|
||(mem_ack)||(flash_ack)||(sdram_ack)
|
||(sdcard_ack)
|
||(sdcard_ack)
|
||((none_sel)&&(1'b1)));
|
||((none_sel)&&(1'b1)));
|
assign wb_stall = ((io_sel)&&(io_stall))
|
assign wb_stall = ((io_sel)&&(io_stall))
|
||((uart_sel)&&(uart_stall))
|
||((uart_sel)&&(uart_stall))
|
||((pwm_sel)&&(pwm_stall))
|
||((pwm_sel)&&(pwm_stall))
|
||((scop_sel)&&(scop_stall))
|
||((scop_sel)&&(scop_stall))
|
||((cfg_sel)&&(cfg_stall))
|
||((cfg_sel)&&(cfg_stall))
|
||((mem_sel)&&(mem_stall))
|
||((mem_sel)&&(mem_stall))
|
||((sdram_sel)&&(sdram_stall))
|
||((sdram_sel)&&(sdram_stall))
|
||((sdcard_sel)&&(sdcard_stall))
|
||((sdcard_sel)&&(sdcard_stall))
|
||((flash_sel||flctl_sel)&&(flash_stall));
|
||((flash_sel||flctl_sel)&&(flash_stall));
|
// (none_sel)&&(1'b0)
|
// (none_sel)&&(1'b0)
|
|
|
/*
|
/*
|
assign wb_idata = (io_ack)?io_data
|
assign wb_idata = (io_ack)?io_data
|
: ((scop_ack)?scop_data
|
: ((scop_ack)?scop_data
|
: ((cfg_ack)?cfg_data
|
: ((cfg_ack)?cfg_data
|
: ((mem_ack)?mem_data
|
: ((mem_ack)?mem_data
|
: ((flash_ack)?flash_data
|
: ((flash_ack)?flash_data
|
: 32'h00))));
|
: 32'h00))));
|
*/
|
*/
|
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
|
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
|
: ((uart_ack|pwm_ack)?((uart_ack)?uart_data: pwm_data)
|
: ((uart_ack|pwm_ack)?((uart_ack)?uart_data: pwm_data)
|
: ((cfg_ack) ? cfg_data
|
: ((cfg_ack) ? cfg_data
|
: ((sdram_ack|sdcard_ack)
|
: ((sdram_ack|sdcard_ack)
|
?((sdram_ack)? sdram_data : sdcard_data)
|
?((sdram_ack)? sdram_data : sdcard_data)
|
: ((mem_ack)?mem_data:flash_data)))); // if (flash_ack)
|
: ((mem_ack)?mem_data:flash_data)))); // if (flash_ack)
|
assign wb_err = ((wb_stb)&&(none_sel || many_sel))
|
assign wb_err = ((wb_stb)&&(none_sel || many_sel))
|
|| ((wb_cyc)&&(many_ack));
|
|| ((wb_cyc)&&(many_ack));
|
|
|
// Addresses ...
|
// Addresses ...
|
// 0000 xxxx configuration/control registers
|
// 0000 xxxx configuration/control registers
|
// 001x xxxx Down-sampler taps (64 taps, 2 at a time)
|
// 001x xxxx Down-sampler taps (64 taps, 2 at a time)
|
// 1xxx xxxx Up-sampler taps
|
// 1xxx xxxx Up-sampler taps
|
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
|
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
|
|
|
`define SPEEDY_IO
|
`define SPEEDY_IO
|
`ifndef SPEEDY_IO
|
`ifndef SPEEDY_IO
|
|
|
wire pre_io, pre_pwm, pre_uart, pre_flctl, pre_scop;
|
wire pre_io, pre_pwm, pre_uart, pre_flctl, pre_scop;
|
assign io_bank = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
|
assign io_bank = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
|
assign pre_io = (~pre_flctl)&&(~pre_pwm)&&(~pre_uart)&&(~pre_scop);
|
assign pre_io = (~pre_flctl)&&(~pre_pwm)&&(~pre_uart)&&(~pre_scop);
|
assign io_sel = (io_bank)&&(pre_io);
|
assign io_sel = (io_bank)&&(pre_io);
|
assign pre_pwm = (wb_addr[4: 1]== 4'h4);
|
assign pre_pwm = (wb_addr[4: 1]== 4'h4);
|
assign pwm_sel = (io_bank)&&(pre_pwm);
|
assign pwm_sel = (io_bank)&&(pre_pwm);
|
assign pre_uart = (wb_addr[4: 1]== 4'h5)||(wb_addr[4:0]==5'h7);
|
assign pre_uart = (wb_addr[4: 1]== 4'h5)||(wb_addr[4:0]==5'h7);
|
assign uart_sel = (io_bank)&&(pre_uart);
|
assign uart_sel = (io_bank)&&(pre_uart);
|
assign pre_flctl= (wb_addr[4: 2]== 3'h3);
|
assign pre_flctl= (wb_addr[4: 2]== 3'h3);
|
assign flctl_sel= (io_bank)&&(pre_flctl);
|
assign flctl_sel= (io_bank)&&(pre_flctl);
|
assign pre_scop = (wb_addr[4: 3]== 2'h3);
|
assign pre_scop = (wb_addr[4: 3]== 2'h3);
|
assign scop_sel = (io_bank)&&(pre_scop);
|
assign scop_sel = (io_bank)&&(pre_scop);
|
assign cfg_sel =((wb_cyc)&&(wb_addr[31: 6]== 26'h05));
|
assign cfg_sel =((wb_cyc)&&(wb_addr[31: 6]== 26'h05));
|
// zip_sel is not on the bus at this point
|
// zip_sel is not on the bus at this point
|
assign mem_sel =((wb_cyc)&&(wb_addr[31:13]== 19'h01));
|
assign mem_sel =((wb_cyc)&&(wb_addr[31:13]== 19'h01));
|
assign flash_sel=((wb_cyc)&&(wb_addr[31:18]== 14'h01));
|
assign flash_sel=((wb_cyc)&&(wb_addr[31:18]== 14'h01));
|
`ifdef SDCARD_ACCESS
|
`ifdef SDCARD_ACCESS
|
assign sdcard_sel=((wb_cyc)&&(wb_addr[31:2]== 30'h48));
|
assign sdcard_sel=((wb_cyc)&&(wb_addr[31:2]== 30'h48));
|
`else
|
`else
|
assign sdcard_sel=1'b0;
|
assign sdcard_sel=1'b0;
|
`endif
|
`endif
|
assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
|
assign sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
|
`else
|
`else
|
wire [3:0] iovec;
|
wire [3:0] iovec;
|
assign iovec = { wb_addr[23],wb_addr[18],wb_addr[13],wb_addr[8] };
|
assign iovec = { wb_addr[23],wb_addr[18],wb_addr[13],wb_addr[8] };
|
|
|
assign sdram_sel = (iovec[3]);
|
assign sdram_sel = (iovec[3]);
|
assign flash_sel = (iovec[3:2]==2'b01);
|
assign flash_sel = (iovec[3:2]==2'b01);
|
assign mem_sel = (iovec[3:1]==3'b001);
|
assign mem_sel = (iovec[3:1]==3'b001);
|
assign io_bank = (iovec[3:0]==4'b0001)&&(wb_addr[7:5]==3'b000);
|
assign io_bank = (iovec[3:0]==4'b0001)&&(wb_addr[7:5]==3'b000);
|
assign cfg_sel = (iovec[3:0]==4'b0001)&&(wb_addr[6]);
|
assign cfg_sel = (iovec[3:0]==4'b0001)&&(wb_addr[6]);
|
assign sdcard_sel= (iovec[3:0]==4'b0001)&&(wb_addr[6:5]==2'b01);
|
assign sdcard_sel= (iovec[3:0]==4'b0001)&&(wb_addr[6:5]==2'b01);
|
assign scop_sel = (io_bank)&&(wb_addr[7:3]==5'b00011);
|
assign scop_sel = (io_bank)&&(wb_addr[7:3]==5'b00011);
|
assign io_sel = (io_bank)&&(wb_addr[7:5]==3'b000)
|
assign io_sel = (io_bank)&&(wb_addr[7:5]==3'b000)
|
&&(wb_addr[4:0] != 5'b00111) // Not UART Ctrl
|
&&(wb_addr[4:0] != 5'b00111) // Not UART Ctrl
|
&&(wb_addr[3] != 1'b1);//Not PWM/UART/Flash/Scp
|
&&(wb_addr[3] != 1'b1);//Not PWM/UART/Flash/Scp
|
assign flctl_sel = (io_bank)&&(wb_addr[4:2]==3'b011);
|
assign flctl_sel = (io_bank)&&(wb_addr[4:2]==3'b011);
|
assign pwm_sel = (io_bank)&&(wb_addr[4:1]==4'b0100);
|
assign pwm_sel = (io_bank)&&(wb_addr[4:1]==4'b0100);
|
// Note that in the following definition, the UART is given four words
|
// Note that in the following definition, the UART is given four words
|
// despite the fact that it can probably only use 3.
|
// despite the fact that it can probably only use 3.
|
assign uart_sel = (io_bank)&&((wb_addr[4:1]==4'b0101)
|
assign uart_sel = (io_bank)&&((wb_addr[4:1]==4'b0101)
|
||(wb_addr[4:0]==5'b00111));
|
||(wb_addr[4:0]==5'b00111));
|
|
|
`endif
|
`endif
|
|
|
assign none_sel =((wb_stb)&&(~
|
assign none_sel =((wb_stb)&&(~
|
(io_sel
|
(io_sel
|
||uart_sel
|
||uart_sel
|
||pwm_sel
|
||pwm_sel
|
||flctl_sel
|
||flctl_sel
|
||scop_sel
|
||scop_sel
|
||cfg_sel
|
||cfg_sel
|
||mem_sel
|
||mem_sel
|
||sdram_sel
|
||sdram_sel
|
||sdcard_sel
|
||sdcard_sel
|
||flash_sel)));
|
||flash_sel)));
|
assign many_sel =((wb_stb)&&(
|
assign many_sel =((wb_stb)&&(
|
{3'h0, io_sel}
|
{3'h0, io_sel}
|
+{3'h0, uart_sel}
|
+{3'h0, uart_sel}
|
+{3'h0, pwm_sel}
|
+{3'h0, pwm_sel}
|
+{3'h0, flctl_sel}
|
+{3'h0, flctl_sel}
|
+{3'h0, scop_sel}
|
+{3'h0, scop_sel}
|
+{3'h0, cfg_sel}
|
+{3'h0, cfg_sel}
|
+{3'h0, mem_sel}
|
+{3'h0, mem_sel}
|
+{3'h0, sdram_sel}
|
+{3'h0, sdram_sel}
|
+{3'h0, sdcard_sel}
|
+{3'h0, sdcard_sel}
|
+{3'h0, flash_sel} > 1));
|
+{3'h0, flash_sel} > 1));
|
|
|
wire many_ack;
|
wire many_ack;
|
assign many_ack =((wb_cyc)&&(
|
assign many_ack =((wb_cyc)&&(
|
{3'h0, io_ack}
|
{3'h0, io_ack}
|
+{3'h0, uart_ack}
|
+{3'h0, uart_ack}
|
+{3'h0, pwm_ack}
|
+{3'h0, pwm_ack}
|
// FLCTL acks through the flash, so one less check here
|
// FLCTL acks through the flash, so one less check here
|
+{3'h0, scop_ack}
|
+{3'h0, scop_ack}
|
+{3'h0, cfg_ack}
|
+{3'h0, cfg_ack}
|
+{3'h0, mem_ack}
|
+{3'h0, mem_ack}
|
+{3'h0, sdram_ack}
|
+{3'h0, sdram_ack}
|
+{3'h0, sdcard_ack}
|
+{3'h0, sdcard_ack}
|
+{3'h0, flash_ack} > 1));
|
+{3'h0, flash_ack} > 1));
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (wb_err)
|
if (wb_err)
|
bus_err_addr <= wb_addr;
|
bus_err_addr <= wb_addr;
|
|
|
wire flash_interrupt, sdcard_interrupt, scop_interrupt,
|
wire flash_interrupt, sdcard_interrupt, scop_interrupt,
|
uart_rx_int, uart_tx_int, pwm_int;
|
uart_rx_int, uart_tx_int, pwm_int;
|
wire [(NGPO-1):0] w_gpio;
|
wire [(NGPO-1):0] w_gpio;
|
// The I/O processor, herein called an ioslave
|
// The I/O processor, herein called an ioslave
|
ioslave #(NGPO, NGPI) runio(i_clk,
|
ioslave #(NGPO, NGPI) runio(i_clk,
|
wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
|
wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
|
wb_data, io_ack, io_stall, io_data,
|
wb_data, io_ack, io_stall, io_data,
|
i_gpio, w_gpio,
|
i_gpio, w_gpio,
|
bus_err_addr,
|
bus_err_addr,
|
{
|
{
|
sdcard_interrupt,
|
sdcard_interrupt,
|
uart_tx_int, uart_rx_int, pwm_int, scop_interrupt,
|
uart_tx_int, uart_rx_int, pwm_int, scop_interrupt,
|
flash_interrupt,
|
flash_interrupt,
|
`ifdef XULA25
|
`ifdef XULA25
|
zip_cpu_int
|
zip_cpu_int
|
`else
|
`else
|
1'b0
|
1'b0
|
`endif
|
`endif
|
},
|
},
|
w_ints_to_zip_cpu,
|
w_ints_to_zip_cpu,
|
w_interrupt);
|
w_interrupt);
|
// 8684
|
// 8684
|
// 1'bx, 4'h0, scop_sel, scop_ack, ~scop_stall,
|
// 1'bx, 4'h0, scop_sel, scop_ack, ~scop_stall,
|
// wb_err, ~vga_interrupt, 2'b00, flash_interrupt
|
// wb_err, ~vga_interrupt, 2'b00, flash_interrupt
|
//
|
//
|
|
|
//
|
//
|
// UART device
|
// UART device
|
//
|
//
|
wire [31:0] uart_debug;
|
wire [31:0] uart_debug;
|
uartdev serialport(i_clk, i_rx_uart, o_tx_uart,
|
uartdev serialport(i_clk, i_rx_uart, o_tx_uart,
|
wb_cyc, (wb_stb)&&(uart_sel), wb_we,
|
wb_cyc, (wb_stb)&&(uart_sel), wb_we,
|
{ ~wb_addr[2], wb_addr[0]}, wb_data,
|
{ ~wb_addr[2], wb_addr[0]}, wb_data,
|
uart_ack, uart_stall, uart_data,
|
uart_ack, uart_stall, uart_data,
|
uart_rx_int, uart_tx_int,
|
uart_rx_int, uart_tx_int,
|
uart_debug);
|
uart_debug);
|
|
|
//
|
//
|
// PWM (audio) device
|
// PWM (audio) device
|
//
|
//
|
// The audio rate is given by the number of clock ticks between
|
// The audio rate is given by the number of clock ticks between
|
// samples. If we are running at 80 MHz, then divide that by the
|
// samples. If we are running at 80 MHz, then divide that by the
|
// sample rate to get the first parameter for the PWM device. The
|
// sample rate to get the first parameter for the PWM device. The
|
// second parameter is zero or one, indicating whether or not the
|
// second parameter is zero or one, indicating whether or not the
|
// audio rate can be adjusted (1), or whether it is fixed within the
|
// audio rate can be adjusted (1), or whether it is fixed within the
|
// build (0).
|
// build (0).
|
`ifdef XULA25
|
`ifdef XULA25
|
// `define FMHACK
|
// `define FMHACK
|
|
|
`ifdef FMHACK
|
`ifdef FMHACK
|
wbfmtxhack #(16'd1813) // 44.1 kHz, user adjustable
|
wbfmtxhack #(16'd1813) // 44.1 kHz, user adjustable
|
`else
|
`else
|
wbpwmaudio #(16'd1813,1,16) // 44.1 kHz, user adjustable
|
wbpwmaudio #(16'd1813,1,16) // 44.1 kHz, user adjustable
|
`endif
|
`endif
|
|
|
`else
|
`else
|
wbpwmaudio #(16'h270f,0,16) // 8 kHz, fixed audio rate
|
wbpwmaudio #(16'h270f,0,16) // 8 kHz, fixed audio rate
|
`endif
|
`endif
|
pwmdev(i_clk,
|
pwmdev(i_clk,
|
wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
|
wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
|
wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
|
wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
|
|
|
`ifdef FMHACK
|
`ifdef FMHACK
|
assign o_gpio = {(NGPO){o_pwm}};
|
assign o_gpio = {(NGPO){o_pwm}};
|
`else
|
`else
|
assign o_gpio = w_gpio;
|
assign o_gpio = w_gpio;
|
`endif
|
`endif
|
|
|
|
|
|
|
//
|
//
|
// FLASH MEMORY CONFIGURATION ACCESS
|
// FLASH MEMORY CONFIGURATION ACCESS
|
//
|
//
|
wire flash_cs_n, flash_sck, flash_mosi;
|
wire flash_cs_n, flash_sck, flash_mosi;
|
wire spi_user, sdcard_grant, flash_grant;
|
wire spi_user, sdcard_grant, flash_grant;
|
`ifdef FLASH_ACCESS
|
`ifdef FLASH_ACCESS
|
wbspiflash flashmem(i_clk,
|
wbspiflash flashmem(i_clk,
|
wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_addr[17:0], wb_data,
|
wb_addr[17:0], wb_data,
|
flash_ack, flash_stall, flash_data,
|
flash_ack, flash_stall, flash_data,
|
flash_sck, flash_cs_n, o_sf_cs_n, flash_mosi, i_spi_miso,
|
flash_sck, flash_cs_n, o_sf_cs_n, flash_mosi, i_spi_miso,
|
flash_interrupt, flash_grant);
|
flash_interrupt, flash_grant);
|
`else
|
`else
|
reg r_flash_ack;
|
reg r_flash_ack;
|
initial r_flash_ack = 1'b0;
|
initial r_flash_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
|
r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
|
|
|
assign flash_ack = r_flash_ack;
|
assign flash_ack = r_flash_ack;
|
assign flash_stall = 1'b0;
|
assign flash_stall = 1'b0;
|
assign flash_data = 32'h0000;
|
assign flash_data = 32'h0000;
|
assign flash_interrupt = 1'b0;
|
assign flash_interrupt = 1'b0;
|
|
|
assign flash_cs_n = 1'b1;
|
assign flash_cs_n = 1'b1;
|
assign flash_sck = 1'b1;
|
assign flash_sck = 1'b1;
|
assign flash_mosi = 1'b1;
|
assign flash_mosi = 1'b1;
|
`endif
|
`endif
|
|
|
//
|
//
|
// SDCARD ACCESS
|
// SDCARD ACCESS
|
//
|
//
|
wire sdcard_cs_n, sdcard_sck, sdcard_mosi;
|
wire sdcard_cs_n, sdcard_sck, sdcard_mosi;
|
wire [31:0] sdspi_scope;
|
wire [31:0] sdspi_scope;
|
`ifdef SDCARD_ACCESS
|
`ifdef SDCARD_ACCESS
|
sdspi sdcard_controller(i_clk,
|
sdspi sdcard_controller(i_clk,
|
// Wishbone interface
|
// Wishbone interface
|
wb_cyc, (wb_stb)&&(sdcard_sel), wb_we, wb_addr[1:0], wb_data,
|
wb_cyc, (wb_stb)&&(sdcard_sel), wb_we, wb_addr[1:0], wb_data,
|
// return
|
// return
|
sdcard_ack, sdcard_stall, sdcard_data,
|
sdcard_ack, sdcard_stall, sdcard_data,
|
// SPI interface
|
// SPI interface
|
sdcard_cs_n, sdcard_sck, sdcard_mosi, i_spi_miso,
|
sdcard_cs_n, sdcard_sck, sdcard_mosi, i_spi_miso,
|
sdcard_interrupt, sdcard_grant, sdspi_scope);
|
sdcard_interrupt, sdcard_grant, sdspi_scope);
|
`else
|
`else
|
reg r_sdcard_ack;
|
reg r_sdcard_ack;
|
initial r_sdcard_ack = 1'b0;
|
initial r_sdcard_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_sdcard_ack <= (wb_stb)&&(sdcard_sel);
|
r_sdcard_ack <= (wb_stb)&&(sdcard_sel);
|
assign sdcard_stall = 1'b0;
|
assign sdcard_stall = 1'b0;
|
assign sdcard_ack = r_sdcard_ack;
|
assign sdcard_ack = r_sdcard_ack;
|
assign sdcard_data = 32'h0000;
|
assign sdcard_data = 32'h0000;
|
assign sdcard_interrupt= 1'b0;
|
assign sdcard_interrupt= 1'b0;
|
`endif // SDCARD_ACCESS
|
`endif // SDCARD_ACCESS
|
|
|
|
|
`ifdef FLASH_ACCESS
|
`ifdef FLASH_ACCESS
|
`ifdef SDCARD_ACCESS
|
`ifdef SDCARD_ACCESS
|
spiarbiter spichk(i_clk,
|
spiarbiter spichk(i_clk,
|
// Channel zero
|
// Channel zero
|
flash_cs_n, flash_sck, flash_mosi,
|
flash_cs_n, flash_sck, flash_mosi,
|
// Channel one
|
// Channel one
|
sdcard_cs_n, sdcard_sck, sdcard_mosi,
|
sdcard_cs_n, sdcard_sck, sdcard_mosi,
|
o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi,
|
o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi,
|
spi_user);
|
spi_user);
|
assign sdcard_grant = spi_user;
|
assign sdcard_grant = spi_user;
|
assign flash_grant = ~spi_user;
|
assign flash_grant = ~spi_user;
|
`else
|
`else
|
// Flash access, but no SD card access
|
// Flash access, but no SD card access
|
assign o_sf_cs_n = flash_cs_n;
|
assign o_sf_cs_n = flash_cs_n;
|
assign o_sd_cs_n = 1'b1;
|
assign o_sd_cs_n = 1'b1;
|
assign o_spi_sck = flash_sck;
|
assign o_spi_sck = flash_sck;
|
assign o_spi_mosi = flash_mosi;
|
assign o_spi_mosi = flash_mosi;
|
assign spi_user = 1'b0;
|
assign spi_user = 1'b0;
|
assign flash_grant = 1'b1;
|
assign flash_grant = 1'b1;
|
assign sdcard_grant= 1'b0;
|
assign sdcard_grant= 1'b0;
|
`endif // SDCARD_ACCESS && FLASH_ACCESS
|
`endif // SDCARD_ACCESS && FLASH_ACCESS
|
`else // FLASH_ACCESS
|
`else // FLASH_ACCESS
|
`ifdef SDCARD_ACCESS
|
`ifdef SDCARD_ACCESS
|
// SDCard access, but no flash access
|
// SDCard access, but no flash access
|
assign o_sf_cs_n = 1'b1;
|
assign o_sf_cs_n = 1'b1;
|
assign o_sd_cs_n = sdcard_cs_n;
|
assign o_sd_cs_n = sdcard_cs_n;
|
assign o_spi_sck = sdcard_sck;
|
assign o_spi_sck = sdcard_sck;
|
assign o_spi_mosi = sdcard_mosi;
|
assign o_spi_mosi = sdcard_mosi;
|
assign spi_user = 1'b1;
|
assign spi_user = 1'b1;
|
assign flash_grant = 1'b0;
|
assign flash_grant = 1'b0;
|
assign sdcard_grant= 1'b1;
|
assign sdcard_grant= 1'b1;
|
`else
|
`else
|
// No SPI access ...
|
// No SPI access ...
|
assign o_sf_cs_n = 1'b1;
|
assign o_sf_cs_n = 1'b1;
|
assign o_sd_cs_n = 1'b1;
|
assign o_sd_cs_n = 1'b1;
|
assign o_spi_sck = 1'b1;
|
assign o_spi_sck = 1'b1;
|
assign o_spi_mosi = 1'b1;
|
assign o_spi_mosi = 1'b1;
|
assign spi_user = 1'b0;
|
assign spi_user = 1'b0;
|
assign flash_grant = 1'b0;
|
assign flash_grant = 1'b0;
|
assign sdcard_grant= 1'b0;
|
assign sdcard_grant= 1'b0;
|
`endif // SDCARD_ACCESS, w/o FLASH_ACCESS
|
`endif // SDCARD_ACCESS, w/o FLASH_ACCESS
|
`endif // !FLASH_ACCESS
|
`endif // !FLASH_ACCESS
|
|
|
|
|
//
|
//
|
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
|
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
|
//
|
//
|
wire [31:0] cfg_scope;
|
wire [31:0] cfg_scope;
|
`ifdef FANCY_ICAP_ACCESS
|
`ifdef FANCY_ICAP_ACCESS
|
wbicape6 fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
|
wbicape6 fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
|
wb_addr[5:0], wb_data,
|
wb_addr[5:0], wb_data,
|
cfg_ack, cfg_stall, cfg_data,
|
cfg_ack, cfg_stall, cfg_data,
|
cfg_scope);
|
cfg_scope);
|
`else
|
`else
|
assign cfg_scope = 32'h0000;
|
assign cfg_scope = 32'h0000;
|
reg r_cfg_ack;
|
reg r_cfg_ack;
|
initial r_cfg_ack = 1'b0;
|
initial r_cfg_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_cfg_ack <= ((cfg_sel)&&(wb_stb)&&(~cfg_stall));
|
r_cfg_ack <= ((cfg_sel)&&(wb_stb)&&(~cfg_stall));
|
assign cfg_ack = r_cfg_ack;
|
assign cfg_ack = r_cfg_ack;
|
assign cfg_stall = 1'b0;
|
assign cfg_stall = 1'b0;
|
assign cfg_data = 32'h0000;
|
assign cfg_data = 32'h0000;
|
`endif
|
`endif
|
|
|
|
|
//
|
//
|
// RAM MEMORY ACCESS
|
// RAM MEMORY ACCESS
|
//
|
//
|
`ifdef IMPLEMENT_ONCHIP_RAM
|
`ifdef IMPLEMENT_ONCHIP_RAM
|
memdev #(13) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
|
memdev #(13) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
|
wb_addr[12:0], wb_data, mem_ack, mem_stall, mem_data);
|
wb_addr[12:0], wb_data, mem_ack, mem_stall, mem_data);
|
`else
|
`else
|
reg r_mem_ack;
|
reg r_mem_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_mem_ack = (wb_stb)&&(mem_sel);
|
r_mem_ack = (wb_stb)&&(mem_sel);
|
assign mem_data = 32'h000;
|
assign mem_data = 32'h000;
|
assign mem_stall = 1'b0;
|
assign mem_stall = 1'b0;
|
assign mem_ack = r_mem_ack;
|
assign mem_ack = r_mem_ack;
|
`endif
|
`endif
|
|
|
|
|
//
|
//
|
// SDRAM Memory Access
|
// SDRAM Memory Access
|
//
|
//
|
wire [31:0] sdram_debug;
|
wire [31:0] sdram_debug;
|
`ifndef BYPASS_SDRAM_ACCESS
|
`ifndef BYPASS_SDRAM_ACCESS
|
wbsdram sdram(i_clk,
|
wbsdram sdram(i_clk,
|
wb_cyc, (wb_stb)&&(sdram_sel),
|
wb_cyc, (wb_stb)&&(sdram_sel),
|
wb_we, wb_addr[22:0], wb_data,
|
wb_we, wb_addr[22:0], wb_data,
|
sdram_ack, sdram_stall, sdram_data,
|
sdram_ack, sdram_stall, sdram_data,
|
o_ram_cs_n, o_ram_cke, o_ram_ras_n, o_ram_cas_n, o_ram_we_n,
|
o_ram_cs_n, o_ram_cke, o_ram_ras_n, o_ram_cas_n, o_ram_we_n,
|
o_ram_bs, o_ram_addr,
|
o_ram_bs, o_ram_addr,
|
o_ram_drive_data, i_ram_data, o_ram_data, o_ram_dqm,
|
o_ram_drive_data, i_ram_data, o_ram_data, o_ram_dqm,
|
sdram_debug);
|
sdram_debug);
|
`else
|
`else
|
reg r_sdram_ack;
|
reg r_sdram_ack;
|
initial r_sdram_ack = 1'b0;
|
initial r_sdram_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_sdram_ack <= (wb_stb)&&(sdram_sel);
|
r_sdram_ack <= (wb_stb)&&(sdram_sel);
|
assign sdram_ack = r_sdram_ack;
|
assign sdram_ack = r_sdram_ack;
|
assign sdram_stall = 1'b0;
|
assign sdram_stall = 1'b0;
|
assign sdram_data = 32'h0000;
|
assign sdram_data = 32'h0000;
|
|
|
assign o_ram_ce_n = 1'b1;
|
assign o_ram_ce_n = 1'b1;
|
assign o_ram_ras_n = 1'b1;
|
assign o_ram_ras_n = 1'b1;
|
assign o_ram_cas_n = 1'b1;
|
assign o_ram_cas_n = 1'b1;
|
assign o_ram_we_n = 1'b1;
|
assign o_ram_we_n = 1'b1;
|
|
|
assign sdram_debug = 32'h0000;
|
assign sdram_debug = 32'h0000;
|
`endif
|
`endif
|
|
|
//
|
//
|
//
|
//
|
// WISHBONE SCOPES
|
// WISHBONE SCOPES
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
wire [31:0] scop_flash_data;
|
wire [31:0] scop_flash_data;
|
wire scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
|
wire scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
|
|
|
`ifndef FLASH_ACCESS
|
`ifndef FLASH_ACCESS
|
`ifdef FLASH_SCOPE
|
`ifdef FLASH_SCOPE
|
`undef FLASH_SCOPE // FLASH_SCOPE only makes sense if you have flash access
|
`undef FLASH_SCOPE // FLASH_SCOPE only makes sense if you have flash access
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef FLASH_SCOPE
|
`ifdef FLASH_SCOPE
|
reg [31:0] r_flash_debug, last_flash_debug;
|
reg [31:0] r_flash_debug, last_flash_debug;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_flash_debug <= flash_debug;
|
r_flash_debug <= flash_debug;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
last_flash_debug <= r_flash_debug;
|
last_flash_debug <= r_flash_debug;
|
wbscope spiscope(i_clk, 1'b1, (~o_spi_cs_n), r_flash_debug,
|
wbscope spiscope(i_clk, 1'b1, (~o_spi_cs_n), r_flash_debug,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
|
wb_data,
|
wb_data,
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
scop_flash_interrupt);
|
scop_flash_interrupt);
|
`else
|
`else
|
`ifdef WBUS_SCOPE
|
`ifdef WBUS_SCOPE
|
wbscopc #(5'ha) wbuscope(i_clk, 1'b1, wbus_debug[31], wbus_debug[30:0],
|
wbscopc #(5'ha) wbuscope(i_clk, 1'b1, wbus_debug[31], wbus_debug[30:0],
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
|
wb_data,
|
wb_data,
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
scop_flash_interrupt);
|
scop_flash_interrupt);
|
`else
|
`else
|
assign scop_flash_data = 32'h00;
|
assign scop_flash_data = 32'h00;
|
assign scop_flash_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00);
|
assign scop_flash_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00);
|
assign scop_flash_stall = 1'b0;
|
assign scop_flash_stall = 1'b0;
|
assign scop_flash_interrupt = 1'b0;
|
assign scop_flash_interrupt = 1'b0;
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
|
|
wire [31:0] scop_cfg_data;
|
wire [31:0] scop_cfg_data;
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
`ifdef CFG_SCOPE
|
`ifdef CFG_SCOPE
|
wire scop_cfg_trigger;
|
wire scop_cfg_trigger;
|
assign scop_cfg_trigger = (wb_stb)&&(cfg_sel);
|
assign scop_cfg_trigger = (wb_stb)&&(cfg_sel);
|
wbscope #(5'h7) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
|
wbscope #(5'h7) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
wb_we, wb_addr[0], wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
|
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
|
scop_cfg_interrupt);
|
scop_cfg_interrupt);
|
`else
|
`else
|
`ifdef SDCARD_SCOPE
|
`ifdef SDCARD_SCOPE
|
wire scop_sd_trigger, scop_sd_ce;
|
wire scop_sd_trigger, scop_sd_ce;
|
assign scop_sd_trigger = (wb_stb)&&(sdcard_sel)&&(wb_we);
|
assign scop_sd_trigger = (wb_stb)&&(sdcard_sel)&&(wb_we);
|
assign scop_sd_ce = 1'b1; // sdspi_scope[31];
|
assign scop_sd_ce = 1'b1; // sdspi_scope[31];
|
wbscope #(5'h9) sdspiscope(i_clk, scop_sd_ce,
|
wbscope #(5'h9) sdspiscope(i_clk, scop_sd_ce,
|
scop_sd_trigger, sdspi_scope,
|
scop_sd_trigger, sdspi_scope,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
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wb_we, wb_addr[0], wb_data,
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wb_we, wb_addr[0], wb_data,
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,scop_cfg_interrupt);
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,scop_cfg_interrupt);
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`else
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`else
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assign scop_cfg_data = 32'h00;
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assign scop_cfg_data = 32'h00;
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assign scop_cfg_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01);
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assign scop_cfg_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01);
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assign scop_cfg_stall = 1'b0;
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assign scop_cfg_stall = 1'b0;
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assign scop_cfg_interrupt = 1'b0;
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assign scop_cfg_interrupt = 1'b0;
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`endif
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`endif
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`endif
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`endif
|
|
|
wire [31:0] scop_two_data;
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wire [31:0] scop_two_data;
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wire scop_two_ack, scop_two_stall, scop_two_interrupt;
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wire scop_two_ack, scop_two_stall, scop_two_interrupt;
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`ifdef SDRAM_SCOPE
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`ifdef SDRAM_SCOPE
|
wire sdram_trigger;
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wire sdram_trigger;
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assign sdram_trigger = sdram_debug[18]; // sdram_sel;
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assign sdram_trigger = sdram_debug[18]; // sdram_sel;
|
|
|
wbscope #(5'hb) sdramscope(i_clk, 1'b1, sdram_trigger,
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wbscope #(5'hb) sdramscope(i_clk, 1'b1, sdram_trigger,
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sdram_debug,
|
sdram_debug,
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//{ sdram_trigger, wb_data[30:0] },
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//{ sdram_trigger, wb_data[30:0] },
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
|
wb_data,
|
wb_data,
|
scop_two_ack, scop_two_stall, scop_two_data,
|
scop_two_ack, scop_two_stall, scop_two_data,
|
scop_two_interrupt);
|
scop_two_interrupt);
|
`else
|
`else
|
`ifdef UART_SCOPE
|
`ifdef UART_SCOPE
|
wire uart_trigger;
|
wire uart_trigger;
|
assign uart_trigger = uart_debug[31];
|
assign uart_trigger = uart_debug[31];
|
|
|
// wbscopc #(5'ha) uartscope(i_clk,1'b1, uart_trigger, uart_debug[30:0],
|
// wbscopc #(5'ha) uartscope(i_clk,1'b1, uart_trigger, uart_debug[30:0],
|
wbscope #(5'ha) uartscope(i_clk, 1'b1, uart_trigger, uart_debug[31:0],
|
wbscope #(5'ha) uartscope(i_clk, 1'b1, uart_trigger, uart_debug[31:0],
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
|
wb_data,
|
wb_data,
|
scop_two_ack, scop_two_stall, scop_two_data,
|
scop_two_ack, scop_two_stall, scop_two_data,
|
scop_two_interrupt);
|
scop_two_interrupt);
|
`else
|
`else
|
assign scop_two_data = 32'h00;
|
assign scop_two_data = 32'h00;
|
assign scop_two_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10);
|
assign scop_two_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10);
|
assign scop_two_stall = 1'b0;
|
assign scop_two_stall = 1'b0;
|
assign scop_two_interrupt = 1'b0;
|
assign scop_two_interrupt = 1'b0;
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
wire [31:0] scop_zip_data;
|
wire [31:0] scop_zip_data;
|
wire scop_zip_ack, scop_zip_stall, scop_zip_interrupt;
|
wire scop_zip_ack, scop_zip_stall, scop_zip_interrupt;
|
`ifdef ZIP_SCOPE
|
`ifdef ZIP_SCOPE
|
reg zip_trigger, pre_trigger_a, pre_trigger_b;
|
reg zip_trigger, pre_trigger_a, pre_trigger_b;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
pre_trigger_a <= (wb_stb)&&(wb_addr[31:0]==32'h010b);
|
pre_trigger_a <= (wb_stb)&&(wb_addr[31:0]==32'h010b);
|
pre_trigger_b <= (|wb_data[31:8]);
|
pre_trigger_b <= (|wb_data[31:8]);
|
zip_trigger= (pre_trigger_a)&&(pre_trigger_b)||(zip_debug[31]);
|
zip_trigger= (pre_trigger_a)&&(pre_trigger_b)||(zip_debug[31]);
|
end
|
end
|
wbscope #(5'h9) zipscope(i_clk, 1'b1, zip_trigger,
|
wbscope #(5'h9) zipscope(i_clk, 1'b1, zip_trigger,
|
zip_debug,
|
zip_debug,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)), wb_we, wb_addr[0],
|
wb_data,
|
wb_data,
|
scop_zip_ack, scop_zip_stall, scop_zip_data,
|
scop_zip_ack, scop_zip_stall, scop_zip_data,
|
scop_zip_interrupt);
|
scop_zip_interrupt);
|
`else
|
`else
|
assign scop_zip_data = 32'h00;
|
assign scop_zip_data = 32'h00;
|
assign scop_zip_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11);
|
assign scop_zip_ack = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11);
|
assign scop_zip_stall = 1'b0;
|
assign scop_zip_stall = 1'b0;
|
assign scop_zip_interrupt = 1'b0;
|
assign scop_zip_interrupt = 1'b0;
|
`endif
|
`endif
|
|
|
|
|
assign scop_interrupt = scop_flash_interrupt || scop_cfg_interrupt
|
assign scop_interrupt = scop_flash_interrupt || scop_cfg_interrupt
|
|| scop_two_interrupt || scop_zip_interrupt;
|
|| scop_two_interrupt || scop_zip_interrupt;
|
assign scop_ack = scop_cfg_ack | scop_flash_ack | scop_two_ack | scop_zip_ack;
|
assign scop_ack = scop_cfg_ack | scop_flash_ack | scop_two_ack | scop_zip_ack;
|
assign scop_stall = ((~wb_addr[2])?
|
assign scop_stall = ((~wb_addr[2])?
|
((wb_addr[1])?scop_flash_stall:scop_cfg_stall)
|
((wb_addr[1])?scop_flash_stall:scop_cfg_stall)
|
: ((wb_addr[1])?scop_two_stall:scop_zip_stall));
|
: ((wb_addr[1])?scop_two_stall:scop_zip_stall));
|
assign scop_data = ((scop_cfg_ack)?scop_cfg_data
|
assign scop_data = ((scop_cfg_ack)?scop_cfg_data
|
: ((scop_flash_ack) ? scop_flash_data
|
: ((scop_flash_ack) ? scop_flash_data
|
: ((scop_two_ack) ? scop_two_data
|
: ((scop_two_ack) ? scop_two_data
|
: scop_zip_data)));
|
: scop_zip_data)));
|
|
|
|
|
endmodule
|
endmodule
|
|
|
// 0x8684 interrupts ...???
|
// 0x8684 interrupts ...???
|
|
|
