////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Filename: uartdev.v
|
// Filename: uartdev.v
|
//
|
//
|
// Project: XuLA2 board
|
// Project: XuLA2 board
|
//
|
//
|
// Purpose: This is a simple wrapper around the txuart and rxuart
|
// Purpose: This is a simple wrapper around the txuart and rxuart
|
// modules. The purpose is to make both of those modules
|
// modules. The purpose is to make both of those modules
|
// configurable from a single wishbone address, and capable of receiving
|
// configurable from a single wishbone address, and capable of receiving
|
// (or transmitting) via reads (writes) from two other addresses.
|
// (or transmitting) via reads (writes) from two other addresses.
|
//
|
//
|
// It also generates interrupts: a receive interrupt strobe on the clock
|
// It also generates interrupts: a receive interrupt strobe on the clock
|
// when data is made available, and a transmit not busy level interrupt
|
// when data is made available, and a transmit not busy level interrupt
|
// which is held high as long as the transmitter is idle. Both should be
|
// which is held high as long as the transmitter is idle. Both should be
|
// able to work nicely with the programmable interrupt controllers found
|
// able to work nicely with the programmable interrupt controllers found
|
// in the ZipCPU project.
|
// in the ZipCPU project.
|
//
|
//
|
//
|
//
|
// Creator: Dan Gisselquist, Ph.D.
|
// Creator: Dan Gisselquist, Ph.D.
|
// Gisselquist Technology, LLC
|
// Gisselquist Technology, LLC
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Copyright (C) 2015, Gisselquist Technology, LLC
|
// Copyright (C) 2015, Gisselquist Technology, LLC
|
//
|
//
|
// This program is free software (firmware): you can redistribute it and/or
|
// This program is free software (firmware): you can redistribute it and/or
|
// modify it under the terms of the GNU General Public License as published
|
// modify it under the terms of the GNU General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// your option) any later version.
|
// your option) any later version.
|
//
|
//
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// for more details.
|
// for more details.
|
//
|
//
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// http://www.gnu.org/licenses/gpl.html
|
// http://www.gnu.org/licenses/gpl.html
|
//
|
//
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
//
|
//
|
module uartdev(i_clk, i_rx_uart, o_tx_uart,
|
module uartdev(i_clk, i_rx_uart, o_tx_uart,
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_rx_int, o_tx_int);
|
o_rx_int, o_tx_int);
|
parameter DEFAULT_SETUP = { 2'b00, 1'b0, 1'b0, 2'b00, 24'd10417 };
|
parameter DEFAULT_SETUP = { 2'b00, 1'b0, 1'b0, 2'b00, 24'd10417 };
|
input i_clk, i_rx_uart;
|
input i_clk, i_rx_uart;
|
output wire o_tx_uart;
|
output wire o_tx_uart;
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
input [1:0] i_wb_addr;
|
input [1:0] i_wb_addr;
|
input [31:0] i_wb_data;
|
input [31:0] i_wb_data;
|
output reg o_wb_ack;
|
output reg o_wb_ack;
|
output wire o_wb_stall;
|
output wire o_wb_stall;
|
output reg [31:0] o_wb_data;
|
output reg [31:0] o_wb_data;
|
output wire o_rx_int, o_tx_int;
|
output wire o_rx_int, o_tx_int;
|
|
|
reg [29:0] r_setup;
|
reg [29:0] r_setup;
|
reg r_tx_stb, rx_rdy;
|
reg r_tx_stb, rx_rdy;
|
reg [7:0] r_tx_data;
|
reg [7:0] r_tx_data;
|
initial r_setup = DEFAULT_SETUP;
|
initial r_setup = DEFAULT_SETUP;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
|
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(~i_wb_addr[1]))
|
|
r_setup <= i_wb_data[29:0];
|
|
|
|
initial r_tx_stb = 1'b0;
|
|
always @(posedge i_clk)
|
|
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(i_wb_addr == 2'b10))
|
begin
|
begin
|
case(i_wb_addr)
|
// Note: there's no check for overflow here.
|
2'b00: r_setup <= i_wb_data[29:0];
|
// You're on your own: verify that the device
|
2'b10: begin
|
// isn't busy first.
|
r_tx_data <= i_wb_data[7:0];
|
r_tx_data <= i_wb_data[7:0];
|
r_tx_stb <= 1'b1;
|
r_tx_stb <= 1'b1;
|
end
|
|
default: begin end
|
|
endcase
|
|
end else
|
end else
|
r_tx_stb <= 1'b0;
|
r_tx_stb <= 1'b0;
|
|
|
wire rx_stb, rx_break, rx_parity_err, rx_frame_err, rx_ignored;
|
wire rx_stb, rx_break, rx_parity_err, rx_frame_err;
|
wire [7:0] rx_data;
|
wire [7:0] rx_data;
|
rxuart rxmod(i_clk, 1'b0, r_setup, i_rx_uart,
|
rxuart rxmod(i_clk, 1'b0, r_setup, i_rx_uart,
|
rx_stb, rx_data, rx_break,
|
rx_stb, rx_data, rx_break,
|
rx_parity_err, rx_frame_err, rx_ignored);
|
rx_parity_err, rx_frame_err);
|
|
|
wire tx_break, tx_busy;
|
wire tx_break, tx_busy;
|
assign tx_break = 1'b0;
|
assign tx_break = 1'b0;
|
txuart txmod(i_clk, 1'b0, r_setup, tx_break, r_tx_stb, r_tx_data,
|
txuart txmod(i_clk, 1'b0, r_setup, tx_break, r_tx_stb, r_tx_data,
|
o_tx_uart, tx_busy);
|
o_tx_uart, tx_busy);
|
|
|
reg [7:0] r_data;
|
reg [7:0] r_data;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (rx_stb)
|
if (rx_stb)
|
r_data <= rx_data;
|
r_data <= rx_data;
|
|
|
|
initial o_wb_data = 32'h00;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if (rx_stb)
|
if (rx_stb)
|
rx_rdy <= (rx_rdy | rx_stb);
|
rx_rdy <= (rx_rdy | rx_stb);
|
|
|
case(i_wb_addr)
|
case(i_wb_addr)
|
2'b00: o_wb_data <= { 2'b00, r_setup };
|
2'b00: o_wb_data <= { 2'b00, r_setup };
|
2'b01: o_wb_data <= { 2'b00, r_setup };
|
2'b01: o_wb_data <= { 2'b00, r_setup };
|
2'b10: o_wb_data <= { 31'h00,tx_busy };
|
2'b10: o_wb_data <= { 31'h00,tx_busy };
|
2'b11: begin
|
2'b11: begin
|
if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we))
|
if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we))
|
rx_rdy <= 1'b0;
|
rx_rdy <= rx_stb;
|
o_wb_data <= { 20'h00, rx_break, rx_frame_err, rx_parity_err, ~rx_rdy, r_data };
|
o_wb_data <= { 20'h00, rx_break, rx_frame_err, rx_parity_err, ~rx_rdy, r_data };
|
end
|
end
|
endcase
|
endcase
|
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
|
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); // Read or write, we ack
|
end
|
end
|
|
|
assign o_wb_stall = 1'b0;
|
assign o_wb_stall = 1'b0;
|
assign o_rx_int = rx_stb;
|
assign o_rx_int = rx_stb;
|
assign o_tx_int = ~tx_busy;
|
assign o_tx_int = ~tx_busy;
|
|
|
endmodule
|
endmodule
|
|
|
