////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbgpio.v
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// Filename: wbgpio.v
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//
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//
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// Project: XuLA2 board
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// Project: XuLA2 board
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//
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//
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// Purpose:
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// Purpose: This extremely simple GPIO controller, although minimally
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// featured, is designed to control up to sixteen general purpose
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// input and sixteen general purpose output lines of a module from a
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// single address on a 32-bit wishbone bus.
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//
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// Input GPIO values are contained in the top 16-bits. Any change in
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// input values will generate an interrupt.
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//
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// Output GPIO values are contained in the bottom 16-bits. To change an
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// output GPIO value, writes to this port must also set a bit in the
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// upper sixteen bits. Hence, to set GPIO output zero, one would write
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// a 0x010001 to the port, whereas a 0x010000 would clear the bit. This
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// interface makes it possible to change only the bit of interest, without
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// needing to capture and maintain the prior bit values--something that
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// might be difficult from a interrupt context within a CPU.
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//
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module wbgpio(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, o_wb_data,
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module wbgpio(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, o_wb_data,
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i_gpio, o_gpio, o_int);
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i_gpio, o_gpio, o_int);
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parameter NIN=16, NOUT=16, DEFAULT=16'h00;
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parameter NIN=16, NOUT=16, DEFAULT=16'h00;
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input i_clk;
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input i_clk;
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//
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//
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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//
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//
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input [(NIN-1):0] i_gpio;
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input [(NIN-1):0] i_gpio;
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output reg [(NOUT-1):0] o_gpio;
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output reg [(NOUT-1):0] o_gpio;
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//
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//
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output reg o_int;
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output reg o_int;
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// 9LUT's, 16 FF's
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// 9LUT's, 16 FF's
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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o_gpio <= ((o_gpio)&(~i_wb_data[(NOUT+16-1):16]))
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o_gpio <= ((o_gpio)&(~i_wb_data[(NOUT+16-1):16]))
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|((i_wb_data[(NOUT-1):0])&(i_wb_data[(NOUT+16-1):16]));
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|((i_wb_data[(NOUT-1):0])&(i_wb_data[(NOUT+16-1):16]));
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reg [(NIN-1):0] x_gpio, r_gpio;
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reg [(NIN-1):0] x_gpio, r_gpio;
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// 3 LUTs, 33 FF's
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// 3 LUTs, 33 FF's
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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x_gpio <= i_gpio;
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x_gpio <= i_gpio;
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r_gpio <= x_gpio;
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r_gpio <= x_gpio;
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o_int <= (x_gpio != r_gpio);
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o_int <= (x_gpio != r_gpio);
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end
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end
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assign o_wb_data = { {(16-NIN){1'b0}}, r_gpio,
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assign o_wb_data = { {(16-NIN){1'b0}}, r_gpio,
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{(16-NOUT){1'b0}}, o_gpio };
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{(16-NOUT){1'b0}}, o_gpio };
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endmodule
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endmodule
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