///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbpwmaudio.v
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// Filename: wbpwmaudio.v
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//
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//
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// Project: A Wishbone Controlled PWM (audio) controller
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// Project: A Wishbone Controlled PWM (audio) controller
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//
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//
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// Purpose: This PWM controller was designed with audio in mind, although
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// Purpose: This PWM controller was designed with audio in mind, although
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// it should be sufficient for many other purposes. Specifically,
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// it should be sufficient for many other purposes. Specifically,
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// it creates a pulse-width modulated output, where the amount of time
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// it creates a pulse-width modulated output, where the amount of time
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// the output is 'high' is determined by the pulse width data given to
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// the output is 'high' is determined by the pulse width data given to
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// it. Further, the 'high' time is spread out in bit reversed order.
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// it. Further, the 'high' time is spread out in bit reversed order.
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// In this fashion, a halfway point will alternate between high and low,
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// In this fashion, a halfway point will alternate between high and low,
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// rather than the normal fashion of being high for half the time and then
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// rather than the normal fashion of being high for half the time and then
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// low. This approach was chosen to move the PWM artifacts to higher,
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// low. This approach was chosen to move the PWM artifacts to higher,
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// inaudible frequencies and hence improve the sound quality.
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// inaudible frequencies and hence improve the sound quality.
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//
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//
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// The interface supports two addresses:
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// The interface supports two addresses:
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//
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//
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// Addr[0] is the data register. Writes to this register will set
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// Addr[0] is the data register. Writes to this register will set
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// a 16-bit sample value to be produced by the PWM logic.
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// a 16-bit sample value to be produced by the PWM logic.
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// Reads will also produce, in the 17th bit, whether the interrupt
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// Reads will also produce, in the 17th bit, whether the interrupt
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// is set or not. (If set, it's time to write a new data value
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// is set or not. (If set, it's time to write a new data value
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// ...)
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// ...)
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//
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//
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// Addr[1] is a timer reload value, used to determine how often the
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// Addr[1] is a timer reload value, used to determine how often the
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// PWM logic needs its next value. This number should be set
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// PWM logic needs its next value. This number should be set
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// to the number of clock cycles between reload values. So,
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// to the number of clock cycles between reload values. So,
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// for example, an 80 MHz clock can generate a 44.1 kHz audio
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// for example, an 80 MHz clock can generate a 44.1 kHz audio
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// stream by reading in a new sample every (80e6/44.1e3 = 1814)
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// stream by reading in a new sample every (80e6/44.1e3 = 1814)
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// samples. After loading a sample, the device is immediately
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// samples. After loading a sample, the device is immediately
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// ready to load a second. Once the first sample completes,
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// ready to load a second. Once the first sample completes,
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// the second sample will start going to the output, and an
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// the second sample will start going to the output, and an
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// interrupt will be generated indicating that the device is
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// interrupt will be generated indicating that the device is
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// now ready for the third sample. (The one sample buffer
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// now ready for the third sample. (The one sample buffer
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// allows some flexibility in getting the new sample there fast
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// allows some flexibility in getting the new sample there fast
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// enough ...)
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// enough ...)
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//
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//
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//
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//
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// If you read through the code below, you'll notice that you can also
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// If you read through the code below, you'll notice that you can also
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// set the timer reload value to an immutable constant by changing the
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// set the timer reload value to an immutable constant by changing the
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// VARIABLE_RATE parameter to 0. When VARIABLE_RATE is set to zero,
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// VARIABLE_RATE parameter to 0. When VARIABLE_RATE is set to zero,
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// both addresses become the same, Addr[0] or the data register, and the
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// both addresses become the same, Addr[0] or the data register, and the
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// reload value can no longer be changed--forcing the sample rate to
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// reload value can no longer be changed--forcing the sample rate to
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// stay constant.
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// stay constant.
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//
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//
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//
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//
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// Of course, if you don't want to deal with the interrupts or sample
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// Of course, if you don't want to deal with the interrupts or sample
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// rates, you can still get a pseudo analog output by just setting the
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// rates, you can still get a pseudo analog output by just setting the
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// value to the analog output you would like and then not updating
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// value to the analog output you would like and then not updating
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// it. In this case, you could also shut the interrupt down at the
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// it. In this case, you could also shut the interrupt down at the
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// controller, to keep that from bothering you as well.
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// controller, to keep that from bothering you as well.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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module wbpwmaudio(i_clk,
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module wbpwmaudio(i_clk,
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// Wishbone interface
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// Wishbone interface
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_pwm, o_int);
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o_pwm, o_int);
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parameter DEFAULT_RELOAD = 17'd1814, // about 44.1 kHz @ 80MHz
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parameter DEFAULT_RELOAD = 17'd1814, // about 44.1 kHz @ 80MHz
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//DEFAULT_RELOAD = 17'd2268,//about 44.1 kHz @ 100MHz
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//DEFAULT_RELOAD = 17'd2268,//about 44.1 kHz @ 100MHz
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VARIABLE_RATE=0,
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VARIABLE_RATE=0,
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TIMING_BITS=17;
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TIMING_BITS=17;
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input i_clk;
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input i_clk;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_addr;
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input i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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output reg o_pwm;
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output reg o_pwm;
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output reg o_int;
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output reg o_int;
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// How often shall we create an interrupt? Every reload_value clocks!
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// How often shall we create an interrupt? Every reload_value clocks!
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// If VARIABLE_RATE==0, this value will never change and will be kept
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// If VARIABLE_RATE==0, this value will never change and will be kept
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// at the default reload rate (defined up top)
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// at the default reload rate (defined up top)
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wire [(TIMING_BITS-1):0] w_reload_value;
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wire [(TIMING_BITS-1):0] w_reload_value;
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generate
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generate
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if (VARIABLE_RATE != 0)
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if (VARIABLE_RATE != 0)
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begin
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begin
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reg [(TIMING_BITS-1):0] r_reload_value;
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reg [(TIMING_BITS-1):0] r_reload_value;
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initial r_reload_value = DEFAULT_RELOAD;
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initial r_reload_value = DEFAULT_RELOAD;
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always @(posedge i_clk) // Data write
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always @(posedge i_clk) // Data write
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
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if ((i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
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r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
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r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
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assign w_reload_value = r_reload_value;
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assign w_reload_value = r_reload_value;
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end else begin
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end else begin
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assign w_reload_value = DEFAULT_RELOAD;
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assign w_reload_value = DEFAULT_RELOAD;
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end endgenerate
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end endgenerate
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reg ztimer;
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reg ztimer;
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reg [(TIMING_BITS-1):0] timer;
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reg [(TIMING_BITS-1):0] timer;
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initial timer = DEFAULT_RELOAD;
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initial timer = DEFAULT_RELOAD;
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initial ztimer= 1'b0;
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initial ztimer= 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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ztimer <= (timer == { {(TIMING_BITS-1){1'b0}}, 1'b1 });
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ztimer <= (timer == { {(TIMING_BITS-1){1'b0}}, 1'b1 });
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (ztimer)
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if (ztimer)
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timer <= w_reload_value;
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timer <= w_reload_value;
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else
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else
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timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
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timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
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reg [15:0] sample_out;
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reg [15:0] sample_out;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (ztimer)
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if (ztimer)
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sample_out <= next_sample;
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sample_out <= next_sample;
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reg [15:0] next_sample;
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reg [15:0] next_sample;
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reg next_valid;
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reg next_valid;
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initial next_valid = 1'b1;
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initial next_valid = 1'b1;
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initial next_sample = 16'h8000;
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initial next_sample = 16'h8000;
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always @(posedge i_clk) // Data write
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always @(posedge i_clk) // Data write
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)
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if ((i_wb_stb)&&(i_wb_we)
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&&((~i_wb_addr)||(VARIABLE_RATE==0)))
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&&((~i_wb_addr)||(VARIABLE_RATE==0)))
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begin
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begin
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// Write with two's complement data, convert it
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// Write with two's complement data, convert it
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// internally to binary offset
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// internally to binary offset
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next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
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next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
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next_valid <= 1'b1;
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next_valid <= 1'b1;
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end else if (ztimer)
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end else if (ztimer)
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next_valid <= 1'b0;
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next_valid <= 1'b0;
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initial o_int = 1'b0;
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initial o_int = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_int <= (~next_valid);
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o_int <= (~next_valid);
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reg [15:0] pwm_counter;
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reg [15:0] pwm_counter;
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initial pwm_counter = 16'h00;
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initial pwm_counter = 16'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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pwm_counter <= pwm_counter + 16'h01;
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pwm_counter <= pwm_counter + 16'h01;
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wire [15:0] br_counter;
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wire [15:0] br_counter;
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genvar k;
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genvar k;
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generate for(k=0; k<16; k=k+1)
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generate for(k=0; k<16; k=k+1)
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begin : bit_reversal_loop
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begin : bit_reversal_loop
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assign br_counter[k] = pwm_counter[15-k];
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assign br_counter[k] = pwm_counter[15-k];
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end endgenerate
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end endgenerate
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_pwm <= (sample_out >= br_counter);
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o_pwm <= (sample_out >= br_counter);
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generate
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generate
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if (VARIABLE_RATE == 0)
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if (VARIABLE_RATE == 0)
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begin
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begin
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assign o_wb_data = { 15'h00, o_int, sample_out };
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assign o_wb_data = { 15'h00, o_int, sample_out };
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end else begin
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end else begin
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reg [31:0] r_wb_data;
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reg [31:0] r_wb_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wb_addr)
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if (i_wb_addr)
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r_wb_data <= w_reload_value;
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r_wb_data <= { {(32-TIMING_BITS){1'b0}}, w_reload_value };
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else
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else
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r_wb_data <= { 15'h00, o_int, sample_out };
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r_wb_data <= { 15'h00, o_int, sample_out };
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assign o_wb_data = r_wb_data;
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assign o_wb_data = r_wb_data;
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end endgenerate
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end endgenerate
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initial o_wb_ack = 1'b0;
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initial o_wb_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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o_wb_ack <= (i_wb_stb);
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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endmodule
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endmodule
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