///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbspiflash.v
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// Filename: wbspiflash.v
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//
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//
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// Project: XuLA2 board
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// Project: XuLA2 board
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//
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//
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// Purpose: Access a SPI flash via a WISHBONE interface. This
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// Purpose: Access a SPI flash via a WISHBONE interface. This
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// includes both read and write (and erase) commands to the SPI
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// includes both read and write (and erase) commands to the SPI
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// flash. All read/write commands are accomplished using the
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// flash. All read/write commands are accomplished using the
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// high speed (4-bit) interface. Further, the device will be
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// high speed (4-bit) interface. Further, the device will be
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// left/kept in the 4-bit read interface mode between accesses,
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// left/kept in the 4-bit read interface mode between accesses,
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// for a minimum read latency.
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// for a minimum read latency.
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//
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//
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// Wishbone Registers (See spec sheet for more detail):
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// Wishbone Registers (See spec sheet for more detail):
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// 0: local config(r) / erase commands(w) / deep power down cmds / etc.
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// 0: local config(r) / erase commands(w) / deep power down cmds / etc.
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// R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
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// R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
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// { last_erased_sector, 14'h00 } if (WIP)
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// { last_erased_sector, 14'h00 } if (WIP)
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// else { current_sector_being_erased, 14'h00 }
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// else { current_sector_being_erased, 14'h00 }
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// current if write in progress, last if written
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// current if write in progress, last if written
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// W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
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// W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
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// 1: Configuration register
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// 1: Configuration register
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// 2: Status register (R/w)
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// 2: Status register (R/w)
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// 3: Read ID (read only)
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// 3: Read ID (read only)
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// (19 bits): Data (R/w, but expect writes to take a while)
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// (19 bits): Data (R/w, but expect writes to take a while)
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//
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//
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//
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//
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// Creator: Dan Gisselquist
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// Creator: Dan Gisselquist
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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`define WBSPI_RESET 6'd0
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`define WBSPI_RESET 6'd0
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// `define WBSPI_RESET_QUADMODE 1
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// `define WBSPI_RESET_QUADMODE 1
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`define WBSPI_IDLE 6'd2
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`define WBSPI_IDLE 6'd2
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// `define WBQSPI_RDIDLE 3 // Idle, but in fast read mode
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// `define WBQSPI_RDIDLE 3 // Idle, but in fast read mode
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// `define WBSPI_WBDECODE 4
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// `define WBSPI_WBDECODE 4
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`define WBSPI_WAIT_WIP_CLEAR 6'd5
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`define WBSPI_WAIT_WIP_CLEAR 6'd5
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`define WBSPI_CHECK_WIP_CLEAR 6'd6
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`define WBSPI_CHECK_WIP_CLEAR 6'd6
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`define WBSPI_CHECK_WIP_DONE 6'd7
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`define WBSPI_CHECK_WIP_DONE 6'd7
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`define WBSPI_WEN 6'd8
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`define WBSPI_WEN 6'd8
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`define WBSPI_PP 6'd9 // Program page
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`define WBSPI_PP 6'd9 // Program page
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// `define WBSPI_QPP 10 // Program page, 4 bit mode
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// `define WBSPI_QPP 10 // Program page, 4 bit mode
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`define WBSPI_WR_DATA 6'd11
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`define WBSPI_WR_DATA 6'd11
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`define WBSPI_WR_BUS_CYCLE 6'd12
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`define WBSPI_WR_BUS_CYCLE 6'd12
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`define WBSPI_RD_DUMMY 6'd13
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`define WBSPI_RD_DUMMY 6'd13
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// `define WBSPI_QRD_ADDRESS 14
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// `define WBSPI_QRD_ADDRESS 14
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// `define WBSPI_QRD_DUMMY 15
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// `define WBSPI_QRD_DUMMY 15
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`define WBSPI_READ_CMD 6'd16
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`define WBSPI_READ_CMD 6'd16
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`define WBSPI_READ_DATA 6'd17
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`define WBSPI_READ_DATA 6'd17
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//`define WBSPI_WAIT_TIL_RDIDLE 18
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//`define WBSPI_WAIT_TIL_RDIDLE 18
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`define WBSPI_READ_ID_CMD 6'd19
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`define WBSPI_READ_ID_CMD 6'd19
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`define WBSPI_READ_ID 6'd20
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`define WBSPI_READ_ID 6'd20
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`define WBSPI_READ_STATUS 6'd21
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`define WBSPI_READ_STATUS 6'd21
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`define WBSPI_READ_CONFIG 6'd22
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`define WBSPI_READ_CONFIG 6'd22
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`define WBSPI_WRITE_STATUS 6'd23
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`define WBSPI_WRITE_STATUS 6'd23
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`define WBSPI_WRITE_CONFIG 6'd24
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`define WBSPI_WRITE_CONFIG 6'd24
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`define WBSPI_ERASE_WEN 6'd25
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`define WBSPI_ERASE_WEN 6'd25
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`define WBSPI_ERASE_CMD 6'd26
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`define WBSPI_ERASE_CMD 6'd26
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`define WBSPI_ERASE_BLOCK 6'd27
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`define WBSPI_ERASE_BLOCK 6'd27
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`define WBSPI_CLEAR_STATUS 6'd28
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`define WBSPI_CLEAR_STATUS 6'd28
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`define WBSPI_IDLE_CHECK_WIP 6'd29
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`define WBSPI_IDLE_CHECK_WIP 6'd29
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`define WBSPI_WAIT_TIL_IDLE 6'd30
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`define WBSPI_WAIT_TIL_IDLE 6'd30
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//
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//
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module wbspiflash(i_clk_100mhz,
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module wbspiflash(i_clk_100mhz,
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// Internal wishbone connections
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// Internal wishbone connections
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i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
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i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
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i_wb_addr, i_wb_data,
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i_wb_addr, i_wb_data,
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// Wishbone return values
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// Wishbone return values
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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// Quad Spi connections to the external device
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// Quad Spi connections to the external device
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o_spi_sck, o_spi_cs_n, i_spi_cs_n, o_spi_mosi, i_spi_miso,
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o_spi_sck, o_spi_cs_n, i_spi_cs_n, o_spi_mosi, i_spi_miso,
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o_interrupt);
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o_interrupt,
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i_bus_grant);
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parameter AW=18, // Address width, -2 for 32-bit word access
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parameter AW=18, // Address width, -2 for 32-bit word access
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PW=6, // Page address width (256 bytes,64 words)
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PW=6, // Page address width (256 bytes,64 words)
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SW=10; // Sector address width (4kB, 1kW)
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SW=10; // Sector address width (4kB, 1kW)
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// parameter AW, PW, Sw; // Address, page, and sector width(s)
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// parameter AW, PW, Sw; // Address, page, and sector width(s)
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input i_clk_100mhz;
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input i_clk_100mhz;
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// Wishbone, inputs first
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// Wishbone, inputs first
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input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
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input i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
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input [(AW-1):0] i_wb_addr;
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input [(AW-1):0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// then outputs
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// then outputs
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output reg o_wb_ack;
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output reg o_wb_ack;
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output reg o_wb_stall;
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output reg o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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// Quad SPI control wires
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// Quad SPI control wires
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output wire o_spi_sck;
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output wire o_spi_sck;
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output wire o_spi_cs_n;
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output wire o_spi_cs_n;
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input i_spi_cs_n;
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input i_spi_cs_n;
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output wire o_spi_mosi;
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output wire o_spi_mosi;
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input i_spi_miso;
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input i_spi_miso;
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// Interrupt line
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// Interrupt line
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output reg o_interrupt;
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output reg o_interrupt;
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// Do we own the bus?
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input i_bus_grant;
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// output wire [31:0] o_debug;
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// output wire [31:0] o_debug;
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reg spi_wr, spi_hold;
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reg spi_wr, spi_hold;
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reg [31:0] spi_in;
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reg [31:0] spi_in;
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reg [1:0] spi_len;
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reg [1:0] spi_len;
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wire [31:0] spi_out;
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wire [31:0] spi_out;
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wire spi_valid, spi_busy;
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wire spi_valid, spi_busy;
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wire w_spi_sck, w_spi_cs_n;
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wire w_spi_sck, w_spi_cs_n;
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wire w_spi_mosi;
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wire w_spi_mosi;
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// wire [22:0] spi_dbg;
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// wire [22:0] spi_dbg;
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lldspi lldriver(i_clk_100mhz,
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lldspi lldriver(i_clk_100mhz,
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spi_wr, spi_hold, spi_in, spi_len,
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spi_wr, spi_hold, spi_in, spi_len,
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spi_out, spi_valid, spi_busy,
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spi_out, spi_valid, spi_busy,
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w_spi_sck, w_spi_cs_n, i_spi_cs_n, w_spi_mosi,
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w_spi_sck, w_spi_cs_n, i_spi_cs_n, w_spi_mosi,
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i_spi_miso);
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i_spi_miso,
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i_bus_grant);
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// Erase status tracking
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// Erase status tracking
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reg write_in_progress, write_protect;
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reg write_in_progress, write_protect;
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reg [(AW-1-SW):0] erased_sector;
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reg [(AW-1-SW):0] erased_sector;
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reg dirty_sector;
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reg dirty_sector;
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initial begin
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initial begin
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write_in_progress = 1'b0;
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write_in_progress = 1'b0;
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erased_sector = 0;
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erased_sector = 0;
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dirty_sector = 1'b1;
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dirty_sector = 1'b1;
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write_protect = 1'b1;
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write_protect = 1'b1;
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end
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end
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reg [7:0] last_status;
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reg [7:0] last_status;
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reg spif_cmd, spif_override;
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reg spif_cmd, spif_override;
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reg [(AW-1):0] spif_addr;
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reg [(AW-1):0] spif_addr;
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reg [31:0] spif_data;
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reg [31:0] spif_data;
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reg [5:0] state;
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reg [5:0] state;
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reg spif_ctrl, spif_req;
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reg spif_ctrl, spif_req;
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wire [(AW-1-SW):0] spif_sector;
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wire [(AW-1-SW):0] spif_sector;
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assign spif_sector = spif_addr[(AW-1):SW];
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assign spif_sector = spif_addr[(AW-1):SW];
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// assign o_debug = { spi_wr, spi_hold, state, spi_dbg };
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// assign o_debug = { spi_wr, spi_hold, state, spi_dbg };
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initial state = `WBSPI_RESET;
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initial state = `WBSPI_RESET;
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initial o_wb_ack = 1'b0;
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initial o_wb_ack = 1'b0;
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initial o_wb_stall = 1'b1;
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initial o_wb_stall = 1'b1;
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initial spi_wr = 1'b0;
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initial spi_wr = 1'b0;
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initial spi_len = 2'b00;
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initial spi_len = 2'b00;
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initial o_interrupt= 1'b0;
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initial o_interrupt= 1'b0;
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always @(posedge i_clk_100mhz)
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always @(posedge i_clk_100mhz)
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begin
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begin
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if (state == `WBSPI_RESET)
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if (state == `WBSPI_RESET)
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begin
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begin
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// From a reset, we should
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// From a reset, we should
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// Enable the Quad I/O mode
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// Enable the Quad I/O mode
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// Disable the Write protection bits in the status register
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// Disable the Write protection bits in the status register
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// Chip should already be up and running, so we can start
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// Chip should already be up and running, so we can start
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// immediately ....
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// immediately ....
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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spi_wr <= 1'b0;
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spi_wr <= 1'b0;
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spi_hold <= 1'b0;
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spi_hold <= 1'b0;
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last_status <= 8'h00;
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last_status <= 8'h00;
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state <= `WBSPI_IDLE;
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state <= `WBSPI_IDLE;
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spif_req <= 1'b0;
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spif_req <= 1'b0;
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end else if (state == `WBSPI_IDLE)
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end else if (state == `WBSPI_IDLE)
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begin
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begin
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o_interrupt <= 1'b0;
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o_interrupt <= 1'b0;
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o_wb_stall <= 1'b0;
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o_wb_stall <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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spif_cmd <= i_wb_we;
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spif_cmd <= i_wb_we;
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spif_addr <= i_wb_addr;
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spif_addr <= i_wb_addr;
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spif_data <= i_wb_data;
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spif_data <= i_wb_data;
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spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
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spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
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spif_req <= (i_wb_ctrl_stb)||(i_wb_data_stb);
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spif_req <= (i_wb_ctrl_stb)||(i_wb_data_stb);
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spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
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spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
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spi_hold <= 1'b0;
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spi_hold <= 1'b0;
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// Data register access
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// Data register access
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if ((i_wb_data_stb)&&(i_wb_cyc))
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if ((i_wb_data_stb)&&(i_wb_cyc))
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begin
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begin
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|
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if (i_wb_we) // Request to write a page
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if (i_wb_we) // Request to write a page
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begin
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begin
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if((~write_protect)&&(~write_in_progress))
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if((~write_protect)&&(~write_in_progress))
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begin // 00
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begin // 00
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spi_wr <= 1'b1;
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spi_wr <= 1'b1;
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spi_len <= 2'b00; // 8 bits
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spi_len <= 2'b00; // 8 bits
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// Send a write enable command
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// Send a write enable command
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spi_in <= { 8'h06, 24'h00 };
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spi_in <= { 8'h06, 24'h00 };
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state <= `WBSPI_WEN;
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state <= `WBSPI_WEN;
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|
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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end else if (write_protect)
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end else if (write_protect)
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begin // whether or not write-in_progress ...
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begin // whether or not write-in_progress ...
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// Do nothing on a write protect
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// Do nothing on a write protect
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// violation
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// violation
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//
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//
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o_wb_ack <= 1'b1;
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o_wb_ack <= 1'b1;
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o_wb_stall <= 1'b0;
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o_wb_stall <= 1'b0;
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end else begin // write is in progress, wait
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end else begin // write is in progress, wait
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// for it to complete
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// for it to complete
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state <= `WBSPI_WAIT_WIP_CLEAR;
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state <= `WBSPI_WAIT_WIP_CLEAR;
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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end
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end
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end else if (~write_in_progress)
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end else if (~write_in_progress)
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begin // Read access, normal mode(s)
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begin // Read access, normal mode(s)
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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spi_wr <= 1'b1; // Write cmd to device
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spi_wr <= 1'b1; // Write cmd to device
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spi_in <= { 8'h0b,
|
spi_in <= { 8'h0b,
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{(22-AW){1'b0}},
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{(22-AW){1'b0}},
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i_wb_addr[(AW-1):0], 2'b00 };
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i_wb_addr[(AW-1):0], 2'b00 };
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state <= `WBSPI_RD_DUMMY;
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state <= `WBSPI_RD_DUMMY;
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spi_len <= 2'b11; // cmd+addr,32bits
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spi_len <= 2'b11; // cmd+addr,32bits
|
end else begin
|
end else begin
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// A write is in progress ... need to stall
|
// A write is in progress ... need to stall
|
// the bus until the write is complete.
|
// the bus until the write is complete.
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state <= `WBSPI_WAIT_WIP_CLEAR;
|
state <= `WBSPI_WAIT_WIP_CLEAR;
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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end
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end
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end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))
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end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))
|
begin
|
begin
|
o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
|
case(i_wb_addr[1:0])
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case(i_wb_addr[1:0])
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2'b00: begin // Erase command register
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2'b00: begin // Erase command register
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write_protect <= ~i_wb_data[28];
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write_protect <= ~i_wb_data[28];
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o_wb_stall <= 1'b0;
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o_wb_stall <= 1'b0;
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|
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if((i_wb_data[31])&&(~write_in_progress))
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if((i_wb_data[31])&&(~write_in_progress))
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begin
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begin
|
// Command an erase--ack it immediately
|
// Command an erase--ack it immediately
|
|
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
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o_wb_stall <= 1'b0;
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o_wb_stall <= 1'b0;
|
|
|
if ((i_wb_data[31])&&(~write_protect))
|
if ((i_wb_data[31])&&(~write_protect))
|
begin
|
begin
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00;
|
spi_len <= 2'b00;
|
// Send a write enable command
|
// Send a write enable command
|
spi_in <= { 8'h06, 24'h00 };
|
spi_in <= { 8'h06, 24'h00 };
|
state <= `WBSPI_ERASE_CMD;
|
state <= `WBSPI_ERASE_CMD;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
end else if (i_wb_data[31])
|
end else if (i_wb_data[31])
|
begin
|
begin
|
state <= `WBSPI_WAIT_WIP_CLEAR;
|
state <= `WBSPI_WAIT_WIP_CLEAR;
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end else
|
end else
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
end
|
end
|
2'b01: begin
|
2'b01: begin
|
/*
|
/*
|
// Write the configuration register
|
// Write the configuration register
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
// Need to send a write enable command first
|
// Need to send a write enable command first
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00; // 8 bits
|
spi_len <= 2'b00; // 8 bits
|
// Send a write enable command
|
// Send a write enable command
|
spi_in <= { 8'h06, 24'h00 };
|
spi_in <= { 8'h06, 24'h00 };
|
state <= `WBSPI_WRITE_CONFIG;
|
state <= `WBSPI_WRITE_CONFIG;
|
*/
|
*/
|
o_wb_ack <= 1'b1; // Ack immediately
|
o_wb_ack <= 1'b1; // Ack immediately
|
o_wb_stall <= 1'b0; // No stall, but do nothing
|
o_wb_stall <= 1'b0; // No stall, but do nothing
|
end
|
end
|
2'b10: begin
|
2'b10: begin
|
/*
|
/*
|
// Write the status register
|
// Write the status register
|
o_wb_ack <= 1'b1; // Ack immediately
|
o_wb_ack <= 1'b1; // Ack immediately
|
o_wb_stall <= 1'b1; // Stall other cmds
|
o_wb_stall <= 1'b1; // Stall other cmds
|
// Need to send a write enable command first
|
// Need to send a write enable command first
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00; // 8 bits
|
spi_len <= 2'b00; // 8 bits
|
// Send a write enable command
|
// Send a write enable command
|
spi_in <= { 8'h06, 24'h00 };
|
spi_in <= { 8'h06, 24'h00 };
|
state <= `WBSPI_WRITE_STATUS;
|
state <= `WBSPI_WRITE_STATUS;
|
*/
|
*/
|
o_wb_ack <= 1'b1; // Ack immediately
|
o_wb_ack <= 1'b1; // Ack immediately
|
o_wb_stall <= 1'b0; // No stall, but do nothing
|
o_wb_stall <= 1'b0; // No stall, but do nothing
|
end
|
end
|
2'b11: begin // Write the ID register??? makes no sense
|
2'b11: begin // Write the ID register??? makes no sense
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
end
|
end
|
endcase
|
endcase
|
end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))
|
end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))
|
begin
|
begin
|
case(i_wb_addr[1:0])
|
case(i_wb_addr[1:0])
|
2'b00: begin // Read local register
|
2'b00: begin // Read local register
|
if (write_in_progress) // Read status
|
if (write_in_progress) // Read status
|
begin// register, is write still in progress?
|
begin// register, is write still in progress?
|
state <= `WBSPI_READ_STATUS;
|
state <= `WBSPI_READ_STATUS;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b01;// 8 bits out, 8 bits in
|
spi_len <= 2'b01;// 8 bits out, 8 bits in
|
spi_in <= { 8'h05, 24'h00};
|
spi_in <= { 8'h05, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end else begin // Return w/o talking to device
|
end else begin // Return w/o talking to device
|
o_wb_ack <= 1'b1;
|
o_wb_ack <= 1'b1;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_data <= { write_in_progress,
|
o_wb_data <= { write_in_progress,
|
dirty_sector, spi_busy,
|
dirty_sector, spi_busy,
|
~write_protect,
|
~write_protect,
|
{(28-AW){1'b0}},
|
{(28-AW){1'b0}},
|
erased_sector, {(SW){1'b0}} };
|
erased_sector, {(SW){1'b0}} };
|
end end
|
end end
|
2'b01: begin // Read configuration register
|
2'b01: begin // Read configuration register
|
state <= `WBSPI_READ_CONFIG;
|
state <= `WBSPI_READ_CONFIG;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b01;
|
spi_len <= 2'b01;
|
spi_in <= { 8'h35, 24'h00};
|
spi_in <= { 8'h35, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
2'b10: begin // Read status register
|
2'b10: begin // Read status register
|
state <= `WBSPI_READ_STATUS;
|
state <= `WBSPI_READ_STATUS;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_in <= { 8'h05, 24'h00};
|
spi_in <= { 8'h05, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
2'b11: begin // Read ID register
|
2'b11: begin // Read ID register
|
state <= `WBSPI_READ_ID_CMD;
|
state <= `WBSPI_READ_ID_CMD;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00;
|
spi_len <= 2'b00;
|
spi_in <= { 8'h9f, 24'h00};
|
spi_in <= { 8'h9f, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
endcase
|
endcase
|
end else if ((~i_wb_cyc)&&(write_in_progress))
|
end else if ((~i_wb_cyc)&&(write_in_progress))
|
begin
|
begin
|
state <= `WBSPI_IDLE_CHECK_WIP;
|
state <= `WBSPI_IDLE_CHECK_WIP;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_in <= { 8'h05, 24'h00};
|
spi_in <= { 8'h05, 24'h00};
|
|
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
end else if (state == `WBSPI_WAIT_WIP_CLEAR)
|
end else if (state == `WBSPI_WAIT_WIP_CLEAR)
|
begin
|
begin
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
if (~spi_busy)
|
if (~spi_busy)
|
begin
|
begin
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_in <= { 8'h05, 24'h0000 };
|
spi_in <= { 8'h05, 24'h0000 };
|
spi_hold <= 1'b1;
|
spi_hold <= 1'b1;
|
spi_len <= 2'b01; // 16 bits write, so we can read 8
|
spi_len <= 2'b01; // 16 bits write, so we can read 8
|
state <= `WBSPI_CHECK_WIP_CLEAR;
|
state <= `WBSPI_CHECK_WIP_CLEAR;
|
end
|
end
|
end else if (state == `WBSPI_CHECK_WIP_CLEAR)
|
end else if (state == `WBSPI_CHECK_WIP_CLEAR)
|
begin
|
begin
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
// Repeat as often as necessary until we are clear
|
// Repeat as often as necessary until we are clear
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_in <= 32'h0000; // Values here are actually irrelevant
|
spi_in <= 32'h0000; // Values here are actually irrelevant
|
spi_hold <= 1'b1;
|
spi_hold <= 1'b1;
|
spi_len <= 2'b00; // One byte at a time
|
spi_len <= 2'b00; // One byte at a time
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
if ((spi_valid)&&(~spi_out[0]))
|
if ((spi_valid)&&(~spi_out[0]))
|
begin
|
begin
|
state <= `WBSPI_CHECK_WIP_DONE;
|
state <= `WBSPI_CHECK_WIP_DONE;
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
write_in_progress <= 1'b0;
|
write_in_progress <= 1'b0;
|
last_status <= spi_out[7:0];
|
last_status <= spi_out[7:0];
|
end
|
end
|
end else if (state == `WBSPI_CHECK_WIP_DONE)
|
end else if (state == `WBSPI_CHECK_WIP_DONE)
|
begin
|
begin
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
// Let's let the SPI port come back to a full idle,
|
// Let's let the SPI port come back to a full idle,
|
// and the chip select line go low before continuing
|
// and the chip select line go low before continuing
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_len <= 2'b00;
|
spi_len <= 2'b00;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
if ((o_spi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
|
if ((o_spi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
|
begin
|
begin
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
|
|
casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
|
casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
|
4'b00??: begin // Read data from ... somewhere
|
4'b00??: begin // Read data from ... somewhere
|
spi_wr <= 1'b1; // Write cmd to device
|
spi_wr <= 1'b1; // Write cmd to device
|
spi_in <= { 8'h0b, {(22-AW){1'b0}},
|
spi_in <= { 8'h0b, {(22-AW){1'b0}},
|
spif_addr[(AW-1):0], 2'b00 };
|
spif_addr[(AW-1):0], 2'b00 };
|
state <= `WBSPI_RD_DUMMY;
|
state <= `WBSPI_RD_DUMMY;
|
spi_len <= 2'b11; // Send cmd and addr
|
spi_len <= 2'b11; // Send cmd and addr
|
end
|
end
|
4'b10??: begin // Write data to ... anywhere
|
4'b10??: begin // Write data to ... anywhere
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00; // 8 bits
|
spi_len <= 2'b00; // 8 bits
|
// Send a write enable command
|
// Send a write enable command
|
spi_in <= { 8'h06, 24'h00 };
|
spi_in <= { 8'h06, 24'h00 };
|
state <= `WBSPI_WEN;
|
state <= `WBSPI_WEN;
|
end
|
end
|
4'b0110: begin // Read status register
|
4'b0110: begin // Read status register
|
state <= `WBSPI_READ_STATUS;
|
state <= `WBSPI_READ_STATUS;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_len <= 2'b01; // 8 bits out, 8 bits in
|
spi_in <= { 8'h05, 24'h00};
|
spi_in <= { 8'h05, 24'h00};
|
end
|
end
|
4'b0111: begin
|
4'b0111: begin
|
state <= `WBSPI_READ_ID_CMD;
|
state <= `WBSPI_READ_ID_CMD;
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_len <= 2'b00;
|
spi_len <= 2'b00;
|
spi_in <= { 8'h9f, 24'h00};
|
spi_in <= { 8'h9f, 24'h00};
|
end
|
end
|
default: begin //
|
default: begin //
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
end
|
end
|
endcase
|
endcase
|
// spif_cmd <= i_wb_we;
|
// spif_cmd <= i_wb_we;
|
// spif_addr <= i_wb_addr;
|
// spif_addr <= i_wb_addr;
|
// spif_data <= i_wb_data;
|
// spif_data <= i_wb_data;
|
// spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
|
// spif_ctrl <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
|
// spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
|
// spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
|
end
|
end
|
end else if (state == `WBSPI_WEN)
|
end else if (state == `WBSPI_WEN)
|
begin // We came here after issuing a write enable command
|
begin // We came here after issuing a write enable command
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
if ((~spi_busy)&&(o_spi_cs_n)&&(~spi_wr)) // Let's come to a full stop
|
if ((~spi_busy)&&(o_spi_cs_n)&&(~spi_wr)) // Let's come to a full stop
|
state <= `WBSPI_PP;
|
state <= `WBSPI_PP;
|
end else if (state == `WBSPI_PP)
|
end else if (state == `WBSPI_PP)
|
begin // We come here under a full stop / full port idle mode
|
begin // We come here under a full stop / full port idle mode
|
// Issue our command immediately
|
// Issue our command immediately
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_in <= { 8'h02, {(22-AW){1'b0}}, spif_addr, 2'b00 };
|
spi_in <= { 8'h02, {(22-AW){1'b0}}, spif_addr, 2'b00 };
|
spi_len <= 2'b11;
|
spi_len <= 2'b11;
|
spi_hold <= 1'b1;
|
spi_hold <= 1'b1;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
// Once we get busy, move on
|
// Once we get busy, move on
|
if (spi_busy)
|
if (spi_busy)
|
state <= `WBSPI_WR_DATA;
|
state <= `WBSPI_WR_DATA;
|
if (spif_sector == erased_sector)
|
if (spif_sector == erased_sector)
|
dirty_sector <= 1'b1;
|
dirty_sector <= 1'b1;
|
end else if (state == `WBSPI_WR_DATA)
|
end else if (state == `WBSPI_WR_DATA)
|
begin
|
begin
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spi_wr <= 1'b1; // write without waiting
|
spi_wr <= 1'b1; // write without waiting
|
spi_in <= {
|
spi_in <= {
|
spif_data[ 7: 0],
|
spif_data[ 7: 0],
|
spif_data[15: 8],
|
spif_data[15: 8],
|
spif_data[23:16],
|
spif_data[23:16],
|
spif_data[31:24] };
|
spif_data[31:24] };
|
spi_len <= 2'b11; // Write 4 bytes
|
spi_len <= 2'b11; // Write 4 bytes
|
spi_hold <= 1'b1;
|
spi_hold <= 1'b1;
|
if (~spi_busy)
|
if (~spi_busy)
|
begin
|
begin
|
o_wb_ack <= spif_req; // Ack when command given
|
o_wb_ack <= spif_req; // Ack when command given
|
state <= `WBSPI_WR_BUS_CYCLE;
|
state <= `WBSPI_WR_BUS_CYCLE;
|
end
|
end
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
end else if (state == `WBSPI_WR_BUS_CYCLE)
|
end else if (state == `WBSPI_WR_BUS_CYCLE)
|
begin
|
begin
|
o_wb_ack <= 1'b0; // Turn off our ack and stall flags
|
o_wb_ack <= 1'b0; // Turn off our ack and stall flags
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_hold <= 1'b1;
|
spi_hold <= 1'b1;
|
write_in_progress <= 1'b1;
|
write_in_progress <= 1'b1;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
if (~i_wb_cyc)
|
if (~i_wb_cyc)
|
begin
|
begin
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
end else if (spi_wr)
|
end else if (spi_wr)
|
begin // Give the SPI a chance to get busy on the last write
|
begin // Give the SPI a chance to get busy on the last write
|
// Do nothing here.
|
// Do nothing here.
|
end else if ((i_wb_data_stb)&&(i_wb_we)
|
end else if ((i_wb_data_stb)&&(i_wb_we)
|
&&(i_wb_addr == (spif_addr+1))
|
&&(i_wb_addr == (spif_addr+1))
|
&&(i_wb_addr[(AW-1):PW]==spif_addr[(AW-1):PW]))
|
&&(i_wb_addr[(AW-1):PW]==spif_addr[(AW-1):PW]))
|
begin
|
begin
|
// CHECK ME!
|
// CHECK ME!
|
spif_cmd <= 1'b1;
|
spif_cmd <= 1'b1;
|
spif_data <= i_wb_data;
|
spif_data <= i_wb_data;
|
spif_addr <= i_wb_addr;
|
spif_addr <= i_wb_addr;
|
spif_ctrl <= 1'b0;
|
spif_ctrl <= 1'b0;
|
spif_req<= 1'b1;
|
spif_req<= 1'b1;
|
// We'll keep the bus stalled on this request
|
// We'll keep the bus stalled on this request
|
// for a while
|
// for a while
|
state <= `WBSPI_WR_DATA;
|
state <= `WBSPI_WR_DATA;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
|
end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
|
begin
|
begin
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
end // Otherwise we stay here
|
end // Otherwise we stay here
|
end else if (state == `WBSPI_RD_DUMMY)
|
end else if (state == `WBSPI_RD_DUMMY)
|
begin
|
begin
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_wr <= 1'b1; // Non-stop
|
spi_wr <= 1'b1; // Non-stop
|
// Need to read one byte of dummy data,
|
// Need to read one byte of dummy data,
|
// just to consume 8 clocks
|
// just to consume 8 clocks
|
spi_in <= { 8'h00, 24'h00 };
|
spi_in <= { 8'h00, 24'h00 };
|
spi_len <= 2'b00; // Read 8 bits
|
spi_len <= 2'b00; // Read 8 bits
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
|
|
if ((~spi_busy)&&(~o_spi_cs_n))
|
if ((~spi_busy)&&(~o_spi_cs_n))
|
// Our command was accepted
|
// Our command was accepted
|
state <= `WBSPI_READ_CMD;
|
state <= `WBSPI_READ_CMD;
|
end else if (state == `WBSPI_READ_CMD)
|
end else if (state == `WBSPI_READ_CMD)
|
begin // Issue our first command to read 32 bits.
|
begin // Issue our first command to read 32 bits.
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_in <= { 8'hff, 24'h00 }; // Empty
|
spi_in <= { 8'hff, 24'h00 }; // Empty
|
spi_len <= 2'b11; // Read 32 bits
|
spi_len <= 2'b11; // Read 32 bits
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
if ((spi_valid)&&(spi_len == 2'b11))
|
if ((spi_valid)&&(spi_len == 2'b11))
|
state <= `WBSPI_READ_DATA;
|
state <= `WBSPI_READ_DATA;
|
end else if (state == `WBSPI_READ_DATA)
|
end else if (state == `WBSPI_READ_DATA)
|
begin
|
begin
|
// Pipelined read support
|
// Pipelined read support
|
spi_wr <=((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
|
spi_wr <=((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
|
spi_in <= 32'h00;
|
spi_in <= 32'h00;
|
spi_len <= 2'b11;
|
spi_len <= 2'b11;
|
// Don't let the device go to idle until the bus cycle ends.
|
// Don't let the device go to idle until the bus cycle ends.
|
// This actually prevents a *really* nasty race condition,
|
// This actually prevents a *really* nasty race condition,
|
// where the strobe comes in after the lower level device
|
// where the strobe comes in after the lower level device
|
// has decided to stop waiting. The write is then issued,
|
// has decided to stop waiting. The write is then issued,
|
// but no one is listening. By leaving the device open,
|
// but no one is listening. By leaving the device open,
|
// the device is kept in a state where a valid strobe
|
// the device is kept in a state where a valid strobe
|
// here will be useful. Of course, we don't accept
|
// here will be useful. Of course, we don't accept
|
// all commands, just reads. Further, the strobe needs
|
// all commands, just reads. Further, the strobe needs
|
// to be high for two clocks cycles without changing
|
// to be high for two clocks cycles without changing
|
// anything on the bus--one for us to notice it and pull
|
// anything on the bus--one for us to notice it and pull
|
// our head out of the sand, and a second for whoever
|
// our head out of the sand, and a second for whoever
|
// owns the bus to realize their command went through.
|
// owns the bus to realize their command went through.
|
spi_hold <= 1'b1;
|
spi_hold <= 1'b1;
|
spif_req<= (spif_req) && (i_wb_cyc);
|
spif_req<= (spif_req) && (i_wb_cyc);
|
if ((spi_valid)&&(~spi_in[31]))
|
if ((spi_valid)&&(~spi_in[31]))
|
begin // Single pulse acknowledge and write data out
|
begin // Single pulse acknowledge and write data out
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= (~spi_wr);
|
o_wb_stall <= (~spi_wr);
|
// adjust endian-ness to match the PC
|
// adjust endian-ness to match the PC
|
o_wb_data <= { spi_out[7:0], spi_out[15:8],
|
o_wb_data <= { spi_out[7:0], spi_out[15:8],
|
spi_out[23:16], spi_out[31:24] };
|
spi_out[23:16], spi_out[31:24] };
|
state <= (spi_wr)?`WBSPI_READ_DATA
|
state <= (spi_wr)?`WBSPI_READ_DATA
|
: `WBSPI_WAIT_TIL_IDLE;
|
: `WBSPI_WAIT_TIL_IDLE;
|
spif_req <= spi_wr;
|
spif_req <= spi_wr;
|
spi_hold <= (~spi_wr);
|
spi_hold <= (~spi_wr);
|
if (spi_wr)
|
if (spi_wr)
|
spif_addr <= i_wb_addr;
|
spif_addr <= i_wb_addr;
|
end else if (~i_wb_cyc)
|
end else if (~i_wb_cyc)
|
begin // FAIL SAFE: If the bus cycle ends, forget why we're
|
begin // FAIL SAFE: If the bus cycle ends, forget why we're
|
// here, just go back to idle
|
// here, just go back to idle
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end else begin
|
end else begin
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
end
|
end
|
end else if (state == `WBSPI_READ_ID_CMD)
|
end else if (state == `WBSPI_READ_ID_CMD)
|
begin // We came into here immediately after issuing a 0x9f command
|
begin // We came into here immediately after issuing a 0x9f command
|
// Now we need to read 32 bits of data. Result should be
|
// Now we need to read 32 bits of data. Result should be
|
// 0x0102154d (8'h manufacture ID, 16'h device ID, followed
|
// 0x0102154d (8'h manufacture ID, 16'h device ID, followed
|
// by the number of extended bytes available 8'h4d).
|
// by the number of extended bytes available 8'h4d).
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall<= 1'b1;
|
o_wb_stall<= 1'b1;
|
|
|
spi_wr <= 1'b1; // No data to send, but need four bytes, since
|
spi_wr <= 1'b1; // No data to send, but need four bytes, since
|
spi_len <= 2'b11; // 32 bits of data are ... useful
|
spi_len <= 2'b11; // 32 bits of data are ... useful
|
spi_in <= 32'h00; // Irrelevant
|
spi_in <= 32'h00; // Irrelevant
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
if ((~spi_busy)&&(~o_spi_cs_n)&&(spi_len == 2'b11))
|
if ((~spi_busy)&&(~o_spi_cs_n)&&(spi_len == 2'b11))
|
// Our command was accepted, now go read the result
|
// Our command was accepted, now go read the result
|
state <= `WBSPI_READ_ID;
|
state <= `WBSPI_READ_ID;
|
end else if (state == `WBSPI_READ_ID)
|
end else if (state == `WBSPI_READ_ID)
|
begin
|
begin
|
o_wb_ack <= 1'b0; // Assuming we're still waiting
|
o_wb_ack <= 1'b0; // Assuming we're still waiting
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_wr <= 1'b0; // No more writes, we've already written the cmd
|
spi_wr <= 1'b0; // No more writes, we've already written the cmd
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
|
|
// Here, we just wait until the result comes back
|
// Here, we just wait until the result comes back
|
// The problem is, the result may be the previous result.
|
// The problem is, the result may be the previous result.
|
// So we use spi_len as an indicator
|
// So we use spi_len as an indicator
|
spi_len <= 2'b00;
|
spi_len <= 2'b00;
|
if((spi_valid)&&(spi_len==2'b00))
|
if((spi_valid)&&(spi_len==2'b00))
|
begin // Put the results out as soon as possible
|
begin // Put the results out as soon as possible
|
o_wb_data <= spi_out[31:0];
|
o_wb_data <= spi_out[31:0];
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
spif_req <= 1'b0;
|
spif_req <= 1'b0;
|
end else if ((~spi_busy)&&(o_spi_cs_n))
|
end else if ((~spi_busy)&&(o_spi_cs_n))
|
begin
|
begin
|
state <= `WBSPI_IDLE;
|
state <= `WBSPI_IDLE;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
end
|
end
|
end else if (state == `WBSPI_READ_STATUS)
|
end else if (state == `WBSPI_READ_STATUS)
|
begin // We enter after the command has been given, for now just
|
begin // We enter after the command has been given, for now just
|
// read and return
|
// read and return
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
if (spi_valid)
|
if (spi_valid)
|
begin
|
begin
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
spif_req <= 1'b0;
|
spif_req <= 1'b0;
|
last_status <= spi_out[7:0];
|
last_status <= spi_out[7:0];
|
write_in_progress <= spi_out[0];
|
write_in_progress <= spi_out[0];
|
if (spif_addr[1:0] == 2'b00) // Local read, checking
|
if (spif_addr[1:0] == 2'b00) // Local read, checking
|
begin // status, 'cause we're writing
|
begin // status, 'cause we're writing
|
o_wb_data <= { spi_out[0],
|
o_wb_data <= { spi_out[0],
|
dirty_sector, spi_busy,
|
dirty_sector, spi_busy,
|
~write_protect,
|
~write_protect,
|
{(28-AW){1'b0}},
|
{(28-AW){1'b0}},
|
erased_sector, {(SW){1'b0}} };
|
erased_sector, {(SW){1'b0}} };
|
end else begin
|
end else begin
|
o_wb_data <= { 24'h00, spi_out[7:0] };
|
o_wb_data <= { 24'h00, spi_out[7:0] };
|
end
|
end
|
end
|
end
|
|
|
if ((~spi_busy)&&(~spi_wr))
|
if ((~spi_busy)&&(~spi_wr))
|
state <= `WBSPI_IDLE;
|
state <= `WBSPI_IDLE;
|
end else if (state == `WBSPI_READ_CONFIG)
|
end else if (state == `WBSPI_READ_CONFIG)
|
begin // We enter after the command has been given, for now just
|
begin // We enter after the command has been given, for now just
|
// read and return
|
// read and return
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
|
|
if (spi_valid)
|
if (spi_valid)
|
o_wb_data <= { 24'h00, spi_out[7:0] };
|
o_wb_data <= { 24'h00, spi_out[7:0] };
|
|
|
if ((~spi_busy)&&(~spi_wr))
|
if ((~spi_busy)&&(~spi_wr))
|
begin
|
begin
|
state <= `WBSPI_IDLE;
|
state <= `WBSPI_IDLE;
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
spif_req <= 1'b0;
|
spif_req <= 1'b0;
|
end
|
end
|
end else if (state == `WBSPI_WRITE_CONFIG)
|
end else if (state == `WBSPI_WRITE_CONFIG)
|
begin // We enter immediately after commanding a WEN
|
begin // We enter immediately after commanding a WEN
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_len <= 2'b10;
|
spi_len <= 2'b10;
|
spi_in <= { 8'h01, last_status,
|
spi_in <= { 8'h01, last_status,
|
spif_data[7:2], 1'b0,spif_data[0], 8'h00 };
|
spif_data[7:2], 1'b0,spif_data[0], 8'h00 };
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
if ((~spi_busy)&&(~spi_wr))
|
if ((~spi_busy)&&(~spi_wr))
|
begin
|
begin
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
write_in_progress <= 1'b1;
|
write_in_progress <= 1'b1;
|
end
|
end
|
end else if (state == `WBSPI_WRITE_STATUS)
|
end else if (state == `WBSPI_WRITE_STATUS)
|
begin // We enter immediately after commanding a WEN
|
begin // We enter immediately after commanding a WEN
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
spi_len <= 2'b01;
|
spi_len <= 2'b01;
|
spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
|
spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
|
// last_status <= i_wb_data[7:0]; // We'll read this in a moment
|
// last_status <= i_wb_data[7:0]; // We'll read this in a moment
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
if ((~spi_busy)&&(~spi_wr))
|
if ((~spi_busy)&&(~spi_wr))
|
begin
|
begin
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
last_status <= spif_data[7:0];
|
last_status <= spif_data[7:0];
|
write_in_progress <= 1'b1;
|
write_in_progress <= 1'b1;
|
if(((last_status[6])||(last_status[5]))
|
if(((last_status[6])||(last_status[5]))
|
&&((~spif_data[6])&&(~spif_data[5])))
|
&&((~spif_data[6])&&(~spif_data[5])))
|
state <= `WBSPI_CLEAR_STATUS;
|
state <= `WBSPI_CLEAR_STATUS;
|
else
|
else
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
end
|
end
|
end else if (state == `WBSPI_ERASE_CMD)
|
end else if (state == `WBSPI_ERASE_CMD)
|
begin // Know that WIP is clear on entry, WEN has just been commanded
|
begin // Know that WIP is clear on entry, WEN has just been commanded
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
|
|
// Here's the erase command
|
// Here's the erase command
|
//spi_in <= { 8'hd8, 4'h0, spif_data[17:14], 14'h000, 2'b00 };
|
//spi_in <= { 8'hd8, 4'h0, spif_data[17:14], 14'h000, 2'b00 };
|
spi_in <= { 8'h20, 4'h0, spif_data[(AW-1):SW],
|
spi_in <= { 8'h20, 4'h0, spif_data[(AW-1):SW],
|
{(SW){1'b0}}, 2'b00 };
|
{(SW){1'b0}}, 2'b00 };
|
spi_len <= 2'b11; // 32 bit write
|
spi_len <= 2'b11; // 32 bit write
|
// together with setting our copy of the WIP bit
|
// together with setting our copy of the WIP bit
|
write_in_progress <= 1'b1;
|
write_in_progress <= 1'b1;
|
// keeping track of which sector we just erased
|
// keeping track of which sector we just erased
|
erased_sector <= spif_data[(AW-1):SW];
|
erased_sector <= spif_data[(AW-1):SW];
|
// and marking this erase sector as no longer dirty
|
// and marking this erase sector as no longer dirty
|
dirty_sector <= 1'b0;
|
dirty_sector <= 1'b0;
|
|
|
// Wait for a full stop before issuing this command
|
// Wait for a full stop before issuing this command
|
if ((~spi_busy)&&(~spi_wr)&&(o_spi_cs_n))
|
if ((~spi_busy)&&(~spi_wr)&&(o_spi_cs_n))
|
begin // When our command is accepted, move to the next state
|
begin // When our command is accepted, move to the next state
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
state <= `WBSPI_ERASE_BLOCK;
|
state <= `WBSPI_ERASE_BLOCK;
|
end
|
end
|
end else if (state == `WBSPI_ERASE_BLOCK)
|
end else if (state == `WBSPI_ERASE_BLOCK)
|
begin
|
begin
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
// When the port clears, we can head back to idle
|
// When the port clears, we can head back to idle
|
if ((~spi_busy)&&(~spi_wr))
|
if ((~spi_busy)&&(~spi_wr))
|
begin
|
begin
|
o_wb_ack <= spif_req;
|
o_wb_ack <= spif_req;
|
state <= `WBSPI_IDLE;
|
state <= `WBSPI_IDLE;
|
end
|
end
|
end else if (state == `WBSPI_CLEAR_STATUS)
|
end else if (state == `WBSPI_CLEAR_STATUS)
|
begin // Issue a clear status command
|
begin // Issue a clear status command
|
spi_wr <= 1'b1;
|
spi_wr <= 1'b1;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_len <= 2'b00; // 8 bit command
|
spi_len <= 2'b00; // 8 bit command
|
spi_in <= { 8'h30, 24'h00 };
|
spi_in <= { 8'h30, 24'h00 };
|
last_status[6:5] <= 2'b00;
|
last_status[6:5] <= 2'b00;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
if ((spi_wr)&&(~spi_busy))
|
if ((spi_wr)&&(~spi_busy))
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
state <= `WBSPI_WAIT_TIL_IDLE;
|
end else if (state == `WBSPI_IDLE_CHECK_WIP)
|
end else if (state == `WBSPI_IDLE_CHECK_WIP)
|
begin // We are now in read status register mode
|
begin // We are now in read status register mode
|
|
|
// No bus commands have (yet) been given
|
// No bus commands have (yet) been given
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spif_req <= (spif_req) && (i_wb_cyc);
|
spif_req <= (spif_req) && (i_wb_cyc);
|
|
|
// Stay in this mode unless/until we get a command, or
|
// Stay in this mode unless/until we get a command, or
|
// the write is over
|
// the write is over
|
spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
|
spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
|
&&(write_in_progress));
|
&&(write_in_progress));
|
spi_len <= 2'b00; // 8 bit reads
|
spi_len <= 2'b00; // 8 bit reads
|
if (spi_valid)
|
if (spi_valid)
|
begin
|
begin
|
write_in_progress <= spi_out[0];
|
write_in_progress <= spi_out[0];
|
if ((~spi_out[0])&&(write_in_progress))
|
if ((~spi_out[0])&&(write_in_progress))
|
o_interrupt <= 1'b1;
|
o_interrupt <= 1'b1;
|
end else
|
end else
|
o_interrupt <= 1'b0;
|
o_interrupt <= 1'b0;
|
|
|
if ((~spi_wr)&&(~spi_busy)&&(o_spi_cs_n))
|
if ((~spi_wr)&&(~spi_busy)&&(o_spi_cs_n))
|
begin // We can now go to idle and process a command
|
begin // We can now go to idle and process a command
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
state <= `WBSPI_IDLE;
|
state <= `WBSPI_IDLE;
|
end
|
end
|
end else // if (state == `WBSPI_WAIT_TIL_IDLE) or anything else
|
end else // if (state == `WBSPI_WAIT_TIL_IDLE) or anything else
|
begin
|
begin
|
spi_wr <= 1'b0;
|
spi_wr <= 1'b0;
|
spi_hold <= 1'b0;
|
spi_hold <= 1'b0;
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
o_wb_ack <= 1'b0;
|
o_wb_ack <= 1'b0;
|
spif_req <= 1'b0;
|
spif_req <= 1'b0;
|
if ((~spi_busy)&&(o_spi_cs_n)&&(~spi_wr)) // Wait for a full
|
if ((~spi_busy)&&(o_spi_cs_n)&&(~spi_wr)) // Wait for a full
|
begin // clearing of the SPI port before moving on
|
begin // clearing of the SPI port before moving on
|
state <= `WBSPI_IDLE;
|
state <= `WBSPI_IDLE;
|
o_wb_stall <= 1'b0;
|
o_wb_stall <= 1'b0;
|
o_wb_ack <= 1'b0; // Shouldn't be acking anything here
|
o_wb_ack <= 1'b0; // Shouldn't be acking anything here
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// Command and control during the reset sequence
|
// Command and control during the reset sequence
|
assign o_spi_cs_n = w_spi_cs_n;
|
assign o_spi_cs_n = w_spi_cs_n;
|
assign o_spi_sck = w_spi_sck;
|
assign o_spi_sck = w_spi_sck;
|
assign o_spi_mosi = w_spi_mosi;
|
assign o_spi_mosi = w_spi_mosi;
|
endmodule
|
endmodule
|
|
|
