////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbucompactlines.v
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// Filename: wbucompactlines.v
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//
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//
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// Project: XuLA2 board
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// Project: FPGA library
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//
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//
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// Purpose: Removes 'end of line' characters placed at the end of every
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// Purpose: Removes 'end of line' characters placed at the end of every
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// deworded word, unless we're idle or the line is too long.
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// deworded word, unless we're idle or the line is too long.
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// This helps to format the output nicely to fit in an 80-character
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// This helps to format the output nicely to fit in an 80-character
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// display, should you need to do so for debugging.
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// display, should you need to do so for debugging.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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// When to apply a new line?
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// When to apply a new line?
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// When no prior new line exists
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// When no prior new line exists
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// or when prior line length exceeds (72)
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// or when prior line length exceeds (72)
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// Between codewords (need inserted newline)
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// Between codewords (need inserted newline)
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// When bus has become idle (~wb_cyc)&&(~busys)
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// When bus has become idle (~wb_cyc)&&(~busys)
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//
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//
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// So, if every codeword ends in a newline, what we
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// So, if every codeword ends in a newline, what we
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// really need to do is to remove newlines. Thus, if
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// really need to do is to remove newlines. Thus, if
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// i_stb goes high while i_tx_busy, we skip the newline
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// i_stb goes high while i_tx_busy, we skip the newline
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// unless the line is empty. ... But i_stb will always
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// unless the line is empty. ... But i_stb will always
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// go high while i_tx_busy. How about if the line
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// go high while i_tx_busy. How about if the line
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// length exceeds 72, we do nothing, but record the
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// length exceeds 72, we do nothing, but record the
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// last word. If the last word was a <incomplete-thought>
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// last word. If the last word was a <incomplete-thought>
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//
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//
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//
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//
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module wbucompactlines(i_clk, i_stb, i_nl_hexbits, o_stb, o_nl_hexbits,
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module wbucompactlines(i_clk, i_stb, i_nl_hexbits, o_stb, o_nl_hexbits,
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i_bus_busy, i_tx_busy, o_busy);
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i_bus_busy, i_tx_busy, o_busy);
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input i_clk, i_stb;
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input i_clk, i_stb;
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input [6:0] i_nl_hexbits;
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input [6:0] i_nl_hexbits;
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output reg o_stb;
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output reg o_stb;
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output reg [6:0] o_nl_hexbits;
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output reg [6:0] o_nl_hexbits;
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input i_bus_busy;
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input i_bus_busy;
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input i_tx_busy;
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input i_tx_busy;
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output wire o_busy;
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output wire o_busy;
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reg last_out_nl, last_in_nl;
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reg last_out_nl, last_in_nl;
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initial last_out_nl = 1'b1;
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initial last_out_nl = 1'b1;
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initial last_in_nl = 1'b1;
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initial last_in_nl = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((~i_tx_busy)&&(o_stb))
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if ((~i_tx_busy)&&(o_stb))
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last_out_nl <= (o_nl_hexbits[6]);
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last_out_nl <= (o_nl_hexbits[6]);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_stb)&&(~o_busy))
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if ((i_stb)&&(~o_busy))
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last_in_nl <= (i_nl_hexbits[6]);
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last_in_nl <= (i_nl_hexbits[6]);
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// Now, let's count how long our lines are
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// Now, let's count how long our lines are
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reg [6:0] linelen;
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reg [6:0] linelen;
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initial linelen = 7'h00;
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initial linelen = 7'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((~i_tx_busy)&&(o_stb))
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if ((~i_tx_busy)&&(o_stb))
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begin
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begin
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if (o_nl_hexbits[6])
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if (o_nl_hexbits[6])
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linelen <= 0;
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linelen <= 0;
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else
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else
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linelen <= linelen + 7'h1;
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linelen <= linelen + 7'h1;
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end
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end
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reg full_line;
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reg full_line;
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initial full_line = 1'b0;
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initial full_line = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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full_line <= (linelen > 7'd72);
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full_line <= (linelen > 7'd72);
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// Now that we know whether or not the last character was a newline,
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// Now that we know whether or not the last character was a newline,
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// and indeed how many characters we have in any given line, we can
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// and indeed how many characters we have in any given line, we can
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// selectively remove newlines from our output stream.
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// selectively remove newlines from our output stream.
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initial o_stb = 1'b0;
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initial o_stb = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_stb)&&(~o_busy))
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if ((i_stb)&&(~o_busy))
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begin
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begin
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o_stb <= (full_line)||(~i_nl_hexbits[6]);
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o_stb <= (full_line)||(~i_nl_hexbits[6]);
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o_nl_hexbits <= i_nl_hexbits;
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o_nl_hexbits <= i_nl_hexbits;
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end else if (~o_busy)
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end else if (~o_busy)
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begin
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begin
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o_stb <= (~i_tx_busy)&&(~i_bus_busy)&&(~last_out_nl)&&(last_in_nl);
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o_stb <= (~i_tx_busy)&&(~i_bus_busy)&&(~last_out_nl)&&(last_in_nl);
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o_nl_hexbits <= 7'h40;
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o_nl_hexbits <= 7'h40;
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end else if (~i_tx_busy)
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end else if (~i_tx_busy)
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o_stb <= 1'b0;
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o_stb <= 1'b0;
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reg r_busy;
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reg r_busy;
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initial r_busy = 1'b0;
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initial r_busy = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_busy <= (o_stb);
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r_busy <= (o_stb);
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assign o_busy = (r_busy)||(o_stb);
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assign o_busy = (r_busy)||(o_stb);
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/*
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/*
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output wire [27:0] o_dbg;
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output wire [27:0] o_dbg;
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assign o_dbg = { o_stb, o_nl_hexbits, o_busy, r_busy, full_line,
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assign o_dbg = { o_stb, o_nl_hexbits, o_busy, r_busy, full_line,
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i_bus_busy, linelen, i_tx_busy, i_stb, i_nl_hexbits };
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i_bus_busy, linelen, i_tx_busy, i_stb, i_nl_hexbits };
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*/
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*/
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endmodule
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endmodule
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