////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbucompress.v
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// Filename: wbucompress.v
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//
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//
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// Project: XuLA2 board
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// Project: XuLA2 board
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//
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//
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// Purpose: When reading many words that are identical, it makes no sense
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// Purpose: When reading many words that are identical, it makes no sense
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// to spend the time transmitting the same thing over and over
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// to spend the time transmitting the same thing over and over
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// again, especially on a slow channel. Hence this routine uses a table
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// again, especially on a slow channel. Hence this routine uses a table
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// lookup to see if the word to be transmitted was one from the recent
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// lookup to see if the word to be transmitted was one from the recent
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// past. If so, the word is replaced with an address of the recently
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// past. If so, the word is replaced with an address of the recently
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// transmitted word. Mind you, the table lookup takes one clock per table
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// transmitted word. Mind you, the table lookup takes one clock per table
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// entry, so even if a word is in the table it might not be found in time.
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// entry, so even if a word is in the table it might not be found in time.
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// If the word is not in the table, or if it isn't found due to a lack of
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// If the word is not in the table, or if it isn't found due to a lack of
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// time, the word is placed into the table while incrementing every other
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// time, the word is placed into the table while incrementing every other
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// table address.
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// table address.
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//
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//
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// Oh, and on a new address--the table is reset and starts over. This way,
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// Oh, and on a new address--the table is reset and starts over. This way,
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// any time the host software changes, the host software will always start
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// any time the host software changes, the host software will always start
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// by issuing a new address--hence the table is reset for every new piece
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// by issuing a new address--hence the table is reset for every new piece
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// of software that may wish to communicate.
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// of software that may wish to communicate.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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// All input words are valid codewords. If we can, we make them
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// All input words are valid codewords. If we can, we make them
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// better here.
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// better here.
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module wbucompress(i_clk, i_stb, i_codword, o_stb, o_cword, i_busy);
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module wbucompress(i_clk, i_stb, i_codword, o_stb, o_cword, i_busy);
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parameter DW=32, CW=36, TBITS=10;
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parameter DW=32, CW=36, TBITS=10;
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input i_clk, i_stb;
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input i_clk, i_stb;
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input [(CW-1):0] i_codword;
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input [(CW-1):0] i_codword;
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output wire o_stb;
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output wire o_stb;
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output wire [(CW-1):0] o_cword;
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output wire [(CW-1):0] o_cword;
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input i_busy;
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input i_busy;
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//
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//
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//
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//
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// First stage is to compress the address.
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// First stage is to compress the address.
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// This stage requires one clock.
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// This stage requires one clock.
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//
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//
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// ISTB,ICODWORD
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// ISTB,ICODWORD
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// ISTB2,IWRD2 ASTB,AWORD
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// ISTB2,IWRD2 ASTB,AWORD
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// ISTB3,IWRD3 ASTB2,AWRD2 I_BUSY(1)
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// ISTB3,IWRD3 ASTB2,AWRD2 I_BUSY(1)
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// ISTB3,IWRD3 ASTB2,AWRD2 I_BUSY(1)
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// ISTB3,IWRD3 ASTB2,AWRD2 I_BUSY(1)
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// ISTB3,IWRD3 ASTB2,AWRD2 I_BUSY(1)
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// ISTB3,IWRD3 ASTB2,AWRD2 I_BUSY(1)
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// ISTB3,IWRD3 ASTB2,AWRD2
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// ISTB3,IWRD3 ASTB2,AWRD2
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// ISTB4,IWRD4 ASTB3,AWRD3 I_BUSY(2)
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// ISTB4,IWRD4 ASTB3,AWRD3 I_BUSY(2)
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// ISTB4,IWRD4 ASTB3,AWRD3 I_BUSY(2)
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// ISTB4,IWRD4 ASTB3,AWRD3 I_BUSY(2)
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// ISTB4,IWRD4 ASTB3,AWRD3 I_BUSY(2)
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// ISTB4,IWRD4 ASTB3,AWRD3 I_BUSY(2)
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reg a_stb;
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reg a_stb;
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reg [35:0] a_addrword;
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reg [35:0] a_addrword;
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wire [31:0] w_addr;
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wire [31:0] w_addr;
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assign w_addr = i_codword[31:0];
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assign w_addr = i_codword[31:0];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_stb)&&(~a_stb))
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if ((i_stb)&&(~a_stb))
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begin
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begin
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if (i_codword[35:32] != 4'h2)
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if (i_codword[35:32] != 4'h2)
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begin
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begin
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a_addrword <= i_codword;
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a_addrword <= i_codword;
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end else if (w_addr[31:6] == 26'h00)
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end else if (w_addr[31:6] == 26'h00)
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a_addrword <= { 6'hc, w_addr[ 5:0], 24'h00 };
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a_addrword <= { 6'hc, w_addr[ 5:0], 24'h00 };
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else if (w_addr[31:12] == 20'h00)
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else if (w_addr[31:12] == 20'h00)
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a_addrword <= { 6'hd, w_addr[11:0], 18'h00 };
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a_addrword <= { 6'hd, w_addr[11:0], 18'h00 };
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else if (w_addr[31:18] == 14'h00)
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else if (w_addr[31:18] == 14'h00)
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a_addrword <= { 6'he, w_addr[17:0], 12'h00 };
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a_addrword <= { 6'he, w_addr[17:0], 12'h00 };
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else if (w_addr[31:24] == 8'h00)
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else if (w_addr[31:24] == 8'h00)
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a_addrword <= { 6'hf, w_addr[23:0], 6'h00 };
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a_addrword <= { 6'hf, w_addr[23:0], 6'h00 };
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else begin
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else begin
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a_addrword <= i_codword;
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a_addrword <= i_codword;
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end
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end
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end
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end
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initial a_stb = 1'b0;
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initial a_stb = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_stb)&&(~a_stb))
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if ((i_stb)&&(~a_stb))
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a_stb <= i_stb;
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a_stb <= i_stb;
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else if (~i_busy)
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else if (~i_busy)
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a_stb <= 1'b0;
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a_stb <= 1'b0;
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//
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//
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//
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//
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// The next stage attempts to replace data codewords with previous
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// The next stage attempts to replace data codewords with previous
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// codewords that may have been sent. The memory is only allowed
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// codewords that may have been sent. The memory is only allowed
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// to be as old as the last new address command. In this fashion,
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// to be as old as the last new address command. In this fashion,
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// any program that wishes to talk to the device can start with a
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// any program that wishes to talk to the device can start with a
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// known compression table by simply setting the address and then
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// known compression table by simply setting the address and then
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// reading from the device.
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// reading from the device.
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//
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//
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// We start over any time a new value shows up, and
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// We start over any time a new value shows up, and
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// the follow-on isn't busy and can take it. Likewise,
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// the follow-on isn't busy and can take it. Likewise,
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// we reset the writer on the compression any time a
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// we reset the writer on the compression any time a
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// i_clr value comes through (i.e., ~i_cyc or new
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// i_clr value comes through (i.e., ~i_cyc or new
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// address)
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// address)
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wire w_accepted;
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wire w_accepted;
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assign w_accepted = (a_stb)&&(~i_busy);
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assign w_accepted = (a_stb)&&(~i_busy);
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reg r_stb;
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reg r_stb;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_stb <= a_stb;
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r_stb <= a_stb;
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/*
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reg [35:0] r_word;
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always @(posedge i_clk)
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if (a_stb)
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r_word <= a_addrword;
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*/
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wire [35:0] r_word;
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wire [35:0] r_word;
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assign r_word = a_addrword;
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assign r_word = a_addrword;
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//
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//
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// First step of the compression is keeping track of a compression
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// First step of the compression is keeping track of a compression
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// table. And the first part of that is keeping track of what address
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// table. And the first part of that is keeping track of what address
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// to write into the compression table, and whether or not the entire
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// to write into the compression table, and whether or not the entire
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// table is full or not. This logic follows:
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// table is full or not. This logic follows:
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//
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//
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reg [(TBITS-1):0] tbl_addr;
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reg [(TBITS-1):0] tbl_addr;
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reg r_compressed, tbl_filled;
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reg r_compressed, tbl_filled;
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// First part, write the compression table
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// First part, write the compression table
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always @(posedge i_clk)
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always @(posedge i_clk)
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// If we send a new address, then reset the table to empty
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// If we send a new address, then reset the table to empty
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if (w_accepted)
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if (w_accepted)
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begin
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begin
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// Reset on new address (0010xx) and on new compressed
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// Reset on new address (0010xx) and on new compressed
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// addresses (0011ll).
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// addresses (0011ll).
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if (o_cword[35:33]==3'h1)
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if (o_cword[35:33]==3'h1)
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tbl_addr <= 0;
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tbl_addr <= 0;
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// Otherwise, on any valid return result that wasn't
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// Otherwise, on any valid return result that wasn't
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// from our table, for whatever reason (such as didn't
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// from our table, for whatever reason (such as didn't
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// have the clocks to find it, etc.), increment the
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// have the clocks to find it, etc.), increment the
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// address to add another value into our table
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// address to add another value into our table
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else if (o_cword[35:33] == 3'b111)
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else if (o_cword[35:33] == 3'b111)
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tbl_addr <= tbl_addr + {{(TBITS-1){1'b0}},1'b1};
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tbl_addr <= tbl_addr + {{(TBITS-1){1'b0}},1'b1};
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((w_accepted)&&(o_cword[35:33]==3'h1)) // on new address
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if ((w_accepted)&&(o_cword[35:33]==3'h1)) // on new address
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tbl_filled <= 1'b0;
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tbl_filled <= 1'b0;
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else if (tbl_addr == 10'h3ff)
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else if (tbl_addr == 10'h3ff)
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tbl_filled <= 1'b1;
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tbl_filled <= 1'b1;
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// Now that we know where we are writing into the table, and what
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// Now that we know where we are writing into the table, and what
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// values of the table are valid, we need to actually write into
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// values of the table are valid, we need to actually write into
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// the table.
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// the table.
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//
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//
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// We can keep this logic really simple by writing on every clock
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// We can keep this logic really simple by writing on every clock
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// and writing junk on many of those clocks, but we'll need to remember
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// and writing junk on many of those clocks, but we'll need to remember
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// that the value of the table at tbl_addr is unreliable until tbl_addr
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// that the value of the table at tbl_addr is unreliable until tbl_addr
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// changes.
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// changes.
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//
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//
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reg [31:0] compression_tbl [0:((1<<TBITS)-1)];
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reg [31:0] compression_tbl [0:((1<<TBITS)-1)];
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// Write new values into the table
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// Write new values into the table
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always @(posedge i_clk)
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always @(posedge i_clk)
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compression_tbl[tbl_addr] <= { r_word[32:31], r_word[29:0] };
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compression_tbl[tbl_addr] <= { r_word[32:31], r_word[29:0] };
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// Now that we have a working table, can we use it?
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// Now that we have a working table, can we use it?
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// On any new word, we'll start looking through our codewords.
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// On any new word, we'll start looking through our codewords.
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// If we find any that matches, we're there. We might (or might not)
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// If we find any that matches, we're there. We might (or might not)
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// make it through the table first. That's irrelevant. We just look
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// make it through the table first. That's irrelevant. We just look
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// while we can.
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// while we can.
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reg [(TBITS-1):0] rd_addr;
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reg [(TBITS-1):0] rd_addr;
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wire [(TBITS-1):0] nxt_rd_addr;
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wire [(TBITS-1):0] nxt_rd_addr;
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assign nxt_rd_addr = rd_addr - { {(TBITS-1){1'b0}}, 1'b1 };
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assign nxt_rd_addr = rd_addr - { {(TBITS-1){1'b0}}, 1'b1 };
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initial rd_addr = 0;
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initial rd_addr = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((w_accepted)||(~a_stb))
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if ((w_accepted)||(~a_stb))
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// Keep in mind, if a write was just accepted, then
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// Keep in mind, if a write was just accepted, then
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// rd_addr will need to be reset on the next clock
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// rd_addr will need to be reset on the next clock
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// when (~a_stb). Hence this must be a two clock
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// when (~a_stb). Hence this must be a two clock
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// update
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// update
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rd_addr <= tbl_addr + {(TBITS){1'b1}};
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rd_addr <= tbl_addr + {(TBITS){1'b1}};
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else if ((nxt_rd_addr != tbl_addr)&&(~match)
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else if ((nxt_rd_addr != tbl_addr)&&(~match)
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&&((~nxt_rd_addr[TBITS-1])||(tbl_filled)))
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&&((~nxt_rd_addr[TBITS-1])||(tbl_filled)))
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rd_addr <= nxt_rd_addr;
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rd_addr <= nxt_rd_addr;
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reg [(DW-1):0] cword;
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reg [(DW-1):0] cword;
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reg [(TBITS-1):0] caddr;
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reg [(TBITS-1):0] caddr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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cword <= compression_tbl[rd_addr];
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cword <= compression_tbl[rd_addr];
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caddr <= rd_addr;
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caddr <= rd_addr;
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end
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end
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reg match;
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reg match;
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reg [9:0] matchaddr;
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reg [9:0] matchaddr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if((w_accepted)||(~a_stb)||(~r_stb))// Reset upon any write
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if((w_accepted)||(~a_stb)||(~r_stb))// Reset upon any write
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match <= 1'b0;
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match <= 1'b0;
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else if (~match)
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else if (~match)
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begin
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begin
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// To be a match, the table must not be empty,
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// To be a match, the table must not be empty,
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match <= (({1'b0, caddr } < {tbl_filled, tbl_addr}))
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match <= (({1'b0, caddr } < {tbl_filled, tbl_addr}))
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// the word we are matching to must be
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// the word we are matching to must be
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// in the form of a read command
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// in the form of a read command
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&&(r_word[35:33] == 3'b111)
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&&(r_word[35:33] == 3'b111)
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// And the word in the table must be
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// And the word in the table must be
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// identical to the word we are about
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// identical to the word we are about
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// to send.
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// to send.
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&&(cword == { r_word[32:31], r_word[29:0] });
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&&(cword == { r_word[32:31], r_word[29:0] });
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matchaddr <= tbl_addr-caddr;
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matchaddr <= tbl_addr-caddr;
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end
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end
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// Did we find something?
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// Did we find something?
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wire [(TBITS-1):0] adr_diff;
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wire [(TBITS-1):0] adr_diff;
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wire [9:0] adr_dbld;
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wire [9:0] adr_dbld;
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wire [2:0] adr_hlfd;
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wire [2:0] adr_hlfd;
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assign adr_diff = matchaddr;
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assign adr_diff = matchaddr;
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assign adr_hlfd = matchaddr[2:0]- 3'd2;
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assign adr_hlfd = matchaddr[2:0]- 3'd2;
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assign adr_dbld = matchaddr- 10'd10;
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assign adr_dbld = matchaddr- 10'd10;
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initial r_compressed = 1'b0;
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initial r_compressed = 1'b0;
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reg [(CW-1):0] r_cword; // Record our result
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reg [(CW-1):0] r_cword; // Record our result
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((~a_stb)||(~r_stb)||(w_accepted))//Reset whenever word gets written
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if ((~a_stb)||(~r_stb)||(w_accepted))//Reset whenever word gets written
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r_compressed <= 1'b0; // to our output
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r_compressed <= 1'b0; // to our output
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else if (r_compressed)//Already compressed, wait 'til sent
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else if (r_compressed)//Already compressed, wait 'til sent
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;
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;
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else if ((match)&&(matchaddr < 10'd521)&&(r_word == a_addrword))
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else if ((match)&&(matchaddr < 10'd521))
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begin
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begin
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if (matchaddr == 10'h1)
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if (matchaddr == 10'h1)
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r_cword[35:30] <= { 5'h3, r_word[30] };
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r_cword[35:30] <= { 5'h3, r_word[30] };
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else if (adr_diff < 10'd10)
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else if (adr_diff < 10'd10)
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r_cword[35:30] <= { 2'b10, adr_hlfd, r_word[30] };
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r_cword[35:30] <= { 2'b10, adr_hlfd, r_word[30] };
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else // if (adr_diff < 10'd521)
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else // if (adr_diff < 10'd521)
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r_cword[35:24] <= { 2'b01, adr_dbld[8:6],
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r_cword[35:24] <= { 2'b01, adr_dbld[8:6],
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r_word[30], adr_dbld[5:0] };
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r_word[30], adr_dbld[5:0] };
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r_compressed <= 1'b1;
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r_compressed <= 1'b1;
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end else
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end else
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r_cword <= r_word;
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r_cword <= r_word;
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end
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end
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// Can we do this without a clock delay?
|
// Can we do this without a clock delay?
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assign o_stb = a_stb;
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assign o_stb = a_stb;
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assign o_cword = (r_compressed)?(r_cword):(a_addrword);
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assign o_cword = (r_compressed)?(r_cword):(a_addrword);
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endmodule
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endmodule
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