////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbudecompress.v
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// Filename: wbudecompress.v
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//
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//
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// Project: XuLA2 board
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// Project: FPGA library
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//
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//
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// Purpose: Compression via this interface is simply a lookup table.
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// Purpose: Compression via this interface is simply a lookup table.
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// When writing, if requested, rather than writing a new 36-bit
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// When writing, if requested, rather than writing a new 36-bit
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// word, we may be asked to repeat a word that's been written recently.
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// word, we may be asked to repeat a word that's been written recently.
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// That's the goal of this routine: if given a word's (relative) address
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// That's the goal of this routine: if given a word's (relative) address
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// in the write stream, we use that address, else we expect a full 32-bit
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// in the write stream, we use that address, else we expect a full 32-bit
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// word to come in to be written.
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// word to come in to be written.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module wbudecompress(i_clk, i_stb, i_word, o_stb, o_word);
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module wbudecompress(i_clk, i_stb, i_word, o_stb, o_word);
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input i_clk, i_stb;
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input i_clk, i_stb;
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input [35:0] i_word;
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input [35:0] i_word;
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output reg o_stb;
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output reg o_stb;
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output reg [35:0] o_word;
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output reg [35:0] o_word;
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// Clock zero
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// Clock zero
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// { o_stb, r_stb } = 0
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// { o_stb, r_stb } = 0
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wire cmd_write_not_compressed = (i_word[35:33] == 3'h3);
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wire cmd_write_not_compressed = (i_word[35:33] == 3'h3);
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// Clock one: { o_stb, r_stb } = 4'h1 when done
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// Clock one: { o_stb, r_stb } = 4'h1 when done
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reg [7:0] wr_addr;
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reg [7:0] wr_addr;
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initial wr_addr = 8'h0;
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initial wr_addr = 8'h0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_stb)&&(cmd_write_not_compressed))
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if ((i_stb)&&(cmd_write_not_compressed))
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wr_addr <= wr_addr + 8'h1;
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wr_addr <= wr_addr + 8'h1;
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reg [31:0] compression_tbl [0:255];
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reg [31:0] compression_tbl [0:255];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_stb)
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if (i_stb)
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compression_tbl[wr_addr] <= { i_word[32:31], i_word[29:0] };
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compression_tbl[wr_addr] <= { i_word[32:31], i_word[29:0] };
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reg [35:0] r_word;
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reg [35:0] r_word;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_stb)
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if (i_stb)
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r_word <= i_word;
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r_word <= i_word;
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// Clock two, calculate the table address ... 1 is the smallest address
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// Clock two, calculate the table address ... 1 is the smallest address
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// { o_stb, r_stb } = 4'h2 when done
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// { o_stb, r_stb } = 4'h2 when done
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reg [7:0] cmd_addr;
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reg [7:0] cmd_addr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_addr = wr_addr - { r_word[32:31], r_word[29:24] };
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cmd_addr = wr_addr - { r_word[32:31], r_word[29:24] };
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// Let's also calculate the address, in case this is a compressed
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// Let's also calculate the address, in case this is a compressed
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// address word
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// address word
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reg [24:0] r_addr;
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reg [24:0] r_addr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(r_word[32:30])
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case(r_word[32:30])
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3'b000: r_addr <= { 19'h0, r_word[29:24] };
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3'b000: r_addr <= { 19'h0, r_word[29:24] };
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3'b010: r_addr <= { 13'h0, r_word[29:18] };
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3'b010: r_addr <= { 13'h0, r_word[29:18] };
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3'b100: r_addr <= { 7'h0, r_word[29:12] };
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3'b100: r_addr <= { 7'h0, r_word[29:12] };
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3'b110: r_addr <= { 1'h0, r_word[29: 6] };
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3'b110: r_addr <= { 1'h0, r_word[29: 6] };
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3'b001: r_addr <= { {(19){ r_word[29]}}, r_word[29:24] };
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3'b001: r_addr <= { {(19){ r_word[29]}}, r_word[29:24] };
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3'b011: r_addr <= { {(13){ r_word[29]}}, r_word[29:18] };
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3'b011: r_addr <= { {(13){ r_word[29]}}, r_word[29:18] };
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3'b101: r_addr <= { {( 7){ r_word[29]}}, r_word[29:12] };
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3'b101: r_addr <= { {( 7){ r_word[29]}}, r_word[29:12] };
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3'b111: r_addr <= { {( 1){ r_word[29]}}, r_word[29: 6] };
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3'b111: r_addr <= { {( 1){ r_word[29]}}, r_word[29: 6] };
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endcase
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endcase
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wire [31:0] w_addr;
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wire [31:0] w_addr;
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assign w_addr = { {(7){r_addr[24]}}, r_addr };
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assign w_addr = { {(7){r_addr[24]}}, r_addr };
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reg [9:0] rd_len;
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reg [9:0] rd_len;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~r_word[34])
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if (~r_word[34])
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rd_len <= 10'h01 + { 6'h00, r_word[33:31] };
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rd_len <= 10'h01 + { 6'h00, r_word[33:31] };
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else
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else
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rd_len <= 10'h08 + { 1'b0, r_word[33:31], r_word[29:24] };
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rd_len <= 10'h09 + { 1'b0, r_word[33:31], r_word[29:24] };
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// Clock three, read the table value
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// Clock three, read the table value
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// { o_stb, r_stb } = 4'h4 when done
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// { o_stb, r_stb } = 4'h4 when done
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// Maintaining ...
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// Maintaining ...
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// r_word (clock 1)
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// r_word (clock 1)
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// r_addr, rd_len (clock 2)
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// r_addr, rd_len (clock 2)
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reg [31:0] cword;
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reg [31:0] cword;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cword <= compression_tbl[cmd_addr];
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cword <= compression_tbl[cmd_addr];
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// Pipeline the strobe signal to create an output strobe, 3 clocks later
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// Pipeline the strobe signal to create an output strobe, 3 clocks later
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reg [2:0] r_stb;
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reg [2:0] r_stb;
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initial r_stb = 0;
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initial r_stb = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_stb <= { r_stb[1:0], i_stb };
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r_stb <= { r_stb[1:0], i_stb };
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// Clock four, now that the table value is valid, let's set our output
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// Clock four, now that the table value is valid, let's set our output
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// word.
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// word.
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// { o_stb, r_stb } = 4'h8 when done
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// { o_stb, r_stb } = 4'h8 when done
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_stb <= r_stb[2];
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o_stb <= r_stb[2];
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// Maintaining ...
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// Maintaining ...
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// r_word (clock 1)
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// r_word (clock 1)
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// r_addr, rd_len (clock 2)
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// r_addr, rd_len (clock 2)
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// cword (clock 3)
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// cword (clock 3)
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// Any/all of these can be pipelined for faster operation
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// Any/all of these can be pipelined for faster operation
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// However, speed is really limited by the speed of the I/O port. At
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// However, speed is really limited by the speed of the I/O port. At
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// it's fastest, it's 1 bit per clock, 48 clocks per codeword therefore,
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// it's fastest, it's 1 bit per clock, 48 clocks per codeword therefore,
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// thus ... things will hold still for much longer than just 5 clocks.
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// thus ... things will hold still for much longer than just 5 clocks.
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (r_word[35:30] == 6'b101110)
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if (r_word[35:30] == 6'b101110)
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o_word <= r_word;
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o_word <= r_word;
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else casez(r_word[35:30])
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else casez(r_word[35:30])
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// Set address from something compressed ... unsigned
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// Set address from something compressed ... unsigned
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6'b001??0: o_word <= { 4'h0, w_addr[31:0] };
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6'b001??0: o_word <= { 4'h0, w_addr[31:0] };
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// Set a new address as a signed offset from the last (set) one
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// Set a new address as a signed offset from the last (set) one
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// (The last address is kept further down the chain,
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// (The last address is kept further down the chain,
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// we just mark here that the address is to be set
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// we just mark here that the address is to be set
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// relative to it, and by how much.)
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// relative to it, and by how much.)
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6'b001??1: o_word <= { 3'h1, w_addr[31:30], 1'b1, w_addr[29:0]};
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6'b001??1: o_word <= { 3'h1, w_addr[31:30], 1'b1, w_addr[29:0]};
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// Write a value to the bus, with the value given from our
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// Write a value to the bus, with the value given from our
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// codeword table
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// codeword table
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6'b010???: o_word <=
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6'b010???: o_word <=
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{ 3'h3, cword[31:30], r_word[30], cword[29:0] };
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{ 3'h3, cword[31:30], r_word[30], cword[29:0] };
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// Read, highly compressed length (1 word)
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// Read, highly compressed length (1 word)
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6'b10????: o_word <= { 5'b11000, r_word[30], 20'h00, rd_len };
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6'b10????: o_word <= { 5'b11000, r_word[30], 20'h00, rd_len };
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// Read, two word (3+9 bits) length
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// Read, two word (3+9 bits) length
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6'b11????: o_word <= { 5'b11000, r_word[30], 20'h00, rd_len };
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6'b11????: o_word <= { 5'b11000, r_word[30], 20'h00, rd_len };
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default: o_word <= r_word;
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default: o_word <= r_word;
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endcase
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endcase
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endmodule
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endmodule
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