////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbufifo.v
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// Filename: wbufifo.v
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//
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//
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// Project: XuLA2 board
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// Project: FPGA library
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//
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//
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// Purpose: This was once a FIFO for a UART ... but now it works as a
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// Purpose: This was once a FIFO for a UART ... but now it works as a
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// synchronous FIFO for JTAG-wishbone conversion 36-bit codewords.
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// synchronous FIFO for JTAG-wishbone conversion 36-bit codewords.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module wbufifo(i_clk, i_rst, i_wr, i_data, i_rd, o_data, o_empty_n, o_err);
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module wbufifo(i_clk, i_rst, i_wr, i_data, i_rd, o_data, o_empty_n, o_err);
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parameter BW=66, LGFLEN=10, FLEN=(1<<LGFLEN);
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parameter BW=66, LGFLEN=10, FLEN=(1<<LGFLEN);
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_wr;
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input i_wr;
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input [(BW-1):0] i_data;
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input [(BW-1):0] i_data;
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input i_rd;
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input i_rd;
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output reg [(BW-1):0] o_data;
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output reg [(BW-1):0] o_data;
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output reg o_empty_n;
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output reg o_empty_n;
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output wire o_err;
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output wire o_err;
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reg [(BW-1):0] fifo[0:(FLEN-1)];
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reg [(BW-1):0] fifo[0:(FLEN-1)];
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reg [(LGFLEN-1):0] r_first, r_last;
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reg [(LGFLEN-1):0] r_first, r_last;
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reg will_overflow;
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reg will_overflow;
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initial will_overflow = 1'b0;
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initial will_overflow = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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will_overflow <= 1'b0;
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will_overflow <= 1'b0;
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else if (i_rd)
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else if (i_rd)
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will_overflow <= (will_overflow)&&(i_wr);
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will_overflow <= (will_overflow)&&(i_wr);
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else if (i_wr)
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else if (i_wr)
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will_overflow <= (r_first+2 == r_last);
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will_overflow <= (r_first+2 == r_last);
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else if (r_first+1 == r_last)
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else if (r_first+1 == r_last)
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will_overflow <= 1'b1;
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will_overflow <= 1'b1;
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// Write
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// Write
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initial r_first = 0;
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initial r_first = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_first <= { (LGFLEN){1'b0} };
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r_first <= { (LGFLEN){1'b0} };
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else if (i_wr)
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else if (i_wr)
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begin // Cowardly refuse to overflow
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begin // Cowardly refuse to overflow
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if ((i_rd)||(~will_overflow)) // (r_first+1 != r_last)
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if ((i_rd)||(~will_overflow)) // (r_first+1 != r_last)
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r_first <= r_first+{{(LGFLEN-1){1'b0}},1'b1};
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r_first <= r_first+{{(LGFLEN-1){1'b0}},1'b1};
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// else o_ovfl <= 1'b1;
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// else o_ovfl <= 1'b1;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wr) // Write our new value regardless--on overflow or not
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if (i_wr) // Write our new value regardless--on overflow or not
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fifo[r_first] <= i_data;
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fifo[r_first] <= i_data;
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// Reads
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// Reads
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// Following a read, the next sample will be available on the
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// Following a read, the next sample will be available on the
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// next clock
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// next clock
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// Clock ReadCMD ReadAddr Output
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// Clock ReadCMD ReadAddr Output
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// 0 0 0 fifo[0]
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// 0 0 0 fifo[0]
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// 1 1 0 fifo[0]
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// 1 1 0 fifo[0]
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// 2 0 1 fifo[1]
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// 2 0 1 fifo[1]
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// 3 0 1 fifo[1]
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// 3 0 1 fifo[1]
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// 4 1 1 fifo[1]
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// 4 1 1 fifo[1]
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// 5 1 2 fifo[2]
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// 5 1 2 fifo[2]
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// 6 0 3 fifo[3]
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// 6 0 3 fifo[3]
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// 7 0 3 fifo[3]
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// 7 0 3 fifo[3]
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reg will_underflow;
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reg will_underflow;
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initial will_underflow = 1'b0;
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initial will_underflow = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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will_underflow <= 1'b0;
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will_underflow <= 1'b0;
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else if (i_wr)
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else if (i_wr)
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will_underflow <= (will_underflow)&&(i_rd);
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will_underflow <= (will_underflow)&&(i_rd);
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else if (i_rd)
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else if (i_rd)
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will_underflow <= (r_last+1==r_first);
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will_underflow <= (r_last+1==r_first);
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else
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else
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will_underflow <= (r_last == r_first);
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will_underflow <= (r_last == r_first);
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initial r_last = 0;
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initial r_last = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_last <= { (LGFLEN){1'b0} };
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r_last <= { (LGFLEN){1'b0} };
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else if (i_rd)
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else if (i_rd)
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begin
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begin
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if ((i_wr)||(~will_underflow)) // (r_first != r_last)
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if ((i_wr)||(~will_underflow)) // (r_first != r_last)
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r_last <= r_last+{{(LGFLEN-1){1'b0}},1'b1};
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r_last <= r_last+{{(LGFLEN-1){1'b0}},1'b1};
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// Last chases first
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// Last chases first
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// Need to be prepared for a possible two
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// Need to be prepared for a possible two
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// reads in quick succession
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// reads in quick succession
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// o_data <= fifo[r_last+1];
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// o_data <= fifo[r_last+1];
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// else o_unfl <= 1'b1;
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// else o_unfl <= 1'b1;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_data <= fifo[(i_rd)?(r_last+{{(LGFLEN-1){1'b0}},1'b1})
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o_data <= fifo[(i_rd)?(r_last+{{(LGFLEN-1){1'b0}},1'b1})
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:(r_last)];
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:(r_last)];
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wire [(LGFLEN-1):0] nxt_first;
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wire [(LGFLEN-1):0] nxt_first;
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assign nxt_first = r_first+{{(LGFLEN-1){1'b0}},1'b1};
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assign nxt_first = r_first+{{(LGFLEN-1){1'b0}},1'b1};
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assign o_err = ((i_wr)&&(will_overflow)&&(~i_rd))
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assign o_err = ((i_wr)&&(will_overflow)&&(~i_rd))
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||((i_rd)&&(will_underflow)&&(~i_wr));
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||((i_rd)&&(will_underflow)&&(~i_wr));
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// wire [(LGFLEN-1):0] fill;
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// wire [(LGFLEN-1):0] fill;
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// assign fill = (r_first-r_last);
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// assign fill = (r_first-r_last);
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wire [(LGFLEN-1):0] nxt_last;
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wire [(LGFLEN-1):0] nxt_last;
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assign nxt_last = r_last+{{(LGFLEN-1){1'b0}},1'b1};
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assign nxt_last = r_last+{{(LGFLEN-1){1'b0}},1'b1};
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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o_empty_n <= 1'b0;
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o_empty_n <= 1'b0;
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else
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else
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o_empty_n <= (~i_rd)&&(r_first != r_last)
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o_empty_n <= (~i_rd)&&(r_first != r_last)
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||(i_rd)&&(r_first != nxt_last);
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||(i_rd)&&(r_first != nxt_last);
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endmodule
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endmodule
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