////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbuoutput.v
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// Filename: wbuoutput.v
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//
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//
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// Project: XuLA2 board
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// Project: FPGA library
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//
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//
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// Purpose: Converts 36-bit codewords into bytes to be placed on the serial
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// Purpose: Converts 36-bit codewords into bytes to be placed on the serial
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// output port. The codewords themselves are the results of bus
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// output port. The codewords themselves are the results of bus
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// transactions, which are then (hopefully) compressed within here and
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// transactions, which are then (hopefully) compressed within here and
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// carefully arranged into "lines" for visual viewing (if necessary).
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// carefully arranged into "lines" for visual viewing (if necessary).
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module wbuoutput(i_clk, i_rst, i_stb, i_codword,
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module wbuoutput(i_clk, i_rst, i_stb, i_codword,
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i_wb_cyc, i_int, i_bus_busy,
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i_wb_cyc, i_int, i_bus_busy,
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o_stb, o_char, i_tx_busy, o_fifo_err);
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o_stb, o_char, i_tx_busy, o_fifo_err);
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_stb;
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input i_stb;
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input [35:0] i_codword;
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input [35:0] i_codword;
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// Not Idle indicators
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// Not Idle indicators
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input i_wb_cyc, i_int, i_bus_busy;
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input i_wb_cyc, i_int, i_bus_busy;
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// Outputs to our UART transmitter
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// Outputs to our UART transmitter
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output wire o_stb;
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output wire o_stb;
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output wire [7:0] o_char;
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output wire [7:0] o_char;
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// Miscellaneous I/O: UART transmitter busy, and fifo error
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// Miscellaneous I/O: UART transmitter busy, and fifo error
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input i_tx_busy;
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input i_tx_busy;
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output wire o_fifo_err;
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output wire o_fifo_err;
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wire fifo_rd, dw_busy, fifo_empty_n, fifo_err;
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wire fifo_rd, dw_busy, fifo_empty_n, fifo_err;
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wire [35:0] fifo_codword;
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wire [35:0] fifo_codword;
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wire cw_stb, cw_busy, cp_stb, dw_stb, ln_stb, ln_busy,
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wire cw_stb, cw_busy, cp_stb, dw_stb, ln_stb, ln_busy,
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cp_busy, byte_busy;
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cp_busy, byte_busy;
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wire [35:0] cw_codword, cp_word;
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wire [35:0] cw_codword, cp_word;
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wire [6:0] dw_bits, ln_bits;
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wire [6:0] dw_bits, ln_bits;
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// `define SKIP_FIFO
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// `define SKIP_FIFO
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`ifdef SKIP_FIFO
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`ifdef SKIP_FIFO
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assign fifo_rd = i_stb;
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assign fifo_rd = i_stb;
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assign fifo_codword = i_codword;
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assign fifo_codword = i_codword;
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assign fifo_err = 1'b0;
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assign fifo_err = 1'b0;
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`else
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`else
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assign fifo_rd = (fifo_empty_n)&&(~cw_busy);
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assign fifo_rd = (fifo_empty_n)&&(~cw_busy);
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wbufifo #(36,10) busoutfifo(i_clk, i_rst, i_stb, i_codword,
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wbufifo #(36,10) busoutfifo(i_clk, i_rst, i_stb, i_codword,
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fifo_rd, fifo_codword, fifo_empty_n,
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fifo_rd, fifo_codword, fifo_empty_n,
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fifo_err);
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fifo_err);
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`endif
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`endif
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assign o_fifo_err = fifo_err;
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assign o_fifo_err = fifo_err;
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wbuidleint buildcw(i_clk, fifo_rd, fifo_codword,
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wbuidleint buildcw(i_clk, fifo_rd, fifo_codword,
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i_wb_cyc, i_bus_busy, i_int,
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i_wb_cyc, i_bus_busy, i_int,
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cw_stb, cw_codword, cw_busy, cp_busy);
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cw_stb, cw_codword, cw_busy, cp_busy);
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// assign o_dbg = dw_busy; // Always asserted ... ???
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// assign o_dbg = dw_busy; // Always asserted ... ???
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// assign o_dbg = { dw_busy, ln_busy, fifo_rd };
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// assign o_dbg = { dw_busy, ln_busy, fifo_rd };
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// Stuck: dw_busy and ln_busy get stuck high after read attempt,
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// Stuck: dw_busy and ln_busy get stuck high after read attempt,
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// fifo_rd is low
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// fifo_rd is low
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// assign o_dbg = { fifo_rd, cp_stb, cw_stb };
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// assign o_dbg = { fifo_rd, cp_stb, cw_stb };
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// cw_stb and cp_stb get stuck high after one read
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// cw_stb and cp_stb get stuck high after one read
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//
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//
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// cw_busy & cw_stb, not cp_stb, but dw_busy
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// cw_busy & cw_stb, not cp_stb, but dw_busy
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//
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//
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// `define SKIP_COMPRESS
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// `define SKIP_COMPRESS
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`ifdef SKIP_COMPRESS
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`ifdef SKIP_COMPRESS
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assign cp_stb = cw_stb;
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assign cp_stb = cw_stb;
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assign cp_word = cw_codword;
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assign cp_word = cw_codword;
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assign cp_busy = dw_busy;
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assign cp_busy = dw_busy;
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`else
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`else
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assign cp_busy = cp_stb;
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assign cp_busy = cp_stb;
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wbucompress packit(i_clk, cw_stb, cw_codword,
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wbucompress packit(i_clk, cw_stb, cw_codword,
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cp_stb, cp_word, dw_busy);
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cp_stb, cp_word, dw_busy);
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`endif
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`endif
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wbudeword deword(i_clk, cp_stb, cp_word, ln_busy,
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wbudeword deword(i_clk, cp_stb, cp_word, ln_busy,
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dw_stb, dw_bits, dw_busy);
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dw_stb, dw_bits, dw_busy);
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wbucompactlines linepacker(i_clk, dw_stb, dw_bits,
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wbucompactlines linepacker(i_clk, dw_stb, dw_bits,
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ln_stb, ln_bits,
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ln_stb, ln_bits,
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(i_wb_cyc||i_bus_busy||fifo_empty_n||cw_busy),
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(i_wb_cyc||i_bus_busy||fifo_empty_n||cw_busy),
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byte_busy, ln_busy);
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byte_busy, ln_busy);
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wbusixchar mkbytes(i_clk, ln_stb, ln_bits, o_stb, o_char, byte_busy, i_tx_busy);
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wbusixchar mkbytes(i_clk, ln_stb, ln_bits, o_stb, o_char, byte_busy, i_tx_busy);
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endmodule
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endmodule
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