////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: regdefs.h
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// Filename: regdefs.h
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//
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//
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// Project: XuLA2 board
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// Project: XuLA2 board
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#ifndef REGDEFS_H
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#ifndef REGDEFS_H
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#define REGDEFS_H
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#define REGDEFS_H
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// #define R_RESET 0x00000100
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// #define R_RESET 0x00000100
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// #define R_STATUS 0x00000101
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// #define R_STATUS 0x00000101
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// #define R_CONTROL 0x00000101
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// #define R_CONTROL 0x00000101
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#define R_VERSION 0x00000101
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#define R_VERSION 0x00000101
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#define R_ICONTROL 0x00000102
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#define R_ICONTROL 0x00000102
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#define R_BUSERR 0x00000103
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#define R_BUSERR 0x00000103
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#define R_ITIMER 0x00000104
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#define R_ITIMER 0x00000104
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#define R_DATE 0x00000105
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#define R_DATE 0x00000105
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#define R_GPIO 0x00000106
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#define R_GPIO 0x00000106
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#define R_UART_CTRL 0x00000107
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#define R_UART_CTRL 0x00000107
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#define R_PWM_DATA 0x00000108
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#define R_PWM_DATA 0x00000108
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#define R_PWM_INTERVAL 0x00000109
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#define R_PWM_INTERVAL 0x00000109
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#define R_UART_RX 0x0000010a
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#define R_UART_RX 0x0000010a
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#define R_UART_TX 0x0000010b
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#define R_UART_TX 0x0000010b
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#define R_SPIF_EREG 0x0000010c
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#define R_SPIF_EREG 0x0000010c
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#define R_SPIF_CREG 0x0000010d
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#define R_SPIF_CREG 0x0000010d
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#define R_SPIF_SREG 0x0000010e
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#define R_SPIF_SREG 0x0000010e
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#define R_SPIF_IDREG 0x0000010f
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#define R_SPIF_IDREG 0x0000010f
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#define R_CLOCK 0x00000110
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#define R_CLOCK 0x00000110
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#define R_TIMER 0x00000111
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#define R_TIMER 0x00000111
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#define R_STOPWATCH 0x00000112
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#define R_STOPWATCH 0x00000112
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#define R_CKALARM 0x00000113
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#define R_CKALARM 0x00000113
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#define R_CKSPEED 0x00000114
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#define R_CKSPEED 0x00000114
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// And because the flash driver needs these constants defined ...
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// And because the flash driver needs these constants defined ...
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#define R_QSPI_EREG 0x0000010c
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#define R_QSPI_EREG 0x0000010c
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#define R_QSPI_CREG 0x0000010d
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#define R_QSPI_CREG 0x0000010d
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#define R_QSPI_SREG 0x0000010e
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#define R_QSPI_SREG 0x0000010e
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#define R_QSPI_IDREG 0x0000010f
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#define R_QSPI_IDREG 0x0000010f
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// GPS registers
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// GPS registers
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// 0x00000114
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// 0x00000114
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// 0x00000115
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// 0x00000115
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// 0x00000116
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// 0x00000116
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// 0x00000117
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// 0x00000117
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// WB Scope registers wb_addr[31:3]==30'h23, i.e. 46, 8c, 118
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// WB Scope registers wb_addr[31:3]==30'h23, i.e. 46, 8c, 118
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#define R_QSCOPE 0x00000118 // Quad SPI scope ctrl
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#define R_QSCOPE 0x00000118 // Quad SPI scope ctrl
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#define R_QSCOPED 0x00000119 // and data
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#define R_QSCOPED 0x00000119 // and data
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#define R_CFGSCOPE 0x0000011a // Configuration/ICAPE scope control
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#define R_CFGSCOPE 0x0000011a // Configuration/ICAPE scope control
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#define R_CFGSCOPED 0x0000011b // and data
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#define R_CFGSCOPED 0x0000011b // and data
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#define R_RAMSCOPE 0x0000011c // SDRAM scope control
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#define R_RAMSCOPE 0x0000011c // SDRAM scope control
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#define R_RAMSCOPED 0x0000011d // and data
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#define R_RAMSCOPED 0x0000011d // and data
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#define R_CPUSCOPE 0x0000011e // SDRAM scope control
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#define R_CPUSCOPE 0x0000011e // SDRAM scope control
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#define R_CPUSCOPED 0x0000011f // and data
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#define R_CPUSCOPED 0x0000011f // and data
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//
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//
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// SD Card
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// SD Card
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// 0x00000120
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#define R_SDCARD_CTRL 0x00000120
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// 0x00000121
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#define R_SDCARD_DATA 0x00000121
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// 0x00000122
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#define R_SDCARD_FIFOA 0x00000122
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// 0x00000123
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#define R_SDCARD_FIFOB 0x00000123
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//
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//
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// Unused/open
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// Unused/open
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// #define SOMETHING 0x00000124 -- 0x013f (28 spaces)
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// #define SOMETHING 0x00000124 -- 0x013f (28 spaces)
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//
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//
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// FPGA CONFIG/ICAP REGISTERS
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// FPGA CONFIG/ICAP REGISTERS
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#define R_CFG_CRC 0x00000140
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#define R_CFG_CRC 0x00000140
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#define R_CFG_FAR_MAJ 0x00000141
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#define R_CFG_FAR_MAJ 0x00000141
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#define R_CFG_FAR_MIN 0x00000142
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#define R_CFG_FAR_MIN 0x00000142
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#define R_CFG_FDRI 0x00000143
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#define R_CFG_FDRI 0x00000143
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#define R_CFG_FDRO 0x00000144
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#define R_CFG_FDRO 0x00000144
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#define R_CFG_CMD 0x00000145
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#define R_CFG_CMD 0x00000145
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#define R_CFG_CTL 0x00000146
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#define R_CFG_CTL 0x00000146
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#define R_CFG_MASK 0x00000147
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#define R_CFG_MASK 0x00000147
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#define R_CFG_STAT 0x00000148
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#define R_CFG_STAT 0x00000148
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#define R_CFG_LOUT 0x00000149
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#define R_CFG_LOUT 0x00000149
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#define R_CFG_COR1 0x0000014a
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#define R_CFG_COR1 0x0000014a
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#define R_CFG_COR2 0x0000014b
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#define R_CFG_COR2 0x0000014b
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#define R_CFG_PWRDN 0x0000014c
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#define R_CFG_PWRDN 0x0000014c
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#define R_CFG_FLR 0x0000014d
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#define R_CFG_FLR 0x0000014d
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#define R_CFG_IDCODE 0x0000014e
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#define R_CFG_IDCODE 0x0000014e
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#define R_CFG_CWDT 0x0000014f
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#define R_CFG_CWDT 0x0000014f
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#define R_CFG_HCOPT 0x00000150
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#define R_CFG_HCOPT 0x00000150
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#define R_CFG_CSBO 0x00000152
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#define R_CFG_CSBO 0x00000152
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#define R_CFG_GEN1 0x00000153
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#define R_CFG_GEN1 0x00000153
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#define R_CFG_GEN2 0x00000154
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#define R_CFG_GEN2 0x00000154
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#define R_CFG_GEN3 0x00000155
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#define R_CFG_GEN3 0x00000155
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#define R_CFG_GEN4 0x00000156
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#define R_CFG_GEN4 0x00000156
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#define R_CFG_GEN5 0x00000157
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#define R_CFG_GEN5 0x00000157
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#define R_CFG_MODE 0x00000158
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#define R_CFG_MODE 0x00000158
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#define R_CFG_GWE 0x00000159
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#define R_CFG_GWE 0x00000159
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#define R_CFG_GTS 0x0000015a
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#define R_CFG_GTS 0x0000015a
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#define R_CFG_MFWR 0x0000015b
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#define R_CFG_MFWR 0x0000015b
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#define R_CFG_CCLK 0x0000015c
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#define R_CFG_CCLK 0x0000015c
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#define R_CFG_SEU 0x0000015d
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#define R_CFG_SEU 0x0000015d
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#define R_CFG_EXP 0x0000015e
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#define R_CFG_EXP 0x0000015e
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#define R_CFG_RDBK 0x0000015f
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#define R_CFG_RDBK 0x0000015f
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#define R_CFG_BOOTSTS 0x00000160
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#define R_CFG_BOOTSTS 0x00000160
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#define R_CFG_EYE 0x00000161
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#define R_CFG_EYE 0x00000161
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#define R_CFG_CBC 0x00000162
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#define R_CFG_CBC 0x00000162
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// RAM memory space
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// RAM memory space
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#define RAMBASE 0x00002000
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#define RAMBASE 0x00002000
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#define MEMWORDS (1<<13)
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#define MEMWORDS (1<<13)
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// Flash memory space
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// Flash memory space
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#define SPIFLASH 0x00040000
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#define SPIFLASH 0x00040000
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#define FLASHWORDS (1<<18)
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#define FLASHWORDS (1<<18)
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// SDRAM memory space
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// SDRAM memory space
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#define SDRAMBASE 0x00800000
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#define SDRAMBASE 0x00800000
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#define SDRAMWORDS (1<<25)
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#define SDRAMWORDS (1<<25)
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// Zip CPU Control and Debug registers
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// Zip CPU Control and Debug registers
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#define R_ZIPCTRL 0x01000000
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#define R_ZIPCTRL 0x01000000
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#define R_ZIPDATA 0x01000001
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#define R_ZIPDATA 0x01000001
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// Interrupt control constants
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// Interrupt control constants
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#define GIE 0x80000000 // Enable all interrupts
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#define GIE 0x80000000 // Enable all interrupts
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#define SCOPEN 0x80080008 // Enable WBSCOPE interrupts
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#define SCOPEN 0x80080008 // Enable WBSCOPE interrupts
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#define ISPIF_EN 0x80040004 // Enable SPI Flash interrupts
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#define ISPIF_EN 0x80040004 // Enable SPI Flash interrupts
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#define ISPIF_DIS 0x00040000 // Disable SPI Flash interrupts
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#define ISPIF_DIS 0x00040000 // Disable SPI Flash interrupts
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#define ISPIF_CLR 0x00000004 // Clear pending SPI Flash interrupt
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#define ISPIF_CLR 0x00000004 // Clear pending SPI Flash interrupt
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// Flash control constants
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// Flash control constants
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#define ERASEFLAG 0x80000000
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#define ERASEFLAG 0x80000000
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#define DISABLEWP 0x10000000
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#define DISABLEWP 0x10000000
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#define SZPAGE 64
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#define SZPAGE 64
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#define PGLEN 64
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#define PGLEN 64
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#define NPAGES 32
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#define NPAGES 32
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#define SECTORSZ (NPAGES * SZPAGE)
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#define SECTORSZ (NPAGES * SZPAGE)
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#define NSECTORS 256
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#define NSECTORS 256
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#define SECTOROF(A) ((A) & (-1<<10))
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#define SECTOROF(A) ((A) & (-1<<10))
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#define PAGEOF(A) ((A) & (-1<<6))
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#define PAGEOF(A) ((A) & (-1<<6))
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#define RAMLEN 0x02000
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#define RAMLEN 0x02000
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// ZIP Control sequences
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// ZIP Control sequences
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#define CPU_GO 0x0000
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#define CPU_GO 0x0000
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#define CPU_RESET 0x0040
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#define CPU_RESET 0x0040
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#define CPU_INT 0x0080
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#define CPU_INT 0x0080
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#define CPU_STEP 0x0100
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#define CPU_STEP 0x0100
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#define CPU_STALL 0x0200
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#define CPU_STALL 0x0200
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#define CPU_HALT 0x0400
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#define CPU_HALT 0x0400
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#define CPU_CLRCACHE 0x0800
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#define CPU_CLRCACHE 0x0800
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#define CPU_sR0 (0x0000|CPU_HALT)
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#define CPU_sR0 (0x0000|CPU_HALT)
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#define CPU_sSP (0x000d|CPU_HALT)
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#define CPU_sSP (0x000d|CPU_HALT)
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#define CPU_sCC (0x000e|CPU_HALT)
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#define CPU_sCC (0x000e|CPU_HALT)
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#define CPU_sPC (0x000f|CPU_HALT)
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#define CPU_sPC (0x000f|CPU_HALT)
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#define CPU_uR0 (0x0010|CPU_HALT)
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#define CPU_uR0 (0x0010|CPU_HALT)
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#define CPU_uSP (0x001d|CPU_HALT)
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#define CPU_uSP (0x001d|CPU_HALT)
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#define CPU_uCC (0x001e|CPU_HALT)
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#define CPU_uCC (0x001e|CPU_HALT)
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#define CPU_uPC (0x001f|CPU_HALT)
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#define CPU_uPC (0x001f|CPU_HALT)
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// Scop definition/sequences
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// Scop definition/sequences
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#define SCOPE_NO_RESET 0x80000000
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#define SCOPE_NO_RESET 0x80000000
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#define SCOPE_TRIGGER (0x08000000|SCOPE_NO_RESET)
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#define SCOPE_TRIGGER (0x08000000|SCOPE_NO_RESET)
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#define SCOPE_DISABLE (0x04000000)
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#define SCOPE_DISABLE (0x04000000)
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typedef struct {
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typedef struct {
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unsigned m_addr;
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unsigned m_addr;
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const char *m_name;
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const char *m_name;
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} REGNAME;
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} REGNAME;
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extern const REGNAME *bregs;
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extern const REGNAME *bregs;
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extern const int NREGS;
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extern const int NREGS;
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// #define NREGS (sizeof(bregs)/sizeof(bregs[0]))
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// #define NREGS (sizeof(bregs)/sizeof(bregs[0]))
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extern unsigned addrdecode(const char *v);
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extern unsigned addrdecode(const char *v);
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extern const char *addrname(const unsigned v);
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extern const char *addrname(const unsigned v);
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#include "ttybus.h"
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#include "ttybus.h"
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// #include "portbus.h"
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// #include "portbus.h"
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typedef TTYBUS FPGA;
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typedef TTYBUS FPGA;
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#endif
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#endif
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