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---- ----
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---- ----
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---- Copyright Notice ----
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---- Copyright Notice ----
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---- ----
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---- ----
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---- This file is part of YAC - Yet Another CORDIC Core ----
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---- This file is part of YAC - Yet Another CORDIC Core ----
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---- Copyright (c) 2014, Author(s), All rights reserved. ----
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---- Copyright (c) 2014, Author(s), All rights reserved. ----
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---- ----
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---- ----
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---- YAC is free software; you can redistribute it and/or ----
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---- YAC is free software; you can redistribute it and/or ----
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---- modify it under the terms of the GNU Lesser General Public ----
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---- modify it under the terms of the GNU Lesser General Public ----
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---- License as published by the Free Software Foundation; either ----
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---- License as published by the Free Software Foundation; either ----
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---- version 3.0 of the License, or (at your option) any later version. ----
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---- version 3.0 of the License, or (at your option) any later version. ----
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---- ----
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---- ----
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---- YAC is distributed in the hope that it will be useful, ----
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---- YAC is distributed in the hope that it will be useful, ----
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---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
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---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
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---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----
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---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----
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---- Lesser General Public License for more details. ----
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---- Lesser General Public License for more details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General Public ----
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---- You should have received a copy of the GNU Lesser General Public ----
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---- License along with this library. If not, download it from ----
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---- License along with this library. If not, download it from ----
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---- http://www.gnu.org/licenses/lgpl ----
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---- http://www.gnu.org/licenses/lgpl ----
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---- ----
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---- ----
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<<<<<<< HEAD
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<<<<<<< HEAD
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<<<<<<< HEAD
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<<<<<<< HEAD
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=======
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>>>>>>> Updated C and RTL model as well as the documentation
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>>>>>>> Updated C and RTL model as well as the documentation
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Author(s): Christian Haettich
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Author(s): Christian Haettich
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Email feddischson@opencores.org
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Email feddischson@opencores.org
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Description
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Description
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CORDIC is the acronym for COordinate Rotation DIgital Computer and
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CORDIC is the acronym for COordinate Rotation DIgital Computer and
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allows a hardware efficient calculation of various functions
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allows a hardware efficient calculation of various functions
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like - atan, sin, cos - atanh, sinh, cosh, - division, multiplication.
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like - atan, sin, cos - atanh, sinh, cosh, - division, multiplication.
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Hardware efficient means, that only shifting, additions and
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Hardware efficient means, that only shifting, additions and
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subtractions in combination with table-lookup is required. This makes
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subtractions in combination with table-lookup is required. This makes
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it suitable for a realization in digital hardware. Good
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it suitable for a realization in digital hardware. Good
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introductions can be found in [1][2][3][5].
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introductions can be found in [1][2][3][5].
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The following six CORDIC modes are supported:
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The following six CORDIC modes are supported:
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- trigonometric rotation
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- trigonometric rotation
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- trigonometric vectoring
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- trigonometric vectoring
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- linear rotation
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- linear rotation
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- linear vectoring
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- linear vectoring
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- hyperbolic rotation
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- hyperbolic rotation
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- hyperbolic vectoring
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- hyperbolic vectoring
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Furthermore, the CORDIC algorithm is implemented for iterative
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Furthermore, the CORDIC algorithm is implemented for iterative
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processing which means, that the IP-core is started
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processing which means, that the IP-core is started
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with a set of input data and after a specific amount of
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with a set of input data and after a specific amount of
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clock cycles, the result is
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clock cycles, the result is
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available. No parallel data can be processed.
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available. No parallel data can be processed.
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In addition to an IP-core written in VHDL, a bit-accurate C-model
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In addition to an IP-core written in VHDL, a bit-accurate C-model
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is provided. This C-model can be compiled as mex for a usage with Octave or
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is provided. This C-model can be compiled as mex for a usage with Octave or
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Matlab. Therefore, this C-model allows a bit-accurate analysis
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Matlab. Therefore, this C-model allows a bit-accurate analysis
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of the CORDIC performance on a higher level.
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of the CORDIC performance on a higher level.
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For a more detailed documentation, see ./doc/documentation.pdf
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For a more detailed documentation, see ./doc/documentation.pdf
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Status
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Status
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- C-model implementation is done
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- C-model implementation is done
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- RTL model implementation is done
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- RTL model implementation is done
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- RTL model is verified against C-model
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- RTL model is verified against C-model
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- Wishbone-bus wrapper is added
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- Wishbone-bus wrapper is added
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- included into a small SoC, tested on a spartan-3 FPGA
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- Included into a small SoC, tested on a spartan-3 FPGA
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- Testing within an SOC is done (see ./test_sys)
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Next-Steps
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Next-Steps
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-----------------------
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-----------------------
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- Circuit optimizations
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- Circuit optimizations
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- Numerical optimizations
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- Numerical optimizations
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- Further testing within an SOC
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<<<<<<< HEAD
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<<<<<<< HEAD
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=======
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=======
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>>>>>>> initial commit
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>>>>>>> initial commit
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=======
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=======
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>>>>>>> Updated C and RTL model as well as the documentation
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>>>>>>> Updated C and RTL model as well as the documentation
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Files and folders:
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Files and folders:
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------------------
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./c_octave : contains a bit-accurate C-implementation of the YAC.
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./c_octave : contains a bit-accurate C-implementation of the YAC.
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This C-implementation is used for analyzing the performance
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This C-implementation is used for analyzing the performance
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and to generate RTL testbench stimulus
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and to generate RTL testbench stimulus
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(cordic_iterative_test.m).
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(cordic_iterative_test.m).
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The file cordic_iterative_code.m is used to create some
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The file cordic_iterative_code.m is used to create some
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VHDL/C-code automatically.
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VHDL/C-code automatically.
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./rtl/vhdl : Contains the VHDL implementation files
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./rtl/vhdl : Contains the VHDL implementation files
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./doc : Will contain a detailed documentation in future.
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./doc : Will contain a detailed documentation in future.
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./test_sys : Contains a test system to test the YAC on a spartan-3an board
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<<<<<<< HEAD
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<<<<<<< HEAD
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<<<<<<< HEAD
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<<<<<<< HEAD
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=======
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=======
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>>>>>>> Updated C and RTL model as well as the documentation
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>>>>>>> Updated C and RTL model as well as the documentation
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[1] Andraka, Ray; A survey of CORDIC algorithms for FPGA based computers, 1989
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[1] Andraka, Ray; A survey of CORDIC algorithms for FPGA based computers, 1989
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[2] Hu, Yu Hen; CORDIC-Based VLSI Architectures for Digital Signal Processing, 1992
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[2] Hu, Yu Hen; CORDIC-Based VLSI Architectures for Digital Signal Processing, 1992
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[3] CORDIC on wikibook: http://en.wikibooks.org/wiki/Digital_Circuits/CORDIC
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[3] CORDIC on wikibook: http://en.wikibooks.org/wiki/Digital_Circuits/CORDIC
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[4] CORDIC on wikipedia:http://en.wikipedia.org/wiki/CORDIC
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[4] CORDIC on wikipedia:http://en.wikipedia.org/wiki/CORDIC
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[5] David, Herbert; Meyr, Heinricht; CORDIC Algorithms and Architectures
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[5] David, Herbert; Meyr, Heinricht; CORDIC Algorithms and Architectures
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http://www.eecs.berkeley.edu/newton/Classes/EE290sp99/lectures/ee290aSp996_1/cordic_chap24.pdf
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http://www.eecs.berkeley.edu/newton/Classes/EE290sp99/lectures/ee290aSp996_1/cordic_chap24.pdf
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<<<<<<< HEAD
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<<<<<<< HEAD
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=======
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=======
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>>>>>>> initial commit
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>>>>>>> initial commit
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=======
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=======
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>>>>>>> Updated C and RTL model as well as the documentation
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>>>>>>> Updated C and RTL model as well as the documentation
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