//Apr.4.2005
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//Apr.4.2005
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//Test Bench for calculator using URAT ECHO BACK
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//Test Bench for calculator using URAT ECHO BACK
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`include "define.h"
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`include "define.h"
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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module yacc_test;
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module yacc_test;
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reg clock=0;
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reg clock=0;
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reg Reset=0;
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reg Reset=0;
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reg int_req_usr=0;
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reg int_req_usr=0;
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wire RXD;
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wire RXD;
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wire TXD=RXD;
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wire TXD=RXD;
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wire [31:0] mem_data_w;
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wire [31:0] mem_data_w;
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wire mem_write;
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wire mem_write;
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wire [15:0] mem_address;
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wire [15:0] mem_address;
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always #10 clock=~clock;
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always #10 clock=~clock;
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initial begin
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initial begin
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Reset=0;
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Reset=0;
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#800 Reset=1;
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#800 Reset=1;
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end
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end
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`ifdef RTL_SIMULATION
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`ifdef RTL_SIMULATION
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yacc cpu(.clock(clock),.Async_Reset(Reset),.MemoryWData(mem_data_w),
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yacc cpu(.clock(clock),.Async_Reset(Reset),.MemoryWData(mem_data_w),
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.MWriteFF(mem_write),
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.MWriteFF(mem_write),
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.data_port_address(mem_address),.RXD(RXD),.TXD(TXD));
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.data_port_address(mem_address),.RXD(RXD),.TXD(TXD));
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`else
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`else
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yacc cpu(.clock(clock),.Async_Reset(Reset), .RXD(RXD),.TXD(TXD));
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yacc cpu(.clock(clock),.Async_Reset(Reset), .RXD(RXD),.TXD(TXD));
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`endif
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`endif
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task Cprint;// String OUT until the byte 00 or xx detected with least Byte first and justified.
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task Cprint;// String OUT until the byte 00 or xx detected with least Byte first and justified.
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integer i;
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integer i;
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begin :Block
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begin :Block
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i=0;
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i=0;
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while (1) begin
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while (1) begin
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if (char_buffer[i*8 +:8] ===8'h00 || char_buffer[i*8 +:8]===8'hxx) begin
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if (char_buffer[i*8 +:8] ===8'h00 || char_buffer[i*8 +:8]===8'hxx) begin
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disable Block;
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disable Block;
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end
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end
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$write("%c",char_buffer[i*8 +:8]);
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$write("%c",char_buffer[i*8 +:8]);
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i=i+1;
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i=i+1;
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end
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end
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end
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end
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endtask
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endtask
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reg [0:640*2-1] char_buffer;
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reg [0:640*2-1] char_buffer;
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integer counter=0;
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integer counter=0;
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always @ (posedge clock ) begin
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always @ (posedge clock ) begin
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if ((mem_write === 1'b1)) begin
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if ((mem_write === 1'b1)) begin
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// if (mem_data_w==32'h0101_0101) $stop;
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// if (mem_data_w==32'h0101_0101) $stop;
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if (mem_address==`Print_Port_Address) begin
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if (mem_address==`Print_Port_Address) begin
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if (mem_data_w[7:0]===8'h00) begin
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if (mem_data_w[7:0]===8'h00) begin
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char_buffer[counter*8 +:8]=mem_data_w[7:0];
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char_buffer[counter*8 +:8]=mem_data_w[7:0];
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if (char_buffer[0 +:8*7]==="$finish") begin
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if (char_buffer[0 +:8*7]==="$finish") begin
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$stop;
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$stop;
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end else if (char_buffer[0 +:8*5]==="$time") begin
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end else if (char_buffer[0 +:8*5]==="$time") begin
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$display("Current Time on Simulation=%d",$time);
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$display("Current Time on Simulation=%d",$time);
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end else Cprint;//$write("%s",char_buffer);
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end else Cprint;//$write("%s",char_buffer);
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for (counter=0; counter< 80*2; counter=counter+1) begin
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for (counter=0; counter< 80*2; counter=counter+1) begin
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char_buffer[counter*8 +:8]=8'h00;
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char_buffer[counter*8 +:8]=8'h00;
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end
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end
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counter=0;
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counter=0;
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end else begin
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end else begin
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char_buffer[counter*8 +:8]=mem_data_w[7:0];
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char_buffer[counter*8 +:8]=mem_data_w[7:0];
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counter=counter+1;
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counter=counter+1;
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end
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end
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end
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end
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else if (mem_address==`Print_CAHR_Port_Address) begin
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else if (mem_address==`Print_CAHR_Port_Address) begin
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$write("%h ",mem_data_w[7:0]);
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$write("%h ",mem_data_w[7:0]);
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end else if (mem_address==`Print_INT_Port_Address) begin
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end else if (mem_address==`Print_INT_Port_Address) begin
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$write("%h ",mem_data_w[15:0]);//Little Endian
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$write("%h ",mem_data_w[15:0]);//Little Endian
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end else if (mem_address==`Print_LONG_Port_Address) begin
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end else if (mem_address==`Print_LONG_Port_Address) begin
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$write("%h ",mem_data_w[31:0]);//Big Endian
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$write("%h ",mem_data_w[31:0]);//Big Endian
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end
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end
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end //if
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end //if
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end //always
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end //always
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//uart read port
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//uart read port
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wire [7:0] buffer_reg;
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wire [7:0] buffer_reg;
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wire int_req;
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wire int_req;
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reg sync_reset;
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reg sync_reset;
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localparam LF=8'h0a;
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localparam LF=8'h0a;
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always @(posedge clock, negedge Reset) begin
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always @(posedge clock, negedge Reset) begin
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if (!Reset) sync_reset <=1'b1;
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if (!Reset) sync_reset <=1'b1;
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else sync_reset<=1'b0;
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else sync_reset<=1'b0;
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end
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end
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`define DISABLE_HOST_UART_READ
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`define DISABLE_HOST_UART_READ
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`ifndef DISABLE_HOST_UART_READ
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`ifndef DISABLE_HOST_UART_READ
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uart_read uart_read_port( .sync_reset(sync_reset), .clk(clock), .rxd(TXD),.buffer_reg(buffer_reg), .int_req(int_req));
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uart_read uart_read_port( .sync_reset(sync_reset), .clk(clock), .rxd(TXD),.buffer_reg(buffer_reg), .int_req(int_req));
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always @(posedge int_req) begin
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always @(posedge int_req) begin
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begin :local
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begin :local
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reg [7:0] local_mem [0:1000];
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reg [7:0] local_mem [0:1000];
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integer i=0;
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integer i=0;
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if (i>=1000) $stop;//assert(0);
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if (i>=1000) $stop;//assert(0);
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if (buffer_reg==LF) begin :local2 //pop stack
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if (buffer_reg==LF) begin :local2 //pop stack
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integer j;
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integer j;
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j=0;
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j=0;
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while( j < i) begin
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while( j < i) begin
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$write( "%c",local_mem[j]);
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$write( "%c",local_mem[j]);
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j=j+1;
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j=j+1;
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end
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end
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$write(" : time=%t\n",$time);
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$write(" : time=%t\n",$time);
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i=0;//clear stack
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i=0;//clear stack
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end else begin//push stack
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end else begin//push stack
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local_mem[i]=buffer_reg;
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local_mem[i]=buffer_reg;
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i=i+1;
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i=i+1;
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end
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end
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end
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end
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end
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end
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`endif
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`endif
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endmodule
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endmodule
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