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<P><B>6 Post-Layout Gate Simulation</B><BR>
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<P><B>6 Post-Layout Gate Simulation</B><BR>
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<B>6.1 Spartan3 Gate Simulation</B><BR>
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<B>6.1 Spartan3 Gate Simulation</B><BR>
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<BR>
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<BR>
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Memory Collision Errors are frequently reported as follows. <BR>
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Memory Collision Errors are frequently reported as follows. <BR>
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</P>
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<P><IMG src="xilinx_gatesim2.png" width="783" height="734" border="0"><BR>
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<P><IMG src="xilinx_gatesim2.png" width="783" height="734" border="0"><BR>
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<BR>
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<BR>
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Since this messages are meaningless for YACC. I checked disable warning
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Since this messages are meaningless for YACC. I checked disable warning
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option in coregen generation. However situation was the same. There is
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option in coregen generation. However situation was the same. There is
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no help for it , I changed primitive description temporally as follows.<BR>
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no help for it , I changed primitive description temporally as follows.<BR>
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<BR>
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<BR>
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parameter
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parameter
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SIM_COLLISION_CHECK = "NONE";//All ORIG TAK
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SIM_COLLISION_CHECK = "NONE";//All ORIG TAK
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Apr.12.2005<BR>
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Apr.12.2005<BR>
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<BR>
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<BR>
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<BR>
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<BR>
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<IMG src="xilinx_gate_sim1.png" width="783" height="734" border="0"><BR>
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<IMG src="xilinx_gate_sim1.png" width="783" height="734" border="0"><BR>
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Note:<BR>
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Note:<BR>
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SDF Error Messages are due to transitional state of simulator at
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SDF Error Messages are due to transitional state of simulator at
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initial power on sequence.<BR>
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initial power on sequence.<BR>
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<BR>
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<BR>
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<BR>
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<BR>
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<BR>
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<BR>
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<BR>
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<BR>
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<B>6.2 Stratix2</B><BR>
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<B>6.2 Stratix2</B><BR>
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<BR>
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<BR>
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Run Test Bench at 165MHz.<BR>
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Run Test Bench at 165MHz.<BR>
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<IMG src="stratix2_gatesim.png" width="783" height="715" border="0"><BR>
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<IMG src="stratix2_gatesim.png" width="783" height="715" border="0"><BR>
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<BR>
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<BR>
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<BR>
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<BR>
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<B>6.3 Cyclone</B><BR>
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<B>6.3 Cyclone</B><BR>
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<BR>
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<BR>
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Run test bench at 104MHz<BR>
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Run test bench at 104MHz<BR>
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<IMG src="cyclone_gate_sim.png" width="783" height="715" border="0"></P>
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<IMG src="cyclone_gate_sim.png" width="783" height="715" border="0"></P>
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