//Jun.2.2004
|
//Jun.2.2004
|
//Jun.27.2004
|
//Jun.27.2004
|
//Jun.28.2004
|
//Jun.28.2004
|
//Jun.30.2004 mulfunc output bug fix
|
//Jun.30.2004 mulfunc output bug fix
|
// still 16x16 sign extension
|
// still 16x16 sign extension
|
//Jul.2.2004 mul 32x32=>64bit w/ w/o sign
|
//Jul.2.2004 mul 32x32=>64bit w/ w/o sign
|
//Jul.2.2004 address MUL_WIDTH==1
|
//Jul.2.2004 address MUL_WIDTH==1
|
//Jul.4.2004 input critical path : => add carry_ff;
|
//Jul.4.2004 input critical path : => add carry_ff;
|
//Jul.5.2004 :=> less fanout
|
//Jul.5.2004 :=> less fanout
|
//Jul.13.2004 signed mul bug fix
|
//Jul.13.2004 signed mul bug fix
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//Jul.15.2004 32/32 div
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//Jul.15.2004 32/32 div
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//Jul.16.2004 diet
|
//Jul.16.2004 diet
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//Jul.17.2004 add `ifdef less path delay for interface port
|
//Jul.17.2004 add `ifdef less path delay for interface port
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//Apr.7.2005 ADDRESS to XILINX Specific problem
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//Apr.7.2005 ADDRESS to XILINX Specific problem
|
//Apr.14.2005 Add Stratix2
|
//Apr.14.2005 Add Stratix2
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|
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// mul/div module
|
// mul/div module
|
|
|
// a[31:0] /b[31:0] =>
|
// a[31:0] /b[31:0] =>
|
// mul_div_out[15:0] <=a/b
|
// mul_div_out[15:0] <=a/b
|
// mul_div_out[31:16] <=a%b
|
// mul_div_out[31:16] <=a%b
|
// No detection of overflow
|
// No detection of overflow
|
// Algorithm
|
// Algorithm
|
// answer_reg = (answer_reg << 1);
|
// answer_reg = (answer_reg << 1);
|
// multout_reg<={sum,a_reg[31]};
|
// multout_reg<={sum,a_reg[31]};
|
// if (multout_reg >= b_reg) {
|
// if (multout_reg >= b_reg) {
|
// answer_reg += 1;
|
// answer_reg += 1;
|
// multout_reg -= b_reg;
|
// multout_reg -= b_reg;
|
// }
|
// }
|
// a_reg <= a_reg << 1;
|
// a_reg <= a_reg << 1;
|
`include "define.h"
|
`include "define.h"
|
module mul_div(clock,sync_reset,a,b,mul_div_out,mul_div_sign,mul_div_word,mul_div_mode,state,stop_state,mul_div_enable,lohi);
|
module mul_div(clock,sync_reset,a,b,mul_div_out,mul_div_sign,mul_div_word,mul_div_mode,state,stop_state,mul_div_enable,lohi);
|
`ifdef RAM4K
|
`ifdef RAM4K
|
|
|
`ifdef XILINX
|
`ifdef XILINX
|
parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
|
parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
|
// XILINX fails using ISE7.1 if MUL_WIDTH==1,2
|
// XILINX fails using ISE7.1 if MUL_WIDTH==1,2
|
// if MULWIDTH==1 synthesis is possible but post synthesis simulation fails
|
// if MULWIDTH==1 synthesis is possible but post synthesis simulation fails
|
// if MULWIDTH==2 synthesis fails;
|
// if MULWIDTH==2 synthesis fails;
|
// MUL_WIDTH==16 shows good.
|
// MUL_WIDTH==16 shows good.
|
|
|
`else
|
`else
|
parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;
|
parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;
|
`endif
|
`endif
|
`else
|
`else
|
`ifdef XILINX
|
`ifdef XILINX
|
parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
|
parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
|
// XILINX fails using ISE7.1 if MUL_WIDTH==1,2
|
// XILINX fails using ISE7.1 if MUL_WIDTH==1,2
|
// if MULWIDTH==1 synthesis is possible but post synthesis simulation fails
|
// if MULWIDTH==1 synthesis is possible but post synthesis simulation fails
|
// if MULWIDTH==2 synthesis fails;
|
// if MULWIDTH==2 synthesis fails;
|
// MUL_WIDTH==16 shows good.
|
// MUL_WIDTH==16 shows good.
|
|
|
`else
|
`else
|
`ifdef Stratix2
|
`ifdef Stratix2
|
parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
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parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
|
`else
|
`else
|
parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;
|
parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
input clock,sync_reset;
|
input clock,sync_reset;
|
input [31:0] a,b;
|
input [31:0] a,b;
|
input [7:0] state;
|
input [7:0] state;
|
input lohi;
|
input lohi;
|
input mul_div_enable,mul_div_sign,mul_div_word,mul_div_mode;
|
input mul_div_enable,mul_div_sign,mul_div_word,mul_div_mode;
|
output stop_state;
|
output stop_state;
|
output [31:0] mul_div_out;
|
output [31:0] mul_div_out;
|
|
|
reg [31:0] a_reg;
|
reg [31:0] a_reg;
|
reg [31:0] b_reg;
|
reg [31:0] b_reg;
|
reg [31:0] answer_reg;
|
reg [31:0] answer_reg;
|
|
|
reg stop_state_reg;// For state control
|
reg stop_state_reg;// For state control
|
reg [5:0] counter;
|
reg [5:0] counter;
|
reg mul_div_sign_ff,mul_div_mode_ff;
|
reg mul_div_sign_ff,mul_div_mode_ff;
|
reg a31_latch,b31_latch;
|
reg a31_latch,b31_latch;
|
reg breg31;
|
reg breg31;
|
//mult64
|
//mult64
|
wire [63:0] ab62={1'b0,a_reg[31]*breg31,62'h0};//Jul.5.2004
|
wire [63:0] ab62={1'b0,a_reg[31]*breg31,62'h0};//Jul.5.2004
|
wire [63:0] shift_a31=mul_div_sign_ff ? ~{2'b0,a_reg[30:0],31'h0}+1'b1: {2'b0,a_reg[30:0],31'h0} ;//Jul.13.2004 Jul.2.2004
|
wire [63:0] shift_a31=mul_div_sign_ff ? ~{2'b0,a_reg[30:0],31'h0}+1'b1: {2'b0,a_reg[30:0],31'h0} ;//Jul.13.2004 Jul.2.2004
|
wire [63:0] shift_b31=mul_div_sign_ff ? ~{2'b0,b_reg[30:0],31'h0}+1'b1: {2'b0,b_reg[30:0],31'h0};//Jul.13.2004 Jul.2.2004
|
wire [63:0] shift_b31=mul_div_sign_ff ? ~{2'b0,b_reg[30:0],31'h0}+1'b1: {2'b0,b_reg[30:0],31'h0};//Jul.13.2004 Jul.2.2004
|
|
|
wire [30:0] init_lower =breg31*shift_a31[30:0] +a_reg[31]*shift_b31[30:0]+ab62[30:0];//Jul.5.2004
|
wire [30:0] init_lower =breg31*shift_a31[30:0] +a_reg[31]*shift_b31[30:0]+ab62[30:0];//Jul.5.2004
|
wire [63:31] init_upper=breg31*shift_a31[63:31]+a_reg[31]*shift_b31[63:31]+ab62[63:31];//+carry;Jul.5.2004
|
wire [63:31] init_upper=breg31*shift_a31[63:31]+a_reg[31]*shift_b31[63:31]+ab62[63:31];//+carry;Jul.5.2004
|
wire [63:0] init_val={init_upper,init_lower};
|
wire [63:0] init_val={init_upper,init_lower};
|
wire [MUL_WIDTH+30 :0] mult32x4out_temp=a_reg[30:0]*b_reg[MUL_WIDTH-1:0];//Jul.5.2004
|
wire [MUL_WIDTH+30 :0] mult32x4out_temp=a_reg[30:0]*b_reg[MUL_WIDTH-1:0];//Jul.5.2004
|
wire [MUL_WIDTH+31 :0] mult32x4out={1'b0,mult32x4out_temp};
|
wire [MUL_WIDTH+31 :0] mult32x4out={1'b0,mult32x4out_temp};
|
reg [63:0] mult64_reg;
|
reg [63:0] mult64_reg;
|
reg [31:0] multout_reg;
|
reg [31:0] multout_reg;
|
wire [63:0] mult64_out;
|
wire [63:0] mult64_out;
|
wire [63:0] mult64=a_reg* b_reg;
|
wire [63:0] mult64=a_reg* b_reg;
|
reg [MUL_WIDTH+31-1+1 :0] mult32x4out_reg;
|
reg [MUL_WIDTH+31-1+1 :0] mult32x4out_reg;
|
|
|
|
|
wire finish_operation;
|
wire finish_operation;
|
wire pre_stop;
|
wire pre_stop;
|
wire [32:0] sum;
|
wire [32:0] sum;
|
wire [31:0] answer_inc;
|
wire [31:0] answer_inc;
|
wire [31:0] aminus=-a;
|
wire [31:0] aminus=-a;
|
wire [31:0] div_out,div_out_tmp;
|
wire [31:0] div_out,div_out_tmp;
|
|
|
|
|
wire mul_div_mode_w;
|
wire mul_div_mode_w;
|
reg mul_state_reg;
|
reg mul_state_reg;
|
reg div_msb_ff;
|
reg div_msb_ff;
|
|
|
assign mul_div_mode_w=pre_stop ? mul_div_mode: mul_div_mode_ff;
|
assign mul_div_mode_w=pre_stop ? mul_div_mode: mul_div_mode_ff;
|
|
|
`ifdef RAM4K
|
`ifdef RAM4K
|
//less area
|
//less area
|
|
|
assign mul_div_out=!lohi ? !mul_div_mode_ff ? mult64_out[31:0] : div_out :
|
assign mul_div_out=!lohi ? !mul_div_mode_ff ? mult64_out[31:0] : div_out :
|
!mul_div_mode_ff ? mult64_out[63:32] : div_out;//Jul.16.2004
|
!mul_div_mode_ff ? mult64_out[63:32] : div_out;//Jul.16.2004
|
|
|
assign div_out_tmp=!lohi ? answer_reg: {div_msb_ff,multout_reg[31:1]};
|
assign div_out_tmp=!lohi ? answer_reg: {div_msb_ff,multout_reg[31:1]};
|
assign div_out= (!lohi && (a31_latch ^ b31_latch) && mul_div_sign_ff) ||
|
assign div_out= (!lohi && (a31_latch ^ b31_latch) && mul_div_sign_ff) ||
|
(lohi && mul_div_sign_ff && a31_latch) ? ~div_out_tmp+1'b1 : div_out_tmp;
|
(lohi && mul_div_sign_ff && a31_latch) ? ~div_out_tmp+1'b1 : div_out_tmp;
|
|
|
`else
|
`else
|
|
|
// faster
|
// faster
|
reg [31:0] div_out_multout_latch,answer_reg_latch;//
|
reg [31:0] div_out_multout_latch,answer_reg_latch;//
|
|
|
assign mul_div_out=!lohi ? !mul_div_mode_ff ? mult64_out[31:0] : answer_reg_latch :
|
assign mul_div_out=!lohi ? !mul_div_mode_ff ? mult64_out[31:0] : answer_reg_latch :
|
!mul_div_mode_ff ? mult64_out[63:32] : div_out_multout_latch;//Jul.16.2004
|
!mul_div_mode_ff ? mult64_out[63:32] : div_out_multout_latch;//Jul.16.2004
|
|
|
|
|
|
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
if ( (a31_latch ^ b31_latch) && mul_div_sign_ff)
|
if ( (a31_latch ^ b31_latch) && mul_div_sign_ff)
|
answer_reg_latch<=~answer_reg+1'b1;
|
answer_reg_latch<=~answer_reg+1'b1;
|
else answer_reg_latch<= answer_reg;
|
else answer_reg_latch<= answer_reg;
|
|
|
if ( mul_div_sign_ff && a31_latch)
|
if ( mul_div_sign_ff && a31_latch)
|
div_out_multout_latch<=~{div_msb_ff,multout_reg[31:1]}+1'b1;
|
div_out_multout_latch<=~{div_msb_ff,multout_reg[31:1]}+1'b1;
|
else div_out_multout_latch<={div_msb_ff,multout_reg[31:1]};
|
else div_out_multout_latch<={div_msb_ff,multout_reg[31:1]};
|
|
|
|
|
end
|
end
|
|
|
|
|
`endif
|
`endif
|
|
|
//mul64
|
//mul64
|
//mul_state
|
//mul_state
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
breg31<=b[31];
|
breg31<=b[31];
|
end
|
end
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
mult32x4out_reg<=mult32x4out;
|
mult32x4out_reg<=mult32x4out;
|
end
|
end
|
|
|
//Jul.16.2004
|
//Jul.16.2004
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
if (sync_reset) mul_state_reg<=0;
|
if (sync_reset) mul_state_reg<=0;
|
else if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL ) mul_state_reg<=1;
|
else if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL ) mul_state_reg<=1;
|
else if (finish_operation) mul_state_reg<=0;
|
else if (finish_operation) mul_state_reg<=0;
|
end
|
end
|
|
|
//mult64_reg multout_reg
|
//mult64_reg multout_reg
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
if (mul_state_reg && counter==0 )begin
|
if (mul_state_reg && counter==0 )begin
|
mult64_reg<=init_val;//Jul.13.2004 Jul.5.2004 Jul.4.2004
|
mult64_reg<=init_val;//Jul.13.2004 Jul.5.2004 Jul.4.2004
|
end
|
end
|
else
|
else
|
if (mul_state_reg) begin
|
if (mul_state_reg) begin
|
{mult64_reg,multout_reg[31:31-MUL_WIDTH+1]}<={{MUL_WIDTH {1'b0}},mult64_reg+mult32x4out_reg};
|
{mult64_reg,multout_reg[31:31-MUL_WIDTH+1]}<={{MUL_WIDTH {1'b0}},mult64_reg+mult32x4out_reg};
|
multout_reg[31-MUL_WIDTH:0] <=multout_reg[31:MUL_WIDTH];
|
multout_reg[31-MUL_WIDTH:0] <=multout_reg[31:MUL_WIDTH];
|
|
|
//Division
|
//Division
|
end else if (pre_stop && counter==0 ) multout_reg<=0; //First
|
end else if (pre_stop && counter==0 ) multout_reg<=0; //First
|
else if (mul_div_mode_ff && stop_state_reg ) begin
|
else if (mul_div_mode_ff && stop_state_reg ) begin
|
if (sum[32]==1'b0) begin //if (a_reg >=b_reg)
|
if (sum[32]==1'b0) begin //if (a_reg >=b_reg)
|
if (finish_operation) div_msb_ff<=sum[31];
|
if (finish_operation) div_msb_ff<=sum[31];
|
multout_reg<={sum,a_reg[31]};
|
multout_reg<={sum,a_reg[31]};
|
end else begin
|
end else begin
|
if (finish_operation) div_msb_ff<=multout_reg[31];
|
if (finish_operation) div_msb_ff<=multout_reg[31];
|
multout_reg[0]<=a_reg[31];
|
multout_reg[0]<=a_reg[31];
|
multout_reg[31:1] <=multout_reg[30:0];
|
multout_reg[31:1] <=multout_reg[30:0];
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
assign mult64_out={mult64_reg[31:0],multout_reg[31:0]};
|
assign mult64_out={mult64_reg[31:0],multout_reg[31:0]};
|
//input FFs
|
//input FFs
|
|
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
if (sync_reset) begin
|
if (sync_reset) begin
|
mul_div_sign_ff<=0;
|
mul_div_sign_ff<=0;
|
mul_div_mode_ff<=0;
|
mul_div_mode_ff<=0;
|
|
|
|
|
end else if (pre_stop) begin
|
end else if (pre_stop) begin
|
mul_div_sign_ff<=mul_div_sign;
|
mul_div_sign_ff<=mul_div_sign;
|
a31_latch<=a[31];
|
a31_latch<=a[31];
|
b31_latch<=b[31];
|
b31_latch<=b[31];
|
mul_div_mode_ff<=mul_div_mode;
|
mul_div_mode_ff<=mul_div_mode;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
//state_machine
|
//state_machine
|
assign pre_stop=mul_div_enable ;
|
assign pre_stop=mul_div_enable ;
|
assign finish_operation=(mul_div_mode_ff && counter==32) || (mul_state_reg && counter==MUL_STATE_MSB) ;//Jul.2.2004
|
assign finish_operation=(mul_div_mode_ff && counter==32) || (mul_state_reg && counter==MUL_STATE_MSB) ;//Jul.2.2004
|
|
|
|
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
if (sync_reset) stop_state_reg <=0;
|
if (sync_reset) stop_state_reg <=0;
|
else if (pre_stop && !stop_state_reg ) stop_state_reg<=1;
|
else if (pre_stop && !stop_state_reg ) stop_state_reg<=1;
|
else if (stop_state_reg && finish_operation) stop_state_reg<=0;
|
else if (stop_state_reg && finish_operation) stop_state_reg<=0;
|
end
|
end
|
|
|
assign stop_state=stop_state_reg;
|
assign stop_state=stop_state_reg;
|
|
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
if (sync_reset) counter <=0;
|
if (sync_reset) counter <=0;
|
else if (!stop_state_reg) counter <=0;
|
else if (!stop_state_reg) counter <=0;
|
else if (stop_state_reg ) counter <=counter+1;
|
else if (stop_state_reg ) counter <=counter+1;
|
end
|
end
|
|
|
//a_reg
|
//a_reg
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
if(mul_div_mode_w==`MUL_DIV_MUL_SEL && pre_stop) a_reg <=a;//
|
if(mul_div_mode_w==`MUL_DIV_MUL_SEL && pre_stop) a_reg <=a;//
|
else if(mul_div_mode_w !=`MUL_DIV_MUL_SEL )begin//
|
else if(mul_div_mode_w !=`MUL_DIV_MUL_SEL )begin//
|
if (!stop_state_reg && !pre_stop) a_reg <=a_reg;//
|
if (!stop_state_reg && !pre_stop) a_reg <=a_reg;//
|
else if (pre_stop && counter==0 ) begin //
|
else if (pre_stop && counter==0 ) begin //
|
if (mul_div_sign) begin//
|
if (mul_div_sign) begin//
|
if (a[31]) a_reg <=aminus;//
|
if (a[31]) a_reg <=aminus;//
|
else a_reg <=a;
|
else a_reg <=a;
|
end else a_reg <=a;//
|
end else a_reg <=a;//
|
end else begin//div
|
end else begin//div
|
a_reg <={a_reg[30:0],1'b0};// a_reg <<=1;
|
a_reg <={a_reg[30:0],1'b0};// a_reg <<=1;
|
end
|
end
|
|
|
end
|
end
|
end
|
end
|
|
|
//b_reg
|
//b_reg
|
always @(posedge clock) begin
|
always @(posedge clock) begin
|
if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL ) b_reg<={1'b0,b[30:0]};
|
if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL ) b_reg<={1'b0,b[30:0]};
|
else if ( mul_state_reg) b_reg<=b_reg[31:MUL_WIDTH];
|
else if ( mul_state_reg) b_reg<=b_reg[31:MUL_WIDTH];
|
else if( mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
|
else if( mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
|
if (!stop_state_reg && !pre_stop ) b_reg <=b_reg;//
|
if (!stop_state_reg && !pre_stop ) b_reg <=b_reg;//
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else if (pre_stop && counter==0 ) begin //
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else if (pre_stop && counter==0 ) begin //
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if (mul_div_sign) begin//
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if (mul_div_sign) begin//
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if ( b[31]) b_reg <=-b[31:0];//
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if ( b[31]) b_reg <=-b[31:0];//
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else b_reg <=b[31:0];//
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else b_reg <=b[31:0];//
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end else begin
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end else begin
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b_reg <=b[31:0];//
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b_reg <=b[31:0];//
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end
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end
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end else begin//div
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end else begin//div
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b_reg <=b_reg;//;
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b_reg <=b_reg;//;
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end
|
end
|
end
|
end
|
end
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end
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|
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//answer_reg
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//answer_reg
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always @(posedge clock) begin
|
always @(posedge clock) begin
|
|
|
if (mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
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if (mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
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if (!stop_state_reg && !pre_stop) answer_reg <=answer_reg;//
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if (!stop_state_reg && !pre_stop) answer_reg <=answer_reg;//
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else if (pre_stop && counter==0 ) answer_reg<=0; //
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else if (pre_stop && counter==0 ) answer_reg<=0; //
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else begin//div
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else begin//div
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if ( !sum[32] ) begin//
|
if ( !sum[32] ) begin//
|
if (finish_operation) answer_reg <=answer_inc;
|
if (finish_operation) answer_reg <=answer_inc;
|
else answer_reg <={answer_inc[30:0],1'b0}; //Jun.7.2004 a_reg -= b_reg
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else answer_reg <={answer_inc[30:0],1'b0}; //Jun.7.2004 a_reg -= b_reg
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end else begin
|
end else begin
|
if (finish_operation ) begin
|
if (finish_operation ) begin
|
answer_reg <=answer_reg;
|
answer_reg <=answer_reg;
|
end else answer_reg <={answer_reg[30:0],1'b0}; // answer_reg <<=1;
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end else answer_reg <={answer_reg[30:0],1'b0}; // answer_reg <<=1;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
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assign sum={1'b0,multout_reg}+~{1'b0,b_reg}+1'b1;//
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assign sum={1'b0,multout_reg}+~{1'b0,b_reg}+1'b1;//
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assign answer_inc=answer_reg+1'b1;//Jun.7.2004
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assign answer_inc=answer_reg+1'b1;//Jun.7.2004
|
|
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endmodule
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endmodule
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|
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