Flow report for yacc
|
Flow report for yacc
|
Thu Apr 14 21:02:39 2005
|
Thu Apr 14 21:02:39 2005
|
Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition
|
Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition
|
|
|
|
|
---------------------
|
---------------------
|
; Table of Contents ;
|
; Table of Contents ;
|
---------------------
|
---------------------
|
1. Legal Notice
|
1. Legal Notice
|
2. Flow Summary
|
2. Flow Summary
|
3. Flow Settings
|
3. Flow Settings
|
4. Flow Elapsed Time
|
4. Flow Elapsed Time
|
5. Flow Log
|
5. Flow Log
|
|
|
|
|
|
|
----------------
|
----------------
|
; Legal Notice ;
|
; Legal Notice ;
|
----------------
|
----------------
|
Copyright (C) 1991-2005 Altera Corporation
|
Copyright (C) 1991-2005 Altera Corporation
|
Any megafunction design, and related netlist (encrypted or decrypted),
|
Any megafunction design, and related netlist (encrypted or decrypted),
|
support information, device programming or simulation file, and any other
|
support information, device programming or simulation file, and any other
|
associated documentation or information provided by Altera or a partner
|
associated documentation or information provided by Altera or a partner
|
under Altera's Megafunction Partnership Program may be used only
|
under Altera's Megafunction Partnership Program may be used only
|
to program PLD devices (but not masked PLD devices) from Altera. Any
|
to program PLD devices (but not masked PLD devices) from Altera. Any
|
other use of such megafunction design, netlist, support information,
|
other use of such megafunction design, netlist, support information,
|
device programming or simulation file, or any other related documentation
|
device programming or simulation file, or any other related documentation
|
or information is prohibited for any other purpose, including, but not
|
or information is prohibited for any other purpose, including, but not
|
limited to modification, reverse engineering, de-compiling, or use with
|
limited to modification, reverse engineering, de-compiling, or use with
|
any other silicon devices, unless such use is explicitly licensed under
|
any other silicon devices, unless such use is explicitly licensed under
|
a separate agreement with Altera or a megafunction partner. Title to the
|
a separate agreement with Altera or a megafunction partner. Title to the
|
intellectual property, including patents, copyrights, trademarks, trade
|
intellectual property, including patents, copyrights, trademarks, trade
|
secrets, or maskworks, embodied in any such megafunction design, netlist,
|
secrets, or maskworks, embodied in any such megafunction design, netlist,
|
support information, device programming or simulation file, or any other
|
support information, device programming or simulation file, or any other
|
related documentation or information provided by Altera or a megafunction
|
related documentation or information provided by Altera or a megafunction
|
partner, remains with Altera, the megafunction partner, or their respective
|
partner, remains with Altera, the megafunction partner, or their respective
|
licensors. No other licenses, including any licenses needed under any third
|
licensors. No other licenses, including any licenses needed under any third
|
party's intellectual property, are provided herein.
|
party's intellectual property, are provided herein.
|
|
|
|
|
|
|
+------------------------------------------------------------------------+
|
+------------------------------------------------------------------------+
|
; Flow Summary ;
|
; Flow Summary ;
|
+-------------------------+----------------------------------------------+
|
+-------------------------+----------------------------------------------+
|
; Flow Status ; Successful - Thu Apr 14 21:02:27 2005 ;
|
; Flow Status ; Successful - Thu Apr 14 21:02:27 2005 ;
|
; Quartus II Version ; 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition ;
|
; Quartus II Version ; 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition ;
|
; Revision Name ; yacc ;
|
; Revision Name ; yacc ;
|
; Top-level Entity Name ; yacc ;
|
; Top-level Entity Name ; yacc ;
|
; Family ; Cyclone ;
|
; Family ; Cyclone ;
|
; Device ; EP1C12Q240C6 ;
|
; Device ; EP1C12Q240C6 ;
|
; Timing Models ; Final ;
|
; Timing Models ; Final ;
|
; Met timing requirements ; Yes ;
|
; Met timing requirements ; Yes ;
|
; Total logic elements ; 3,624 / 12,060 ( 30 % ) ;
|
; Total logic elements ; 3,624 / 12,060 ( 30 % ) ;
|
; Total pins ; 53 / 173 ( 30 % ) ;
|
; Total pins ; 53 / 173 ( 30 % ) ;
|
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
; Total memory bits ; 137,216 / 239,616 ( 57 % ) ;
|
; Total memory bits ; 137,216 / 239,616 ( 57 % ) ;
|
; Total PLLs ; 0 / 2 ( 0 % ) ;
|
; Total PLLs ; 0 / 2 ( 0 % ) ;
|
+-------------------------+----------------------------------------------+
|
+-------------------------+----------------------------------------------+
|
|
|
|
|
+-----------------------------------------+
|
+-----------------------------------------+
|
; Flow Settings ;
|
; Flow Settings ;
|
+-------------------+---------------------+
|
+-------------------+---------------------+
|
; Option ; Setting ;
|
; Option ; Setting ;
|
+-------------------+---------------------+
|
+-------------------+---------------------+
|
; Start date & time ; 04/14/2005 20:28:30 ;
|
; Start date & time ; 04/14/2005 20:28:30 ;
|
; Main task ; Compilation ;
|
; Main task ; Compilation ;
|
; Revision Name ; yacc ;
|
; Revision Name ; yacc ;
|
+-------------------+---------------------+
|
+-------------------+---------------------+
|
|
|
|
|
+-------------------------------------+
|
+-------------------------------------+
|
; Flow Elapsed Time ;
|
; Flow Elapsed Time ;
|
+----------------------+--------------+
|
+----------------------+--------------+
|
; Module Name ; Elapsed Time ;
|
; Module Name ; Elapsed Time ;
|
+----------------------+--------------+
|
+----------------------+--------------+
|
; Analysis & Synthesis ; 00:04:40 ;
|
; Analysis & Synthesis ; 00:04:40 ;
|
; Fitter ; 00:25:30 ;
|
; Fitter ; 00:25:30 ;
|
; Assembler ; 00:00:27 ;
|
; Assembler ; 00:00:27 ;
|
; Timing Analyzer ; 00:00:17 ;
|
; Timing Analyzer ; 00:00:17 ;
|
; EDA Netlist Writer ; 00:02:29 ;
|
; EDA Netlist Writer ; 00:02:29 ;
|
; Total ; 00:33:23 ;
|
; Total ; 00:33:23 ;
|
+----------------------+--------------+
|
+----------------------+--------------+
|
|
|
|
|
------------
|
------------
|
; Flow Log ;
|
; Flow Log ;
|
------------
|
------------
|
quartus_map --lower_priority --import_settings_files=on --export_settings_files=off yacc -c yacc
|
quartus_map --lower_priority --import_settings_files=on --export_settings_files=off yacc -c yacc
|
quartus_fit --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc
|
quartus_fit --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc
|
quartus_asm --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc
|
quartus_asm --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc
|
quartus_tan --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc --timing_analysis_only
|
quartus_tan --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc --timing_analysis_only
|
quartus_eda --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc
|
quartus_eda --lower_priority --import_settings_files=off --export_settings_files=off yacc -c yacc
|
|
|
|
|
|
|
|
|
