// SPDX-FileCopyrightText: 2020 Efabless Corporation
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// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// You may obtain a copy of the License at
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//
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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`default_nettype none
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`timescale 1 ns / 1 ps
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`timescale 1 ns / 1 ps
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`include "uprj_netlists.v"
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`include "uprj_netlists.v"
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`include "caravel_netlists.v"
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`include "caravel_netlists.v"
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`include "spiflash.v"
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`include "spiflash.v"
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module io_ports_tb;
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module io_ports_tb;
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reg clock;
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reg clock;
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reg RSTB;
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reg RSTB;
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reg CSB;
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reg CSB;
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reg power1, power2;
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reg power1, power2;
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reg power3, power4;
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reg power3, power4;
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wire gpio;
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wire gpio;
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wire [37:0] mprj_io;
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wire [37:0] mprj_io;
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wire [7:0] mprj_io_0;
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wire [7:0] mprj_io_0;
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assign mprj_io_0 = mprj_io[7:0];
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assign mprj_io_0 = mprj_io[7:0];
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// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
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// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
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assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
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assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
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// assign mprj_io[3] = 1'b1;
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// assign mprj_io[3] = 1'b1;
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// External clock is used by default. Make this artificially fast for the
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// External clock is used by default. Make this artificially fast for the
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// simulation. Normally this would be a slow clock and the digital PLL
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// simulation. Normally this would be a slow clock and the digital PLL
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// would be the fast clock.
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// would be the fast clock.
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always #12.5 clock <= (clock === 1'b0);
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always #12.5 clock <= (clock === 1'b0);
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initial begin
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initial begin
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clock = 0;
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clock = 0;
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end
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end
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initial begin
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initial begin
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`ifdef WFDUMP
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$dumpfile("io_ports.vcd");
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$dumpfile("io_ports.vcd");
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$dumpvars(0, io_ports_tb);
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$dumpvars(0, io_ports_tb);
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`endif
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// Repeat cycles of 1000 clock edges as needed to complete testbench
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// Repeat cycles of 1000 clock edges as needed to complete testbench
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repeat (25) begin
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repeat (25) begin
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repeat (1000) @(posedge clock);
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repeat (1000) @(posedge clock);
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// $display("+1000 cycles");
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// $display("+1000 cycles");
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end
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end
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$display("%c[1;31m",27);
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$display("%c[1;31m",27);
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`ifdef GL
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`ifdef GL
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$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
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$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
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`else
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`else
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$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
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$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
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`endif
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`endif
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$display("%c[0m",27);
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$display("%c[0m",27);
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$finish;
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$finish;
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end
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end
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initial begin
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initial begin
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// Observe Output pins [7:0]
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// Observe Output pins [7:0]
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wait(mprj_io_0 == 8'h01);
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wait(mprj_io_0 == 8'h01);
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wait(mprj_io_0 == 8'h02);
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wait(mprj_io_0 == 8'h02);
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wait(mprj_io_0 == 8'h03);
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wait(mprj_io_0 == 8'h03);
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wait(mprj_io_0 == 8'h04);
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wait(mprj_io_0 == 8'h04);
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wait(mprj_io_0 == 8'h05);
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wait(mprj_io_0 == 8'h05);
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wait(mprj_io_0 == 8'h06);
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wait(mprj_io_0 == 8'h06);
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wait(mprj_io_0 == 8'h07);
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wait(mprj_io_0 == 8'h07);
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wait(mprj_io_0 == 8'h08);
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wait(mprj_io_0 == 8'h08);
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wait(mprj_io_0 == 8'h09);
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wait(mprj_io_0 == 8'h09);
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wait(mprj_io_0 == 8'h0A);
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wait(mprj_io_0 == 8'h0A);
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wait(mprj_io_0 == 8'hFF);
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wait(mprj_io_0 == 8'hFF);
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wait(mprj_io_0 == 8'h00);
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wait(mprj_io_0 == 8'h00);
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`ifdef GL
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`ifdef GL
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$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
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$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
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`else
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`else
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$display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
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$display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
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`endif
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`endif
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$finish;
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$finish;
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end
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end
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initial begin
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initial begin
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RSTB <= 1'b0;
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RSTB <= 1'b0;
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CSB <= 1'b1; // Force CSB high
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CSB <= 1'b1; // Force CSB high
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#2000;
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#2000;
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RSTB <= 1'b1; // Release reset
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RSTB <= 1'b1; // Release reset
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#170000;
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#170000;
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CSB = 1'b0; // CSB can be released
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CSB = 1'b0; // CSB can be released
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end
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end
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initial begin // Power-up sequence
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initial begin // Power-up sequence
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power1 <= 1'b0;
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power1 <= 1'b0;
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power2 <= 1'b0;
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power2 <= 1'b0;
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power3 <= 1'b0;
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power3 <= 1'b0;
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power4 <= 1'b0;
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power4 <= 1'b0;
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#100;
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#100;
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power1 <= 1'b1;
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power1 <= 1'b1;
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#100;
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#100;
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power2 <= 1'b1;
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power2 <= 1'b1;
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#100;
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#100;
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power3 <= 1'b1;
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power3 <= 1'b1;
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#100;
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#100;
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power4 <= 1'b1;
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power4 <= 1'b1;
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end
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end
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always @(mprj_io) begin
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always @(mprj_io) begin
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#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
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#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
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end
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end
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wire flash_csb;
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wire flash_csb;
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wire flash_clk;
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wire flash_clk;
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wire flash_io0;
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wire flash_io0;
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wire flash_io1;
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wire flash_io1;
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wire VDD3V3 = power1;
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wire VDD3V3 = power1;
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wire VDD1V8 = power2;
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wire VDD1V8 = power2;
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wire USER_VDD3V3 = power3;
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wire USER_VDD3V3 = power3;
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wire USER_VDD1V8 = power4;
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wire USER_VDD1V8 = power4;
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wire VSS = 1'b0;
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wire VSS = 1'b0;
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caravel uut (
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caravel uut (
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.vddio (VDD3V3),
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.vddio (VDD3V3),
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.vssio (VSS),
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.vssio (VSS),
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.vdda (VDD3V3),
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.vdda (VDD3V3),
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.vssa (VSS),
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.vssa (VSS),
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.vccd (VDD1V8),
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.vccd (VDD1V8),
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.vssd (VSS),
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.vssd (VSS),
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.vdda1 (USER_VDD3V3),
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.vdda1 (USER_VDD3V3),
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.vdda2 (USER_VDD3V3),
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.vdda2 (USER_VDD3V3),
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.vssa1 (VSS),
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.vssa1 (VSS),
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.vssa2 (VSS),
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.vssa2 (VSS),
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.vccd1 (USER_VDD1V8),
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.vccd1 (USER_VDD1V8),
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.vccd2 (USER_VDD1V8),
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.vccd2 (USER_VDD1V8),
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.vssd1 (VSS),
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.vssd1 (VSS),
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.vssd2 (VSS),
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.vssd2 (VSS),
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.clock (clock),
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.clock (clock),
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.gpio (gpio),
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.gpio (gpio),
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.mprj_io (mprj_io),
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.mprj_io (mprj_io),
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.flash_csb(flash_csb),
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.flash_csb(flash_csb),
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.flash_clk(flash_clk),
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.flash_clk(flash_clk),
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.flash_io0(flash_io0),
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.flash_io0(flash_io0),
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.flash_io1(flash_io1),
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.flash_io1(flash_io1),
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.resetb (RSTB)
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.resetb (RSTB)
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);
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);
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spiflash #(
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spiflash #(
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.FILENAME("io_ports.hex")
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.FILENAME("io_ports.hex")
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) spiflash (
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) spiflash (
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.csb(flash_csb),
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.csb(flash_csb),
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.clk(flash_clk),
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.clk(flash_clk),
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.io0(flash_io0),
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.io0(flash_io0),
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.io1(flash_io1),
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.io1(flash_io1),
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.io2(), // not used
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.io2(), // not used
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.io3() // not used
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.io3() // not used
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);
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);
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endmodule
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endmodule
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`default_nettype wire
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`default_nettype wire
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