/*
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/*
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* SPDX-FileCopyrightText: 2020 Efabless Corporation
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* SPDX-FileCopyrightText: 2020 Efabless Corporation
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*
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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* You may obtain a copy of the License at
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*
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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*
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* Unless required by applicable law or agreed to in writing, software
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* limitations under the License.
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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// This include is relative to $CARAVEL_PATH (see Makefile)
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// This include is relative to $CARAVEL_PATH (see Makefile)
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#include "verilog/dv/caravel/defs.h"
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#include "verilog/dv/caravel/defs.h"
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#include "verilog/dv/caravel/stub.c"
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#include "verilog/dv/caravel/stub.c"
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// User Project Slaves (0x3000_0000)
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#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
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#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30000000)
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#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30000004)
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#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30000008)
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#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3000000C)
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#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30000010)
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#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30000014)
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#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30000018)
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#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3000001C)
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#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30000020)
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#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30000024)
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#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30000028)
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#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3000002C)
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#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30000030)
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#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30000034)
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#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30000038)
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#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3000003C)
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/*
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/*
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Wishbone Test:
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Wishbone Test:
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- Configures MPRJ lower 8-IO pins as outputs
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- Configures MPRJ lower 8-IO pins as outputs
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- Checks counter value through the wishbone port
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- Checks counter value through the wishbone port
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*/
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*/
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int i = 0;
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int i = 0;
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int clk = 0;
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int clk = 0;
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void main()
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void main()
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{
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{
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int bFail = 0;
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/*
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/*
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IO Control Registers
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IO Control Registers
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| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
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| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
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| 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
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| 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
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Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
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Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
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| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
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| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
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| 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
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| 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
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Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
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Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
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| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
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| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
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| 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
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| 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
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*/
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*/
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/* Set up the housekeeping SPI to be connected internally so */
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/* Set up the housekeeping SPI to be connected internally so */
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/* that external pin changes don't affect it. */
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/* that external pin changes don't affect it. */
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reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
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reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
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// connect to housekeeping SPI
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// connect to housekeeping SPI
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// Connect the housekeeping SPI to the SPI master
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// Connect the housekeeping SPI to the SPI master
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// so that the CSB line is not left floating. This allows
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// so that the CSB line is not left floating. This allows
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// all of the GPIO pins to be used for user functions.
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// all of the GPIO pins to be used for user functions.
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reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
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/* Apply configuration */
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/* Apply configuration */
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reg_mprj_xfer = 1;
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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while (reg_mprj_xfer == 1);
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reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
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reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
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// Flag start of the test
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// Flag start of the test
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reg_mprj_datal = 0xAB600000;
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reg_mprj_datal = 0xAB600000;
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reg_mprj_slave = 0x00002710;
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if (reg_mprj_globl_reg1 != 0xA55AA55A) bFail = 1;
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if (reg_mprj_slave == 0x2752) {
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if (reg_mprj_globl_reg2 != 0xAABBCCDD) bFail = 1;
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// Write software Write & Read Register
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reg_mprj_globl_reg6 = 0x11223344;
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reg_mprj_globl_reg7 = 0x22334455;
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reg_mprj_globl_reg8 = 0x33445566;
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reg_mprj_globl_reg9 = 0x44556677;
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reg_mprj_globl_reg10 = 0x55667788;
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reg_mprj_globl_reg11 = 0x66778899;
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reg_mprj_globl_reg12 = 0x778899AA;
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reg_mprj_globl_reg13 = 0x8899AABB;
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reg_mprj_globl_reg14 = 0x99AABBCC;
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reg_mprj_globl_reg15 = 0xAABBCCDD;
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if (reg_mprj_globl_reg6 != 0x11223344) bFail = 1;
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if (reg_mprj_globl_reg7 != 0x22334455) bFail = 1;
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if (reg_mprj_globl_reg8 != 0x33445566) bFail = 1;
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if (reg_mprj_globl_reg9 != 0x44556677) bFail = 1;
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if (reg_mprj_globl_reg10 != 0x55667788) bFail = 1;
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if (reg_mprj_globl_reg11 != 0x66778899) bFail = 1;
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if (reg_mprj_globl_reg12 != 0x778899AA) bFail = 1;
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if (reg_mprj_globl_reg13 != 0x8899AABB) bFail = 1;
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if (reg_mprj_globl_reg14 != 0x99AABBCC) bFail = 1;
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if (reg_mprj_globl_reg15 != 0xAABBCCDD) bFail = 1;
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if(bFail == 0) {
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reg_mprj_datal = 0xAB610000;
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reg_mprj_datal = 0xAB610000;
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} else {
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} else {
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reg_mprj_datal = 0xAB600000;
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reg_mprj_datal = 0xAB600000;
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}
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}
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}
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}
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