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https://opencores.org/ocsvn/z80soc/z80soc/trunk
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Rev 31 |
#!/bin/sh
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#!/bin/sh
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file=rom.hex
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file=rom.hex
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echo "library IEEE;
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echo "library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity rom is
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entity rom is
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port(
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port(
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Clk : in std_logic;
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Clk : in std_logic;
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A : in std_logic_vector(15 downto 0);
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A : in std_logic_vector(15 downto 0);
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D : out std_logic_vector(7 downto 0)
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D : out std_logic_vector(7 downto 0)
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);
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);
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end rom;
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end rom;
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architecture rtl of rom is
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architecture rtl of rom is
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begin
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begin
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process (Clk)
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process (Clk)
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begin
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begin
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if Clk'event and Clk = '1' then
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if Clk'event and Clk = '1' then
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case A is"
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case A is"
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ADDR=0
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ADDR=0
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for i in `cat $file | tr ',' ' '`
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for i in `cat $file | tr ',' ' '`
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do
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do
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BL1="when x\""
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BL1="when x\""
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BL3="\" => D <= x\"$i\";"
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BL3="\" => D <= x\"$i\";"
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hexaddr="000"`echo "obase=16;ibase=10;$ADDR" | bc`
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hexaddr="000"`echo "obase=16;ibase=10;$ADDR" | bc`
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fixhexaddr=${hexaddr:(-4)}
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fixhexaddr=${hexaddr:(-4)}
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echo " "$BL1$fixhexaddr$BL3
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echo " "$BL1$fixhexaddr$BL3
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let ADDR=ADDR+1
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let ADDR=ADDR+1
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done
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done
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echo " when others => D <= x\"00\";
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echo " when others => D <= x\"00\";
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end;"
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end;"
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