-- ****
|
-- ****
|
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
--
|
--
|
--
|
--
|
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
|
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
|
--
|
--
|
-- MikeJ March 2005
|
-- MikeJ March 2005
|
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
--
|
--
|
-- ****
|
-- ****
|
--
|
--
|
-- Z80 compatible microprocessor core
|
-- Z80 compatible microprocessor core
|
--
|
--
|
-- Version : 0247
|
-- Version : 0247
|
--
|
--
|
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
|
--
|
--
|
-- Redistributions of source code must retain the above copyright notice,
|
-- Redistributions of source code must retain the above copyright notice,
|
-- this list of conditions and the following disclaimer.
|
-- this list of conditions and the following disclaimer.
|
--
|
--
|
-- Redistributions in synthesized form must reproduce the above copyright
|
-- Redistributions in synthesized form must reproduce the above copyright
|
-- notice, this list of conditions and the following disclaimer in the
|
-- notice, this list of conditions and the following disclaimer in the
|
-- documentation and/or other materials provided with the distribution.
|
-- documentation and/or other materials provided with the distribution.
|
--
|
--
|
-- Neither the name of the author nor the names of other contributors may
|
-- Neither the name of the author nor the names of other contributors may
|
-- be used to endorse or promote products derived from this software without
|
-- be used to endorse or promote products derived from this software without
|
-- specific prior written permission.
|
-- specific prior written permission.
|
--
|
--
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- POSSIBILITY OF SUCH DAMAGE.
|
-- POSSIBILITY OF SUCH DAMAGE.
|
--
|
--
|
-- Please report bugs to the author, but before you do so, please
|
-- Please report bugs to the author, but before you do so, please
|
-- make sure that this is not a derivative work and that
|
-- make sure that this is not a derivative work and that
|
-- you have the latest version of this file.
|
-- you have the latest version of this file.
|
--
|
--
|
-- The latest version of this file can be found at:
|
-- The latest version of this file can be found at:
|
-- http://www.opencores.org/cvsweb.shtml/t80/
|
-- http://www.opencores.org/cvsweb.shtml/t80/
|
--
|
--
|
-- Limitations :
|
-- Limitations :
|
--
|
--
|
-- File history :
|
-- File history :
|
--
|
--
|
-- 0208 : First complete release
|
-- 0208 : First complete release
|
--
|
--
|
-- 0210 : Fixed wait and halt
|
-- 0210 : Fixed wait and halt
|
--
|
--
|
-- 0211 : Fixed Refresh addition and IM 1
|
-- 0211 : Fixed Refresh addition and IM 1
|
--
|
--
|
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
|
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
|
--
|
--
|
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
|
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
|
--
|
--
|
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
|
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
|
--
|
--
|
-- 0237 : Changed 8080 I/O address output, added IntE output
|
-- 0237 : Changed 8080 I/O address output, added IntE output
|
--
|
--
|
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
|
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
|
--
|
--
|
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
|
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
|
--
|
--
|
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
|
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
|
--
|
--
|
-- 0247 : Fixed bus req/ack cycle
|
-- 0247 : Fixed bus req/ack cycle
|
--
|
--
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
use IEEE.numeric_std.all;
|
use IEEE.numeric_std.all;
|
use work.T80_Pack.all;
|
use work.T80_Pack.all;
|
|
|
entity T80 is
|
entity T80 is
|
generic(
|
generic(
|
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
Flag_C : integer := 0;
|
Flag_C : integer := 0;
|
Flag_N : integer := 1;
|
Flag_N : integer := 1;
|
Flag_P : integer := 2;
|
Flag_P : integer := 2;
|
Flag_X : integer := 3;
|
Flag_X : integer := 3;
|
Flag_H : integer := 4;
|
Flag_H : integer := 4;
|
Flag_Y : integer := 5;
|
Flag_Y : integer := 5;
|
Flag_Z : integer := 6;
|
Flag_Z : integer := 6;
|
Flag_S : integer := 7
|
Flag_S : integer := 7
|
);
|
);
|
port(
|
port(
|
RESET_n : in std_logic;
|
RESET_n : in std_logic;
|
CLK_n : in std_logic;
|
CLK_n : in std_logic;
|
CEN : in std_logic;
|
CEN : in std_logic;
|
WAIT_n : in std_logic;
|
WAIT_n : in std_logic;
|
INT_n : in std_logic;
|
INT_n : in std_logic;
|
NMI_n : in std_logic;
|
NMI_n : in std_logic;
|
BUSRQ_n : in std_logic;
|
BUSRQ_n : in std_logic;
|
M1_n : out std_logic;
|
M1_n : out std_logic;
|
IORQ : out std_logic;
|
IORQ : out std_logic;
|
NoRead : out std_logic;
|
NoRead : out std_logic;
|
Write : out std_logic;
|
Write : out std_logic;
|
RFSH_n : out std_logic;
|
RFSH_n : out std_logic;
|
HALT_n : out std_logic;
|
HALT_n : out std_logic;
|
BUSAK_n : out std_logic;
|
BUSAK_n : out std_logic;
|
A : out std_logic_vector(15 downto 0);
|
A : out std_logic_vector(15 downto 0);
|
DInst : in std_logic_vector(7 downto 0);
|
DInst : in std_logic_vector(7 downto 0);
|
DI : in std_logic_vector(7 downto 0);
|
DI : in std_logic_vector(7 downto 0);
|
DO : out std_logic_vector(7 downto 0);
|
DO : out std_logic_vector(7 downto 0);
|
MC : out std_logic_vector(2 downto 0);
|
MC : out std_logic_vector(2 downto 0);
|
TS : out std_logic_vector(2 downto 0);
|
TS : out std_logic_vector(2 downto 0);
|
IntCycle_n : out std_logic;
|
IntCycle_n : out std_logic;
|
IntE : out std_logic;
|
IntE : out std_logic;
|
Stop : out std_logic
|
Stop : out std_logic
|
);
|
);
|
end T80;
|
end T80;
|
|
|
architecture rtl of T80 is
|
architecture rtl of T80 is
|
|
|
constant aNone : std_logic_vector(2 downto 0) := "111";
|
constant aNone : std_logic_vector(2 downto 0) := "111";
|
constant aBC : std_logic_vector(2 downto 0) := "000";
|
constant aBC : std_logic_vector(2 downto 0) := "000";
|
constant aDE : std_logic_vector(2 downto 0) := "001";
|
constant aDE : std_logic_vector(2 downto 0) := "001";
|
constant aXY : std_logic_vector(2 downto 0) := "010";
|
constant aXY : std_logic_vector(2 downto 0) := "010";
|
constant aIOA : std_logic_vector(2 downto 0) := "100";
|
constant aIOA : std_logic_vector(2 downto 0) := "100";
|
constant aSP : std_logic_vector(2 downto 0) := "101";
|
constant aSP : std_logic_vector(2 downto 0) := "101";
|
constant aZI : std_logic_vector(2 downto 0) := "110";
|
constant aZI : std_logic_vector(2 downto 0) := "110";
|
|
|
-- Registers
|
-- Registers
|
signal ACC, F : std_logic_vector(7 downto 0);
|
signal ACC, F : std_logic_vector(7 downto 0);
|
signal Ap, Fp : std_logic_vector(7 downto 0);
|
signal Ap, Fp : std_logic_vector(7 downto 0);
|
signal I : std_logic_vector(7 downto 0);
|
signal I : std_logic_vector(7 downto 0);
|
signal R : unsigned(7 downto 0);
|
signal R : unsigned(7 downto 0);
|
signal SP, PC : unsigned(15 downto 0);
|
signal SP, PC : unsigned(15 downto 0);
|
|
|
signal RegDIH : std_logic_vector(7 downto 0);
|
signal RegDIH : std_logic_vector(7 downto 0);
|
signal RegDIL : std_logic_vector(7 downto 0);
|
signal RegDIL : std_logic_vector(7 downto 0);
|
signal RegBusA : std_logic_vector(15 downto 0);
|
signal RegBusA : std_logic_vector(15 downto 0);
|
signal RegBusB : std_logic_vector(15 downto 0);
|
signal RegBusB : std_logic_vector(15 downto 0);
|
signal RegBusC : std_logic_vector(15 downto 0);
|
signal RegBusC : std_logic_vector(15 downto 0);
|
signal RegAddrA_r : std_logic_vector(2 downto 0);
|
signal RegAddrA_r : std_logic_vector(2 downto 0);
|
signal RegAddrA : std_logic_vector(2 downto 0);
|
signal RegAddrA : std_logic_vector(2 downto 0);
|
signal RegAddrB_r : std_logic_vector(2 downto 0);
|
signal RegAddrB_r : std_logic_vector(2 downto 0);
|
signal RegAddrB : std_logic_vector(2 downto 0);
|
signal RegAddrB : std_logic_vector(2 downto 0);
|
signal RegAddrC : std_logic_vector(2 downto 0);
|
signal RegAddrC : std_logic_vector(2 downto 0);
|
signal RegWEH : std_logic;
|
signal RegWEH : std_logic;
|
signal RegWEL : std_logic;
|
signal RegWEL : std_logic;
|
signal Alternate : std_logic;
|
signal Alternate : std_logic;
|
|
|
-- Help Registers
|
-- Help Registers
|
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
|
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
|
signal IR : std_logic_vector(7 downto 0); -- Instruction register
|
signal IR : std_logic_vector(7 downto 0); -- Instruction register
|
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
|
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
|
signal RegBusA_r : std_logic_vector(15 downto 0);
|
signal RegBusA_r : std_logic_vector(15 downto 0);
|
|
|
signal ID16 : signed(15 downto 0);
|
signal ID16 : signed(15 downto 0);
|
signal Save_Mux : std_logic_vector(7 downto 0);
|
signal Save_Mux : std_logic_vector(7 downto 0);
|
|
|
signal TState : unsigned(2 downto 0);
|
signal TState : unsigned(2 downto 0);
|
signal MCycle : std_logic_vector(2 downto 0);
|
signal MCycle : std_logic_vector(2 downto 0);
|
signal IntE_FF1 : std_logic;
|
signal IntE_FF1 : std_logic;
|
signal IntE_FF2 : std_logic;
|
signal IntE_FF2 : std_logic;
|
signal Halt_FF : std_logic;
|
signal Halt_FF : std_logic;
|
signal BusReq_s : std_logic;
|
signal BusReq_s : std_logic;
|
signal BusAck : std_logic;
|
signal BusAck : std_logic;
|
signal ClkEn : std_logic;
|
signal ClkEn : std_logic;
|
signal NMI_s : std_logic;
|
signal NMI_s : std_logic;
|
signal INT_s : std_logic;
|
signal INT_s : std_logic;
|
signal IStatus : std_logic_vector(1 downto 0);
|
signal IStatus : std_logic_vector(1 downto 0);
|
|
|
signal DI_Reg : std_logic_vector(7 downto 0);
|
signal DI_Reg : std_logic_vector(7 downto 0);
|
signal T_Res : std_logic;
|
signal T_Res : std_logic;
|
signal XY_State : std_logic_vector(1 downto 0);
|
signal XY_State : std_logic_vector(1 downto 0);
|
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
|
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
|
signal NextIs_XY_Fetch : std_logic;
|
signal NextIs_XY_Fetch : std_logic;
|
signal XY_Ind : std_logic;
|
signal XY_Ind : std_logic;
|
signal No_BTR : std_logic;
|
signal No_BTR : std_logic;
|
signal BTR_r : std_logic;
|
signal BTR_r : std_logic;
|
signal Auto_Wait : std_logic;
|
signal Auto_Wait : std_logic;
|
signal Auto_Wait_t1 : std_logic;
|
signal Auto_Wait_t1 : std_logic;
|
signal Auto_Wait_t2 : std_logic;
|
signal Auto_Wait_t2 : std_logic;
|
signal IncDecZ : std_logic;
|
signal IncDecZ : std_logic;
|
|
|
-- ALU signals
|
-- ALU signals
|
signal BusB : std_logic_vector(7 downto 0);
|
signal BusB : std_logic_vector(7 downto 0);
|
signal BusA : std_logic_vector(7 downto 0);
|
signal BusA : std_logic_vector(7 downto 0);
|
signal ALU_Q : std_logic_vector(7 downto 0);
|
signal ALU_Q : std_logic_vector(7 downto 0);
|
signal F_Out : std_logic_vector(7 downto 0);
|
signal F_Out : std_logic_vector(7 downto 0);
|
|
|
-- Registered micro code outputs
|
-- Registered micro code outputs
|
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
|
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
|
signal Arith16_r : std_logic;
|
signal Arith16_r : std_logic;
|
signal Z16_r : std_logic;
|
signal Z16_r : std_logic;
|
signal ALU_Op_r : std_logic_vector(3 downto 0);
|
signal ALU_Op_r : std_logic_vector(3 downto 0);
|
signal Save_ALU_r : std_logic;
|
signal Save_ALU_r : std_logic;
|
signal PreserveC_r : std_logic;
|
signal PreserveC_r : std_logic;
|
signal MCycles : std_logic_vector(2 downto 0);
|
signal MCycles : std_logic_vector(2 downto 0);
|
|
|
-- Micro code outputs
|
-- Micro code outputs
|
signal MCycles_d : std_logic_vector(2 downto 0);
|
signal MCycles_d : std_logic_vector(2 downto 0);
|
signal TStates : std_logic_vector(2 downto 0);
|
signal TStates : std_logic_vector(2 downto 0);
|
signal IntCycle : std_logic;
|
signal IntCycle : std_logic;
|
signal NMICycle : std_logic;
|
signal NMICycle : std_logic;
|
signal Inc_PC : std_logic;
|
signal Inc_PC : std_logic;
|
signal Inc_WZ : std_logic;
|
signal Inc_WZ : std_logic;
|
signal IncDec_16 : std_logic_vector(3 downto 0);
|
signal IncDec_16 : std_logic_vector(3 downto 0);
|
signal Prefix : std_logic_vector(1 downto 0);
|
signal Prefix : std_logic_vector(1 downto 0);
|
signal Read_To_Acc : std_logic;
|
signal Read_To_Acc : std_logic;
|
signal Read_To_Reg : std_logic;
|
signal Read_To_Reg : std_logic;
|
signal Set_BusB_To : std_logic_vector(3 downto 0);
|
signal Set_BusB_To : std_logic_vector(3 downto 0);
|
signal Set_BusA_To : std_logic_vector(3 downto 0);
|
signal Set_BusA_To : std_logic_vector(3 downto 0);
|
signal ALU_Op : std_logic_vector(3 downto 0);
|
signal ALU_Op : std_logic_vector(3 downto 0);
|
signal Save_ALU : std_logic;
|
signal Save_ALU : std_logic;
|
signal PreserveC : std_logic;
|
signal PreserveC : std_logic;
|
signal Arith16 : std_logic;
|
signal Arith16 : std_logic;
|
signal Set_Addr_To : std_logic_vector(2 downto 0);
|
signal Set_Addr_To : std_logic_vector(2 downto 0);
|
signal Jump : std_logic;
|
signal Jump : std_logic;
|
signal JumpE : std_logic;
|
signal JumpE : std_logic;
|
signal JumpXY : std_logic;
|
signal JumpXY : std_logic;
|
signal Call : std_logic;
|
signal Call : std_logic;
|
signal RstP : std_logic;
|
signal RstP : std_logic;
|
signal LDZ : std_logic;
|
signal LDZ : std_logic;
|
signal LDW : std_logic;
|
signal LDW : std_logic;
|
signal LDSPHL : std_logic;
|
signal LDSPHL : std_logic;
|
signal IORQ_i : std_logic;
|
signal IORQ_i : std_logic;
|
signal Special_LD : std_logic_vector(2 downto 0);
|
signal Special_LD : std_logic_vector(2 downto 0);
|
signal ExchangeDH : std_logic;
|
signal ExchangeDH : std_logic;
|
signal ExchangeRp : std_logic;
|
signal ExchangeRp : std_logic;
|
signal ExchangeAF : std_logic;
|
signal ExchangeAF : std_logic;
|
signal ExchangeRS : std_logic;
|
signal ExchangeRS : std_logic;
|
signal I_DJNZ : std_logic;
|
signal I_DJNZ : std_logic;
|
signal I_CPL : std_logic;
|
signal I_CPL : std_logic;
|
signal I_CCF : std_logic;
|
signal I_CCF : std_logic;
|
signal I_SCF : std_logic;
|
signal I_SCF : std_logic;
|
signal I_RETN : std_logic;
|
signal I_RETN : std_logic;
|
signal I_BT : std_logic;
|
signal I_BT : std_logic;
|
signal I_BC : std_logic;
|
signal I_BC : std_logic;
|
signal I_BTR : std_logic;
|
signal I_BTR : std_logic;
|
signal I_RLD : std_logic;
|
signal I_RLD : std_logic;
|
signal I_RRD : std_logic;
|
signal I_RRD : std_logic;
|
signal I_INRC : std_logic;
|
signal I_INRC : std_logic;
|
signal SetDI : std_logic;
|
signal SetDI : std_logic;
|
signal SetEI : std_logic;
|
signal SetEI : std_logic;
|
signal IMode : std_logic_vector(1 downto 0);
|
signal IMode : std_logic_vector(1 downto 0);
|
signal Halt : std_logic;
|
signal Halt : std_logic;
|
|
|
begin
|
begin
|
|
|
mcode : T80_MCode
|
mcode : T80_MCode
|
generic map(
|
generic map(
|
Mode => Mode,
|
Mode => Mode,
|
Flag_C => Flag_C,
|
Flag_C => Flag_C,
|
Flag_N => Flag_N,
|
Flag_N => Flag_N,
|
Flag_P => Flag_P,
|
Flag_P => Flag_P,
|
Flag_X => Flag_X,
|
Flag_X => Flag_X,
|
Flag_H => Flag_H,
|
Flag_H => Flag_H,
|
Flag_Y => Flag_Y,
|
Flag_Y => Flag_Y,
|
Flag_Z => Flag_Z,
|
Flag_Z => Flag_Z,
|
Flag_S => Flag_S)
|
Flag_S => Flag_S)
|
port map(
|
port map(
|
IR => IR,
|
IR => IR,
|
ISet => ISet,
|
ISet => ISet,
|
MCycle => MCycle,
|
MCycle => MCycle,
|
F => F,
|
F => F,
|
NMICycle => NMICycle,
|
NMICycle => NMICycle,
|
IntCycle => IntCycle,
|
IntCycle => IntCycle,
|
MCycles => MCycles_d,
|
MCycles => MCycles_d,
|
TStates => TStates,
|
TStates => TStates,
|
Prefix => Prefix,
|
Prefix => Prefix,
|
Inc_PC => Inc_PC,
|
Inc_PC => Inc_PC,
|
Inc_WZ => Inc_WZ,
|
Inc_WZ => Inc_WZ,
|
IncDec_16 => IncDec_16,
|
IncDec_16 => IncDec_16,
|
Read_To_Acc => Read_To_Acc,
|
Read_To_Acc => Read_To_Acc,
|
Read_To_Reg => Read_To_Reg,
|
Read_To_Reg => Read_To_Reg,
|
Set_BusB_To => Set_BusB_To,
|
Set_BusB_To => Set_BusB_To,
|
Set_BusA_To => Set_BusA_To,
|
Set_BusA_To => Set_BusA_To,
|
ALU_Op => ALU_Op,
|
ALU_Op => ALU_Op,
|
Save_ALU => Save_ALU,
|
Save_ALU => Save_ALU,
|
PreserveC => PreserveC,
|
PreserveC => PreserveC,
|
Arith16 => Arith16,
|
Arith16 => Arith16,
|
Set_Addr_To => Set_Addr_To,
|
Set_Addr_To => Set_Addr_To,
|
IORQ => IORQ_i,
|
IORQ => IORQ_i,
|
Jump => Jump,
|
Jump => Jump,
|
JumpE => JumpE,
|
JumpE => JumpE,
|
JumpXY => JumpXY,
|
JumpXY => JumpXY,
|
Call => Call,
|
Call => Call,
|
RstP => RstP,
|
RstP => RstP,
|
LDZ => LDZ,
|
LDZ => LDZ,
|
LDW => LDW,
|
LDW => LDW,
|
LDSPHL => LDSPHL,
|
LDSPHL => LDSPHL,
|
Special_LD => Special_LD,
|
Special_LD => Special_LD,
|
ExchangeDH => ExchangeDH,
|
ExchangeDH => ExchangeDH,
|
ExchangeRp => ExchangeRp,
|
ExchangeRp => ExchangeRp,
|
ExchangeAF => ExchangeAF,
|
ExchangeAF => ExchangeAF,
|
ExchangeRS => ExchangeRS,
|
ExchangeRS => ExchangeRS,
|
I_DJNZ => I_DJNZ,
|
I_DJNZ => I_DJNZ,
|
I_CPL => I_CPL,
|
I_CPL => I_CPL,
|
I_CCF => I_CCF,
|
I_CCF => I_CCF,
|
I_SCF => I_SCF,
|
I_SCF => I_SCF,
|
I_RETN => I_RETN,
|
I_RETN => I_RETN,
|
I_BT => I_BT,
|
I_BT => I_BT,
|
I_BC => I_BC,
|
I_BC => I_BC,
|
I_BTR => I_BTR,
|
I_BTR => I_BTR,
|
I_RLD => I_RLD,
|
I_RLD => I_RLD,
|
I_RRD => I_RRD,
|
I_RRD => I_RRD,
|
I_INRC => I_INRC,
|
I_INRC => I_INRC,
|
SetDI => SetDI,
|
SetDI => SetDI,
|
SetEI => SetEI,
|
SetEI => SetEI,
|
IMode => IMode,
|
IMode => IMode,
|
Halt => Halt,
|
Halt => Halt,
|
NoRead => NoRead,
|
NoRead => NoRead,
|
Write => Write);
|
Write => Write);
|
|
|
alu : T80_ALU
|
alu : T80_ALU
|
generic map(
|
generic map(
|
Mode => Mode,
|
Mode => Mode,
|
Flag_C => Flag_C,
|
Flag_C => Flag_C,
|
Flag_N => Flag_N,
|
Flag_N => Flag_N,
|
Flag_P => Flag_P,
|
Flag_P => Flag_P,
|
Flag_X => Flag_X,
|
Flag_X => Flag_X,
|
Flag_H => Flag_H,
|
Flag_H => Flag_H,
|
Flag_Y => Flag_Y,
|
Flag_Y => Flag_Y,
|
Flag_Z => Flag_Z,
|
Flag_Z => Flag_Z,
|
Flag_S => Flag_S)
|
Flag_S => Flag_S)
|
port map(
|
port map(
|
Arith16 => Arith16_r,
|
Arith16 => Arith16_r,
|
Z16 => Z16_r,
|
Z16 => Z16_r,
|
ALU_Op => ALU_Op_r,
|
ALU_Op => ALU_Op_r,
|
IR => IR(5 downto 0),
|
IR => IR(5 downto 0),
|
ISet => ISet,
|
ISet => ISet,
|
BusA => BusA,
|
BusA => BusA,
|
BusB => BusB,
|
BusB => BusB,
|
F_In => F,
|
F_In => F,
|
Q => ALU_Q,
|
Q => ALU_Q,
|
F_Out => F_Out);
|
F_Out => F_Out);
|
|
|
ClkEn <= CEN and not BusAck;
|
ClkEn <= CEN and not BusAck;
|
|
|
T_Res <= '1' when TState = unsigned(TStates) else '0';
|
T_Res <= '1' when TState = unsigned(TStates) else '0';
|
|
|
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
|
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
|
((Set_Addr_To = aXY) or
|
((Set_Addr_To = aXY) or
|
(MCycle = "001" and IR = "11001011") or
|
(MCycle = "001" and IR = "11001011") or
|
(MCycle = "001" and IR = "00110110")) else '0';
|
(MCycle = "001" and IR = "00110110")) else '0';
|
|
|
Save_Mux <= BusB when ExchangeRp = '1' else
|
Save_Mux <= BusB when ExchangeRp = '1' else
|
DI_Reg when Save_ALU_r = '0' else
|
DI_Reg when Save_ALU_r = '0' else
|
ALU_Q;
|
ALU_Q;
|
|
|
process (RESET_n, CLK_n)
|
process (RESET_n, CLK_n)
|
begin
|
begin
|
if RESET_n = '0' then
|
if RESET_n = '0' then
|
PC <= (others => '0'); -- Program Counter
|
PC <= (others => '0'); -- Program Counter
|
A <= (others => '0');
|
A <= (others => '0');
|
TmpAddr <= (others => '0');
|
TmpAddr <= (others => '0');
|
IR <= "00000000";
|
IR <= "00000000";
|
ISet <= "00";
|
ISet <= "00";
|
XY_State <= "00";
|
XY_State <= "00";
|
IStatus <= "00";
|
IStatus <= "00";
|
MCycles <= "000";
|
MCycles <= "000";
|
DO <= "00000000";
|
DO <= "00000000";
|
|
|
ACC <= (others => '1');
|
ACC <= (others => '1');
|
F <= (others => '1');
|
F <= (others => '1');
|
Ap <= (others => '1');
|
Ap <= (others => '1');
|
Fp <= (others => '1');
|
Fp <= (others => '1');
|
I <= (others => '0');
|
I <= (others => '0');
|
R <= (others => '0');
|
R <= (others => '0');
|
SP <= (others => '1');
|
SP <= (others => '1');
|
Alternate <= '0';
|
Alternate <= '0';
|
|
|
Read_To_Reg_r <= "00000";
|
Read_To_Reg_r <= "00000";
|
F <= (others => '1');
|
F <= (others => '1');
|
Arith16_r <= '0';
|
Arith16_r <= '0';
|
BTR_r <= '0';
|
BTR_r <= '0';
|
Z16_r <= '0';
|
Z16_r <= '0';
|
ALU_Op_r <= "0000";
|
ALU_Op_r <= "0000";
|
Save_ALU_r <= '0';
|
Save_ALU_r <= '0';
|
PreserveC_r <= '0';
|
PreserveC_r <= '0';
|
XY_Ind <= '0';
|
XY_Ind <= '0';
|
|
|
elsif CLK_n'event and CLK_n = '1' then
|
elsif CLK_n'event and CLK_n = '1' then
|
|
|
if ClkEn = '1' then
|
if ClkEn = '1' then
|
|
|
ALU_Op_r <= "0000";
|
ALU_Op_r <= "0000";
|
Save_ALU_r <= '0';
|
Save_ALU_r <= '0';
|
Read_To_Reg_r <= "00000";
|
Read_To_Reg_r <= "00000";
|
|
|
MCycles <= MCycles_d;
|
MCycles <= MCycles_d;
|
|
|
if IMode /= "11" then
|
if IMode /= "11" then
|
IStatus <= IMode;
|
IStatus <= IMode;
|
end if;
|
end if;
|
|
|
Arith16_r <= Arith16;
|
Arith16_r <= Arith16;
|
PreserveC_r <= PreserveC;
|
PreserveC_r <= PreserveC;
|
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
|
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
|
Z16_r <= '1';
|
Z16_r <= '1';
|
else
|
else
|
Z16_r <= '0';
|
Z16_r <= '0';
|
end if;
|
end if;
|
|
|
if MCycle = "001" and TState(2) = '0' then
|
if MCycle = "001" and TState(2) = '0' then
|
-- MCycle = 1 and TState = 1, 2, or 3
|
-- MCycle = 1 and TState = 1, 2, or 3
|
|
|
if TState = 2 and Wait_n = '1' then
|
if TState = 2 and Wait_n = '1' then
|
if Mode < 2 then
|
if Mode < 2 then
|
A(7 downto 0) <= std_logic_vector(R);
|
A(7 downto 0) <= std_logic_vector(R);
|
A(15 downto 8) <= I;
|
A(15 downto 8) <= I;
|
R(6 downto 0) <= R(6 downto 0) + 1;
|
R(6 downto 0) <= R(6 downto 0) + 1;
|
end if;
|
end if;
|
|
|
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
|
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
|
PC <= PC + 1;
|
PC <= PC + 1;
|
end if;
|
end if;
|
|
|
if IntCycle = '1' and IStatus = "01" then
|
if IntCycle = '1' and IStatus = "01" then
|
IR <= "11111111";
|
IR <= "11111111";
|
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
|
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
|
IR <= "00000000";
|
IR <= "00000000";
|
else
|
else
|
IR <= DInst;
|
IR <= DInst;
|
end if;
|
end if;
|
|
|
ISet <= "00";
|
ISet <= "00";
|
if Prefix /= "00" then
|
if Prefix /= "00" then
|
if Prefix = "11" then
|
if Prefix = "11" then
|
if IR(5) = '1' then
|
if IR(5) = '1' then
|
XY_State <= "10";
|
XY_State <= "10";
|
else
|
else
|
XY_State <= "01";
|
XY_State <= "01";
|
end if;
|
end if;
|
else
|
else
|
if Prefix = "10" then
|
if Prefix = "10" then
|
XY_State <= "00";
|
XY_State <= "00";
|
XY_Ind <= '0';
|
XY_Ind <= '0';
|
end if;
|
end if;
|
ISet <= Prefix;
|
ISet <= Prefix;
|
end if;
|
end if;
|
else
|
else
|
XY_State <= "00";
|
XY_State <= "00";
|
XY_Ind <= '0';
|
XY_Ind <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
else
|
else
|
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
|
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
|
|
|
if MCycle = "110" then
|
if MCycle = "110" then
|
XY_Ind <= '1';
|
XY_Ind <= '1';
|
if Prefix = "01" then
|
if Prefix = "01" then
|
ISet <= "01";
|
ISet <= "01";
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if T_Res = '1' then
|
if T_Res = '1' then
|
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
|
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
|
if Jump = '1' then
|
if Jump = '1' then
|
A(15 downto 8) <= DI_Reg;
|
A(15 downto 8) <= DI_Reg;
|
A(7 downto 0) <= TmpAddr(7 downto 0);
|
A(7 downto 0) <= TmpAddr(7 downto 0);
|
PC(15 downto 8) <= unsigned(DI_Reg);
|
PC(15 downto 8) <= unsigned(DI_Reg);
|
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
|
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
|
elsif JumpXY = '1' then
|
elsif JumpXY = '1' then
|
A <= RegBusC;
|
A <= RegBusC;
|
PC <= unsigned(RegBusC);
|
PC <= unsigned(RegBusC);
|
elsif Call = '1' or RstP = '1' then
|
elsif Call = '1' or RstP = '1' then
|
A <= TmpAddr;
|
A <= TmpAddr;
|
PC <= unsigned(TmpAddr);
|
PC <= unsigned(TmpAddr);
|
elsif MCycle = MCycles and NMICycle = '1' then
|
elsif MCycle = MCycles and NMICycle = '1' then
|
A <= "0000000001100110";
|
A <= "0000000001100110";
|
PC <= "0000000001100110";
|
PC <= "0000000001100110";
|
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
|
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
|
A(15 downto 8) <= I;
|
A(15 downto 8) <= I;
|
A(7 downto 0) <= TmpAddr(7 downto 0);
|
A(7 downto 0) <= TmpAddr(7 downto 0);
|
PC(15 downto 8) <= unsigned(I);
|
PC(15 downto 8) <= unsigned(I);
|
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
|
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
|
else
|
else
|
case Set_Addr_To is
|
case Set_Addr_To is
|
when aXY =>
|
when aXY =>
|
if XY_State = "00" then
|
if XY_State = "00" then
|
A <= RegBusC;
|
A <= RegBusC;
|
else
|
else
|
if NextIs_XY_Fetch = '1' then
|
if NextIs_XY_Fetch = '1' then
|
A <= std_logic_vector(PC);
|
A <= std_logic_vector(PC);
|
else
|
else
|
A <= TmpAddr;
|
A <= TmpAddr;
|
end if;
|
end if;
|
end if;
|
end if;
|
when aIOA =>
|
when aIOA =>
|
if Mode = 3 then
|
if Mode = 3 then
|
-- Memory map I/O on GBZ80
|
-- Memory map I/O on GBZ80
|
A(15 downto 8) <= (others => '1');
|
A(15 downto 8) <= (others => '1');
|
elsif Mode = 2 then
|
elsif Mode = 2 then
|
-- Duplicate I/O address on 8080
|
-- Duplicate I/O address on 8080
|
A(15 downto 8) <= DI_Reg;
|
A(15 downto 8) <= DI_Reg;
|
else
|
else
|
A(15 downto 8) <= ACC;
|
A(15 downto 8) <= ACC;
|
end if;
|
end if;
|
A(7 downto 0) <= DI_Reg;
|
A(7 downto 0) <= DI_Reg;
|
when aSP =>
|
when aSP =>
|
A <= std_logic_vector(SP);
|
A <= std_logic_vector(SP);
|
when aBC =>
|
when aBC =>
|
if Mode = 3 and IORQ_i = '1' then
|
if Mode = 3 and IORQ_i = '1' then
|
-- Memory map I/O on GBZ80
|
-- Memory map I/O on GBZ80
|
A(15 downto 8) <= (others => '1');
|
A(15 downto 8) <= (others => '1');
|
A(7 downto 0) <= RegBusC(7 downto 0);
|
A(7 downto 0) <= RegBusC(7 downto 0);
|
else
|
else
|
A <= RegBusC;
|
A <= RegBusC;
|
end if;
|
end if;
|
when aDE =>
|
when aDE =>
|
A <= RegBusC;
|
A <= RegBusC;
|
when aZI =>
|
when aZI =>
|
if Inc_WZ = '1' then
|
if Inc_WZ = '1' then
|
A <= std_logic_vector(unsigned(TmpAddr) + 1);
|
A <= std_logic_vector(unsigned(TmpAddr) + 1);
|
else
|
else
|
A(15 downto 8) <= DI_Reg;
|
A(15 downto 8) <= DI_Reg;
|
A(7 downto 0) <= TmpAddr(7 downto 0);
|
A(7 downto 0) <= TmpAddr(7 downto 0);
|
end if;
|
end if;
|
when others =>
|
when others =>
|
A <= std_logic_vector(PC);
|
A <= std_logic_vector(PC);
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
Save_ALU_r <= Save_ALU;
|
Save_ALU_r <= Save_ALU;
|
ALU_Op_r <= ALU_Op;
|
ALU_Op_r <= ALU_Op;
|
|
|
if I_CPL = '1' then
|
if I_CPL = '1' then
|
-- CPL
|
-- CPL
|
ACC <= not ACC;
|
ACC <= not ACC;
|
F(Flag_Y) <= not ACC(5);
|
F(Flag_Y) <= not ACC(5);
|
F(Flag_H) <= '1';
|
F(Flag_H) <= '1';
|
F(Flag_X) <= not ACC(3);
|
F(Flag_X) <= not ACC(3);
|
F(Flag_N) <= '1';
|
F(Flag_N) <= '1';
|
end if;
|
end if;
|
if I_CCF = '1' then
|
if I_CCF = '1' then
|
-- CCF
|
-- CCF
|
F(Flag_C) <= not F(Flag_C);
|
F(Flag_C) <= not F(Flag_C);
|
F(Flag_Y) <= ACC(5);
|
F(Flag_Y) <= ACC(5);
|
F(Flag_H) <= F(Flag_C);
|
F(Flag_H) <= F(Flag_C);
|
F(Flag_X) <= ACC(3);
|
F(Flag_X) <= ACC(3);
|
F(Flag_N) <= '0';
|
F(Flag_N) <= '0';
|
end if;
|
end if;
|
if I_SCF = '1' then
|
if I_SCF = '1' then
|
-- SCF
|
-- SCF
|
F(Flag_C) <= '1';
|
F(Flag_C) <= '1';
|
F(Flag_Y) <= ACC(5);
|
F(Flag_Y) <= ACC(5);
|
F(Flag_H) <= '0';
|
F(Flag_H) <= '0';
|
F(Flag_X) <= ACC(3);
|
F(Flag_X) <= ACC(3);
|
F(Flag_N) <= '0';
|
F(Flag_N) <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if TState = 2 and Wait_n = '1' then
|
if TState = 2 and Wait_n = '1' then
|
if ISet = "01" and MCycle = "111" then
|
if ISet = "01" and MCycle = "111" then
|
IR <= DInst;
|
IR <= DInst;
|
end if;
|
end if;
|
if JumpE = '1' then
|
if JumpE = '1' then
|
PC <= unsigned(signed(PC) + signed(DI_Reg));
|
PC <= unsigned(signed(PC) + signed(DI_Reg));
|
elsif Inc_PC = '1' then
|
elsif Inc_PC = '1' then
|
PC <= PC + 1;
|
PC <= PC + 1;
|
end if;
|
end if;
|
if BTR_r = '1' then
|
if BTR_r = '1' then
|
PC <= PC - 2;
|
PC <= PC - 2;
|
end if;
|
end if;
|
if RstP = '1' then
|
if RstP = '1' then
|
TmpAddr <= (others =>'0');
|
TmpAddr <= (others =>'0');
|
TmpAddr(5 downto 3) <= IR(5 downto 3);
|
TmpAddr(5 downto 3) <= IR(5 downto 3);
|
end if;
|
end if;
|
end if;
|
end if;
|
if TState = 3 and MCycle = "110" then
|
if TState = 3 and MCycle = "110" then
|
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
|
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
|
end if;
|
end if;
|
|
|
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
|
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
|
if IncDec_16(2 downto 0) = "111" then
|
if IncDec_16(2 downto 0) = "111" then
|
if IncDec_16(3) = '1' then
|
if IncDec_16(3) = '1' then
|
SP <= SP - 1;
|
SP <= SP - 1;
|
else
|
else
|
SP <= SP + 1;
|
SP <= SP + 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if LDSPHL = '1' then
|
if LDSPHL = '1' then
|
SP <= unsigned(RegBusC);
|
SP <= unsigned(RegBusC);
|
end if;
|
end if;
|
if ExchangeAF = '1' then
|
if ExchangeAF = '1' then
|
Ap <= ACC;
|
Ap <= ACC;
|
ACC <= Ap;
|
ACC <= Ap;
|
Fp <= F;
|
Fp <= F;
|
F <= Fp;
|
F <= Fp;
|
end if;
|
end if;
|
if ExchangeRS = '1' then
|
if ExchangeRS = '1' then
|
Alternate <= not Alternate;
|
Alternate <= not Alternate;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if TState = 3 then
|
if TState = 3 then
|
if LDZ = '1' then
|
if LDZ = '1' then
|
TmpAddr(7 downto 0) <= DI_Reg;
|
TmpAddr(7 downto 0) <= DI_Reg;
|
end if;
|
end if;
|
if LDW = '1' then
|
if LDW = '1' then
|
TmpAddr(15 downto 8) <= DI_Reg;
|
TmpAddr(15 downto 8) <= DI_Reg;
|
end if;
|
end if;
|
|
|
if Special_LD(2) = '1' then
|
if Special_LD(2) = '1' then
|
case Special_LD(1 downto 0) is
|
case Special_LD(1 downto 0) is
|
when "00" =>
|
when "00" =>
|
ACC <= I;
|
ACC <= I;
|
F(Flag_P) <= IntE_FF2;
|
F(Flag_P) <= IntE_FF2;
|
when "01" =>
|
when "01" =>
|
ACC <= std_logic_vector(R);
|
ACC <= std_logic_vector(R);
|
F(Flag_P) <= IntE_FF2;
|
F(Flag_P) <= IntE_FF2;
|
when "10" =>
|
when "10" =>
|
I <= ACC;
|
I <= ACC;
|
when others =>
|
when others =>
|
R <= unsigned(ACC);
|
R <= unsigned(ACC);
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
|
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
|
if Mode = 3 then
|
if Mode = 3 then
|
F(6) <= F_Out(6);
|
F(6) <= F_Out(6);
|
F(5) <= F_Out(5);
|
F(5) <= F_Out(5);
|
F(7) <= F_Out(7);
|
F(7) <= F_Out(7);
|
if PreserveC_r = '0' then
|
if PreserveC_r = '0' then
|
F(4) <= F_Out(4);
|
F(4) <= F_Out(4);
|
end if;
|
end if;
|
else
|
else
|
F(7 downto 1) <= F_Out(7 downto 1);
|
F(7 downto 1) <= F_Out(7 downto 1);
|
if PreserveC_r = '0' then
|
if PreserveC_r = '0' then
|
F(Flag_C) <= F_Out(0);
|
F(Flag_C) <= F_Out(0);
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
if T_Res = '1' and I_INRC = '1' then
|
if T_Res = '1' and I_INRC = '1' then
|
F(Flag_H) <= '0';
|
F(Flag_H) <= '0';
|
F(Flag_N) <= '0';
|
F(Flag_N) <= '0';
|
if DI_Reg(7 downto 0) = "00000000" then
|
if DI_Reg(7 downto 0) = "00000000" then
|
F(Flag_Z) <= '1';
|
F(Flag_Z) <= '1';
|
else
|
else
|
F(Flag_Z) <= '0';
|
F(Flag_Z) <= '0';
|
end if;
|
end if;
|
F(Flag_S) <= DI_Reg(7);
|
F(Flag_S) <= DI_Reg(7);
|
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
|
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
|
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
|
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
|
end if;
|
end if;
|
|
|
if TState = 1 then
|
if TState = 1 then
|
DO <= BusB;
|
DO <= BusB;
|
if I_RLD = '1' then
|
if I_RLD = '1' then
|
DO(3 downto 0) <= BusA(3 downto 0);
|
DO(3 downto 0) <= BusA(3 downto 0);
|
DO(7 downto 4) <= BusB(3 downto 0);
|
DO(7 downto 4) <= BusB(3 downto 0);
|
end if;
|
end if;
|
if I_RRD = '1' then
|
if I_RRD = '1' then
|
DO(3 downto 0) <= BusB(7 downto 4);
|
DO(3 downto 0) <= BusB(7 downto 4);
|
DO(7 downto 4) <= BusA(3 downto 0);
|
DO(7 downto 4) <= BusA(3 downto 0);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if T_Res = '1' then
|
if T_Res = '1' then
|
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
|
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
|
Read_To_Reg_r(4) <= Read_To_Reg;
|
Read_To_Reg_r(4) <= Read_To_Reg;
|
if Read_To_Acc = '1' then
|
if Read_To_Acc = '1' then
|
Read_To_Reg_r(3 downto 0) <= "0111";
|
Read_To_Reg_r(3 downto 0) <= "0111";
|
Read_To_Reg_r(4) <= '1';
|
Read_To_Reg_r(4) <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if TState = 1 and I_BT = '1' then
|
if TState = 1 and I_BT = '1' then
|
F(Flag_X) <= ALU_Q(3);
|
F(Flag_X) <= ALU_Q(3);
|
F(Flag_Y) <= ALU_Q(1);
|
F(Flag_Y) <= ALU_Q(1);
|
F(Flag_H) <= '0';
|
F(Flag_H) <= '0';
|
F(Flag_N) <= '0';
|
F(Flag_N) <= '0';
|
end if;
|
end if;
|
if I_BC = '1' or I_BT = '1' then
|
if I_BC = '1' or I_BT = '1' then
|
F(Flag_P) <= IncDecZ;
|
F(Flag_P) <= IncDecZ;
|
end if;
|
end if;
|
|
|
if (TState = 1 and Save_ALU_r = '0') or
|
if (TState = 1 and Save_ALU_r = '0') or
|
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
|
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
|
case Read_To_Reg_r is
|
case Read_To_Reg_r is
|
when "10111" =>
|
when "10111" =>
|
ACC <= Save_Mux;
|
ACC <= Save_Mux;
|
when "10110" =>
|
when "10110" =>
|
DO <= Save_Mux;
|
DO <= Save_Mux;
|
when "11000" =>
|
when "11000" =>
|
SP(7 downto 0) <= unsigned(Save_Mux);
|
SP(7 downto 0) <= unsigned(Save_Mux);
|
when "11001" =>
|
when "11001" =>
|
SP(15 downto 8) <= unsigned(Save_Mux);
|
SP(15 downto 8) <= unsigned(Save_Mux);
|
when "11011" =>
|
when "11011" =>
|
F <= Save_Mux;
|
F <= Save_Mux;
|
when others =>
|
when others =>
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
|
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
--
|
--
|
-- BC('), DE('), HL('), IX and IY
|
-- BC('), DE('), HL('), IX and IY
|
--
|
--
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
process (CLK_n)
|
process (CLK_n)
|
begin
|
begin
|
if CLK_n'event and CLK_n = '1' then
|
if CLK_n'event and CLK_n = '1' then
|
if ClkEn = '1' then
|
if ClkEn = '1' then
|
-- Bus A / Write
|
-- Bus A / Write
|
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
|
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
|
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
|
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
|
RegAddrA_r <= XY_State(1) & "11";
|
RegAddrA_r <= XY_State(1) & "11";
|
end if;
|
end if;
|
|
|
-- Bus B
|
-- Bus B
|
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
|
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
|
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
|
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
|
RegAddrB_r <= XY_State(1) & "11";
|
RegAddrB_r <= XY_State(1) & "11";
|
end if;
|
end if;
|
|
|
-- Address from register
|
-- Address from register
|
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
|
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
|
-- Jump (HL), LD SP,HL
|
-- Jump (HL), LD SP,HL
|
if (JumpXY = '1' or LDSPHL = '1') then
|
if (JumpXY = '1' or LDSPHL = '1') then
|
RegAddrC <= Alternate & "10";
|
RegAddrC <= Alternate & "10";
|
end if;
|
end if;
|
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
|
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
|
RegAddrC <= XY_State(1) & "11";
|
RegAddrC <= XY_State(1) & "11";
|
end if;
|
end if;
|
|
|
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
|
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
|
IncDecZ <= F_Out(Flag_Z);
|
IncDecZ <= F_Out(Flag_Z);
|
end if;
|
end if;
|
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
|
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
|
if ID16 = 0 then
|
if ID16 = 0 then
|
IncDecZ <= '0';
|
IncDecZ <= '0';
|
else
|
else
|
IncDecZ <= '1';
|
IncDecZ <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
RegBusA_r <= RegBusA;
|
RegBusA_r <= RegBusA;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
RegAddrA <=
|
RegAddrA <=
|
-- 16 bit increment/decrement
|
-- 16 bit increment/decrement
|
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
|
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
|
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
|
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
|
XY_State(1) & "11" when (TState = 2 or
|
XY_State(1) & "11" when (TState = 2 or
|
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
|
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
|
-- EX HL,DL
|
-- EX HL,DL
|
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
|
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
|
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
|
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
|
-- Bus A / Write
|
-- Bus A / Write
|
RegAddrA_r;
|
RegAddrA_r;
|
|
|
RegAddrB <=
|
RegAddrB <=
|
-- EX HL,DL
|
-- EX HL,DL
|
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
|
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
|
-- Bus B
|
-- Bus B
|
RegAddrB_r;
|
RegAddrB_r;
|
|
|
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
|
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
|
signed(RegBusA) + 1;
|
signed(RegBusA) + 1;
|
|
|
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
|
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
|
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
|
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
|
begin
|
begin
|
RegWEH <= '0';
|
RegWEH <= '0';
|
RegWEL <= '0';
|
RegWEL <= '0';
|
if (TState = 1 and Save_ALU_r = '0') or
|
if (TState = 1 and Save_ALU_r = '0') or
|
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
|
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
|
case Read_To_Reg_r is
|
case Read_To_Reg_r is
|
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
|
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
|
RegWEH <= not Read_To_Reg_r(0);
|
RegWEH <= not Read_To_Reg_r(0);
|
RegWEL <= Read_To_Reg_r(0);
|
RegWEL <= Read_To_Reg_r(0);
|
when others =>
|
when others =>
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
|
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
|
RegWEH <= '1';
|
RegWEH <= '1';
|
RegWEL <= '1';
|
RegWEL <= '1';
|
end if;
|
end if;
|
|
|
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
|
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
|
case IncDec_16(1 downto 0) is
|
case IncDec_16(1 downto 0) is
|
when "00" | "01" | "10" =>
|
when "00" | "01" | "10" =>
|
RegWEH <= '1';
|
RegWEH <= '1';
|
RegWEL <= '1';
|
RegWEL <= '1';
|
when others =>
|
when others =>
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
process (Save_Mux, RegBusB, RegBusA_r, ID16,
|
process (Save_Mux, RegBusB, RegBusA_r, ID16,
|
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
|
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
|
begin
|
begin
|
RegDIH <= Save_Mux;
|
RegDIH <= Save_Mux;
|
RegDIL <= Save_Mux;
|
RegDIL <= Save_Mux;
|
|
|
if ExchangeDH = '1' and TState = 3 then
|
if ExchangeDH = '1' and TState = 3 then
|
RegDIH <= RegBusB(15 downto 8);
|
RegDIH <= RegBusB(15 downto 8);
|
RegDIL <= RegBusB(7 downto 0);
|
RegDIL <= RegBusB(7 downto 0);
|
end if;
|
end if;
|
if ExchangeDH = '1' and TState = 4 then
|
if ExchangeDH = '1' and TState = 4 then
|
RegDIH <= RegBusA_r(15 downto 8);
|
RegDIH <= RegBusA_r(15 downto 8);
|
RegDIL <= RegBusA_r(7 downto 0);
|
RegDIL <= RegBusA_r(7 downto 0);
|
end if;
|
end if;
|
|
|
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
|
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
|
RegDIH <= std_logic_vector(ID16(15 downto 8));
|
RegDIH <= std_logic_vector(ID16(15 downto 8));
|
RegDIL <= std_logic_vector(ID16(7 downto 0));
|
RegDIL <= std_logic_vector(ID16(7 downto 0));
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
Regs : T80_Reg
|
Regs : T80_Reg
|
port map(
|
port map(
|
Clk => CLK_n,
|
Clk => CLK_n,
|
CEN => ClkEn,
|
CEN => ClkEn,
|
WEH => RegWEH,
|
WEH => RegWEH,
|
WEL => RegWEL,
|
WEL => RegWEL,
|
AddrA => RegAddrA,
|
AddrA => RegAddrA,
|
AddrB => RegAddrB,
|
AddrB => RegAddrB,
|
AddrC => RegAddrC,
|
AddrC => RegAddrC,
|
DIH => RegDIH,
|
DIH => RegDIH,
|
DIL => RegDIL,
|
DIL => RegDIL,
|
DOAH => RegBusA(15 downto 8),
|
DOAH => RegBusA(15 downto 8),
|
DOAL => RegBusA(7 downto 0),
|
DOAL => RegBusA(7 downto 0),
|
DOBH => RegBusB(15 downto 8),
|
DOBH => RegBusB(15 downto 8),
|
DOBL => RegBusB(7 downto 0),
|
DOBL => RegBusB(7 downto 0),
|
DOCH => RegBusC(15 downto 8),
|
DOCH => RegBusC(15 downto 8),
|
DOCL => RegBusC(7 downto 0));
|
DOCL => RegBusC(7 downto 0));
|
|
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
--
|
--
|
-- Buses
|
-- Buses
|
--
|
--
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
process (CLK_n)
|
process (CLK_n)
|
begin
|
begin
|
if CLK_n'event and CLK_n = '1' then
|
if CLK_n'event and CLK_n = '1' then
|
if ClkEn = '1' then
|
if ClkEn = '1' then
|
case Set_BusB_To is
|
case Set_BusB_To is
|
when "0111" =>
|
when "0111" =>
|
BusB <= ACC;
|
BusB <= ACC;
|
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
|
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
|
if Set_BusB_To(0) = '1' then
|
if Set_BusB_To(0) = '1' then
|
BusB <= RegBusB(7 downto 0);
|
BusB <= RegBusB(7 downto 0);
|
else
|
else
|
BusB <= RegBusB(15 downto 8);
|
BusB <= RegBusB(15 downto 8);
|
end if;
|
end if;
|
when "0110" =>
|
when "0110" =>
|
BusB <= DI_Reg;
|
BusB <= DI_Reg;
|
when "1000" =>
|
when "1000" =>
|
BusB <= std_logic_vector(SP(7 downto 0));
|
BusB <= std_logic_vector(SP(7 downto 0));
|
when "1001" =>
|
when "1001" =>
|
BusB <= std_logic_vector(SP(15 downto 8));
|
BusB <= std_logic_vector(SP(15 downto 8));
|
when "1010" =>
|
when "1010" =>
|
BusB <= "00000001";
|
BusB <= "00000001";
|
when "1011" =>
|
when "1011" =>
|
BusB <= F;
|
BusB <= F;
|
when "1100" =>
|
when "1100" =>
|
BusB <= std_logic_vector(PC(7 downto 0));
|
BusB <= std_logic_vector(PC(7 downto 0));
|
when "1101" =>
|
when "1101" =>
|
BusB <= std_logic_vector(PC(15 downto 8));
|
BusB <= std_logic_vector(PC(15 downto 8));
|
when "1110" =>
|
when "1110" =>
|
BusB <= "00000000";
|
BusB <= "00000000";
|
when others =>
|
when others =>
|
BusB <= "--------";
|
BusB <= "--------";
|
end case;
|
end case;
|
|
|
case Set_BusA_To is
|
case Set_BusA_To is
|
when "0111" =>
|
when "0111" =>
|
BusA <= ACC;
|
BusA <= ACC;
|
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
|
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
|
if Set_BusA_To(0) = '1' then
|
if Set_BusA_To(0) = '1' then
|
BusA <= RegBusA(7 downto 0);
|
BusA <= RegBusA(7 downto 0);
|
else
|
else
|
BusA <= RegBusA(15 downto 8);
|
BusA <= RegBusA(15 downto 8);
|
end if;
|
end if;
|
when "0110" =>
|
when "0110" =>
|
BusA <= DI_Reg;
|
BusA <= DI_Reg;
|
when "1000" =>
|
when "1000" =>
|
BusA <= std_logic_vector(SP(7 downto 0));
|
BusA <= std_logic_vector(SP(7 downto 0));
|
when "1001" =>
|
when "1001" =>
|
BusA <= std_logic_vector(SP(15 downto 8));
|
BusA <= std_logic_vector(SP(15 downto 8));
|
when "1010" =>
|
when "1010" =>
|
BusA <= "00000000";
|
BusA <= "00000000";
|
when others =>
|
when others =>
|
BusB <= "--------";
|
BusB <= "--------";
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
--
|
--
|
-- Generate external control signals
|
-- Generate external control signals
|
--
|
--
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
process (RESET_n,CLK_n)
|
process (RESET_n,CLK_n)
|
begin
|
begin
|
if RESET_n = '0' then
|
if RESET_n = '0' then
|
RFSH_n <= '1';
|
RFSH_n <= '1';
|
elsif CLK_n'event and CLK_n = '1' then
|
elsif CLK_n'event and CLK_n = '1' then
|
if CEN = '1' then
|
if CEN = '1' then
|
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
|
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
|
RFSH_n <= '0';
|
RFSH_n <= '0';
|
else
|
else
|
RFSH_n <= '1';
|
RFSH_n <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
MC <= std_logic_vector(MCycle);
|
MC <= std_logic_vector(MCycle);
|
TS <= std_logic_vector(TState);
|
TS <= std_logic_vector(TState);
|
DI_Reg <= DI;
|
DI_Reg <= DI;
|
HALT_n <= not Halt_FF;
|
HALT_n <= not Halt_FF;
|
BUSAK_n <= not BusAck;
|
BUSAK_n <= not BusAck;
|
IntCycle_n <= not IntCycle;
|
IntCycle_n <= not IntCycle;
|
IntE <= IntE_FF1;
|
IntE <= IntE_FF1;
|
IORQ <= IORQ_i;
|
IORQ <= IORQ_i;
|
Stop <= I_DJNZ;
|
Stop <= I_DJNZ;
|
|
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
--
|
--
|
-- Syncronise inputs
|
-- Syncronise inputs
|
--
|
--
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
process (RESET_n, CLK_n)
|
process (RESET_n, CLK_n)
|
variable OldNMI_n : std_logic;
|
variable OldNMI_n : std_logic;
|
begin
|
begin
|
if RESET_n = '0' then
|
if RESET_n = '0' then
|
BusReq_s <= '0';
|
BusReq_s <= '0';
|
INT_s <= '0';
|
INT_s <= '0';
|
NMI_s <= '0';
|
NMI_s <= '0';
|
OldNMI_n := '0';
|
OldNMI_n := '0';
|
elsif CLK_n'event and CLK_n = '1' then
|
elsif CLK_n'event and CLK_n = '1' then
|
if CEN = '1' then
|
if CEN = '1' then
|
BusReq_s <= not BUSRQ_n;
|
BusReq_s <= not BUSRQ_n;
|
INT_s <= not INT_n;
|
INT_s <= not INT_n;
|
if NMICycle = '1' then
|
if NMICycle = '1' then
|
NMI_s <= '0';
|
NMI_s <= '0';
|
elsif NMI_n = '0' and OldNMI_n = '1' then
|
elsif NMI_n = '0' and OldNMI_n = '1' then
|
NMI_s <= '1';
|
NMI_s <= '1';
|
end if;
|
end if;
|
OldNMI_n := NMI_n;
|
OldNMI_n := NMI_n;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
--
|
--
|
-- Main state machine
|
-- Main state machine
|
--
|
--
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
process (RESET_n, CLK_n)
|
process (RESET_n, CLK_n)
|
begin
|
begin
|
if RESET_n = '0' then
|
if RESET_n = '0' then
|
MCycle <= "001";
|
MCycle <= "001";
|
TState <= "000";
|
TState <= "000";
|
Pre_XY_F_M <= "000";
|
Pre_XY_F_M <= "000";
|
Halt_FF <= '0';
|
Halt_FF <= '0';
|
BusAck <= '0';
|
BusAck <= '0';
|
NMICycle <= '0';
|
NMICycle <= '0';
|
IntCycle <= '0';
|
IntCycle <= '0';
|
IntE_FF1 <= '0';
|
IntE_FF1 <= '0';
|
IntE_FF2 <= '0';
|
IntE_FF2 <= '0';
|
No_BTR <= '0';
|
No_BTR <= '0';
|
Auto_Wait_t1 <= '0';
|
Auto_Wait_t1 <= '0';
|
Auto_Wait_t2 <= '0';
|
Auto_Wait_t2 <= '0';
|
M1_n <= '1';
|
M1_n <= '1';
|
elsif CLK_n'event and CLK_n = '1' then
|
elsif CLK_n'event and CLK_n = '1' then
|
if CEN = '1' then
|
if CEN = '1' then
|
Auto_Wait_t1 <= Auto_Wait;
|
Auto_Wait_t1 <= Auto_Wait;
|
Auto_Wait_t2 <= Auto_Wait_t1;
|
Auto_Wait_t2 <= Auto_Wait_t1;
|
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
|
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
|
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
|
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
|
(I_BTR and (not IR(4) or F(Flag_Z)));
|
(I_BTR and (not IR(4) or F(Flag_Z)));
|
if TState = 2 then
|
if TState = 2 then
|
if SetEI = '1' then
|
if SetEI = '1' then
|
IntE_FF1 <= '1';
|
IntE_FF1 <= '1';
|
IntE_FF2 <= '1';
|
IntE_FF2 <= '1';
|
end if;
|
end if;
|
if I_RETN = '1' then
|
if I_RETN = '1' then
|
IntE_FF1 <= IntE_FF2;
|
IntE_FF1 <= IntE_FF2;
|
end if;
|
end if;
|
end if;
|
end if;
|
if TState = 3 then
|
if TState = 3 then
|
if SetDI = '1' then
|
if SetDI = '1' then
|
IntE_FF1 <= '0';
|
IntE_FF1 <= '0';
|
IntE_FF2 <= '0';
|
IntE_FF2 <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
if IntCycle = '1' or NMICycle = '1' then
|
if IntCycle = '1' or NMICycle = '1' then
|
Halt_FF <= '0';
|
Halt_FF <= '0';
|
end if;
|
end if;
|
if MCycle = "001" and TState = 2 and Wait_n = '1' then
|
if MCycle = "001" and TState = 2 and Wait_n = '1' then
|
M1_n <= '1';
|
M1_n <= '1';
|
end if;
|
end if;
|
if BusReq_s = '1' and BusAck = '1' then
|
if BusReq_s = '1' and BusAck = '1' then
|
else
|
else
|
BusAck <= '0';
|
BusAck <= '0';
|
if TState = 2 and Wait_n = '0' then
|
if TState = 2 and Wait_n = '0' then
|
elsif T_Res = '1' then
|
elsif T_Res = '1' then
|
if Halt = '1' then
|
if Halt = '1' then
|
Halt_FF <= '1';
|
Halt_FF <= '1';
|
end if;
|
end if;
|
if BusReq_s = '1' then
|
if BusReq_s = '1' then
|
BusAck <= '1';
|
BusAck <= '1';
|
else
|
else
|
TState <= "001";
|
TState <= "001";
|
if NextIs_XY_Fetch = '1' then
|
if NextIs_XY_Fetch = '1' then
|
MCycle <= "110";
|
MCycle <= "110";
|
Pre_XY_F_M <= MCycle;
|
Pre_XY_F_M <= MCycle;
|
if IR = "00110110" and Mode = 0 then
|
if IR = "00110110" and Mode = 0 then
|
Pre_XY_F_M <= "010";
|
Pre_XY_F_M <= "010";
|
end if;
|
end if;
|
elsif (MCycle = "111") or
|
elsif (MCycle = "111") or
|
(MCycle = "110" and Mode = 1 and ISet /= "01") then
|
(MCycle = "110" and Mode = 1 and ISet /= "01") then
|
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
|
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
|
elsif (MCycle = MCycles) or
|
elsif (MCycle = MCycles) or
|
No_BTR = '1' or
|
No_BTR = '1' or
|
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
|
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
|
M1_n <= '0';
|
M1_n <= '0';
|
MCycle <= "001";
|
MCycle <= "001";
|
IntCycle <= '0';
|
IntCycle <= '0';
|
NMICycle <= '0';
|
NMICycle <= '0';
|
if NMI_s = '1' and Prefix = "00" then
|
if NMI_s = '1' and Prefix = "00" then
|
NMICycle <= '1';
|
NMICycle <= '1';
|
IntE_FF1 <= '0';
|
IntE_FF1 <= '0';
|
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
|
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
|
IntCycle <= '1';
|
IntCycle <= '1';
|
IntE_FF1 <= '0';
|
IntE_FF1 <= '0';
|
IntE_FF2 <= '0';
|
IntE_FF2 <= '0';
|
end if;
|
end if;
|
else
|
else
|
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
|
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
|
end if;
|
end if;
|
end if;
|
end if;
|
else
|
else
|
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
|
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
|
|
|
TState <= TState + 1;
|
TState <= TState + 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
if TState = 0 then
|
if TState = 0 then
|
M1_n <= '0';
|
M1_n <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
process (IntCycle, NMICycle, MCycle)
|
process (IntCycle, NMICycle, MCycle)
|
begin
|
begin
|
Auto_Wait <= '0';
|
Auto_Wait <= '0';
|
if IntCycle = '1' or NMICycle = '1' then
|
if IntCycle = '1' or NMICycle = '1' then
|
if MCycle = "001" then
|
if MCycle = "001" then
|
Auto_Wait <= '1';
|
Auto_Wait <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end;
|
end;
|
|
|