--
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--
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-- T80 Registers for Xilinx Select RAM
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-- T80 Registers for Xilinx Select RAM
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--
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--
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-- Version : 0244
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-- Version : 0244
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--
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--
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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--
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- this list of conditions and the following disclaimer.
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--
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- documentation and/or other materials provided with the distribution.
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--
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--
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-- Neither the name of the author nor the names of other contributors may
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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-- specific prior written permission.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- Please report bugs to the author, but before you do so, please
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t51/
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-- http://www.opencores.org/cvsweb.shtml/t51/
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--
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--
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-- Limitations :
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-- Limitations :
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--
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--
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-- File history :
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-- File history :
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--
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--
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-- 0242 : Initial release
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-- 0242 : Initial release
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--
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--
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-- 0244 : Removed UNISIM library and added componet declaration
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-- 0244 : Removed UNISIM library and added componet declaration
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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entity T80_Reg is
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entity T80_Reg is
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port(
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port(
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Clk : in std_logic;
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Clk : in std_logic;
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CEN : in std_logic;
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CEN : in std_logic;
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WEH : in std_logic;
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WEH : in std_logic;
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WEL : in std_logic;
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WEL : in std_logic;
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AddrA : in std_logic_vector(2 downto 0);
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AddrA : in std_logic_vector(2 downto 0);
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AddrB : in std_logic_vector(2 downto 0);
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AddrB : in std_logic_vector(2 downto 0);
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AddrC : in std_logic_vector(2 downto 0);
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AddrC : in std_logic_vector(2 downto 0);
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DIH : in std_logic_vector(7 downto 0);
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DIH : in std_logic_vector(7 downto 0);
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DIL : in std_logic_vector(7 downto 0);
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DIL : in std_logic_vector(7 downto 0);
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DOAH : out std_logic_vector(7 downto 0);
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DOAH : out std_logic_vector(7 downto 0);
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DOAL : out std_logic_vector(7 downto 0);
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DOAL : out std_logic_vector(7 downto 0);
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DOBH : out std_logic_vector(7 downto 0);
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DOBH : out std_logic_vector(7 downto 0);
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DOBL : out std_logic_vector(7 downto 0);
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DOBL : out std_logic_vector(7 downto 0);
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DOCH : out std_logic_vector(7 downto 0);
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DOCH : out std_logic_vector(7 downto 0);
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DOCL : out std_logic_vector(7 downto 0)
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DOCL : out std_logic_vector(7 downto 0)
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);
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);
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end T80_Reg;
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end T80_Reg;
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architecture rtl of T80_Reg is
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architecture rtl of T80_Reg is
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component RAM16X1D
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component RAM16X1D
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port(
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port(
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DPO : out std_ulogic;
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DPO : out std_ulogic;
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SPO : out std_ulogic;
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SPO : out std_ulogic;
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A0 : in std_ulogic;
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A0 : in std_ulogic;
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A1 : in std_ulogic;
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A1 : in std_ulogic;
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A2 : in std_ulogic;
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A2 : in std_ulogic;
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A3 : in std_ulogic;
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A3 : in std_ulogic;
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D : in std_ulogic;
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D : in std_ulogic;
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DPRA0 : in std_ulogic;
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DPRA0 : in std_ulogic;
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DPRA1 : in std_ulogic;
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DPRA1 : in std_ulogic;
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DPRA2 : in std_ulogic;
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DPRA2 : in std_ulogic;
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DPRA3 : in std_ulogic;
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DPRA3 : in std_ulogic;
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WCLK : in std_ulogic;
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WCLK : in std_ulogic;
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WE : in std_ulogic);
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WE : in std_ulogic);
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end component;
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end component;
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signal ENH : std_logic;
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signal ENH : std_logic;
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signal ENL : std_logic;
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signal ENL : std_logic;
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begin
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begin
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ENH <= CEN and WEH;
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ENH <= CEN and WEH;
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ENL <= CEN and WEL;
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ENL <= CEN and WEL;
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bG1: for I in 0 to 7 generate
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bG1: for I in 0 to 7 generate
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begin
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begin
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Reg1H : RAM16X1D
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Reg1H : RAM16X1D
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port map(
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port map(
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DPO => DOBH(i),
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DPO => DOBH(i),
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SPO => DOAH(i),
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SPO => DOAH(i),
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A0 => AddrA(0),
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A0 => AddrA(0),
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A1 => AddrA(1),
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A1 => AddrA(1),
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A2 => AddrA(2),
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A2 => AddrA(2),
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A3 => '0',
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A3 => '0',
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D => DIH(i),
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D => DIH(i),
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DPRA0 => AddrB(0),
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DPRA0 => AddrB(0),
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DPRA1 => AddrB(1),
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DPRA1 => AddrB(1),
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DPRA2 => AddrB(2),
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DPRA2 => AddrB(2),
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DPRA3 => '0',
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DPRA3 => '0',
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WCLK => Clk,
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WCLK => Clk,
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WE => ENH);
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WE => ENH);
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Reg1L : RAM16X1D
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Reg1L : RAM16X1D
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port map(
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port map(
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DPO => DOBL(i),
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DPO => DOBL(i),
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SPO => DOAL(i),
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SPO => DOAL(i),
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A0 => AddrA(0),
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A0 => AddrA(0),
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A1 => AddrA(1),
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A1 => AddrA(1),
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A2 => AddrA(2),
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A2 => AddrA(2),
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A3 => '0',
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A3 => '0',
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D => DIL(i),
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D => DIL(i),
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DPRA0 => AddrB(0),
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DPRA0 => AddrB(0),
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DPRA1 => AddrB(1),
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DPRA1 => AddrB(1),
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DPRA2 => AddrB(2),
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DPRA2 => AddrB(2),
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DPRA3 => '0',
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DPRA3 => '0',
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WCLK => Clk,
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WCLK => Clk,
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WE => ENL);
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WE => ENL);
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Reg2H : RAM16X1D
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Reg2H : RAM16X1D
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port map(
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port map(
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DPO => DOCH(i),
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DPO => DOCH(i),
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SPO => open,
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SPO => open,
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A0 => AddrA(0),
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A0 => AddrA(0),
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A1 => AddrA(1),
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A1 => AddrA(1),
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A2 => AddrA(2),
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A2 => AddrA(2),
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A3 => '0',
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A3 => '0',
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D => DIH(i),
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D => DIH(i),
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DPRA0 => AddrC(0),
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DPRA0 => AddrC(0),
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DPRA1 => AddrC(1),
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DPRA1 => AddrC(1),
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DPRA2 => AddrC(2),
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DPRA2 => AddrC(2),
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DPRA3 => '0',
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DPRA3 => '0',
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WCLK => Clk,
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WCLK => Clk,
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WE => ENH);
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WE => ENH);
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Reg2L : RAM16X1D
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Reg2L : RAM16X1D
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port map(
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port map(
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DPO => DOCL(i),
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DPO => DOCL(i),
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SPO => open,
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SPO => open,
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A0 => AddrA(0),
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A0 => AddrA(0),
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A1 => AddrA(1),
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A1 => AddrA(1),
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A2 => AddrA(2),
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A2 => AddrA(2),
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A3 => '0',
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A3 => '0',
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D => DIL(i),
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D => DIL(i),
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DPRA0 => AddrC(0),
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DPRA0 => AddrC(0),
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DPRA1 => AddrC(1),
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DPRA1 => AddrC(1),
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DPRA2 => AddrC(2),
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DPRA2 => AddrC(2),
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DPRA3 => '0',
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DPRA3 => '0',
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WCLK => Clk,
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WCLK => Clk,
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WE => ENL);
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WE => ENL);
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end generate;
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end generate;
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end;
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end;
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