--
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--
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-- Inferrable Synchronous SRAM for XST synthesis
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-- Inferrable Synchronous SRAM for XST synthesis
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--
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--
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-- Version : 0220
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-- Version : 0220
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--
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--
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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--
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- this list of conditions and the following disclaimer.
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--
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- documentation and/or other materials provided with the distribution.
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--
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--
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-- Neither the name of the author nor the names of other contributors may
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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-- specific prior written permission.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- Please report bugs to the author, but before you do so, please
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t51/
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-- http://www.opencores.org/cvsweb.shtml/t51/
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--
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--
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-- Limitations :
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-- Limitations :
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--
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--
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-- File history :
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-- File history :
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-- 0208 : Initial release
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-- 0208 : Initial release
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-- 0218 : Fixed data out at write
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-- 0218 : Fixed data out at write
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-- 0220 : Added support for XST
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-- 0220 : Added support for XST
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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entity SSRAM is
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entity SSRAM is
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generic(
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generic(
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AddrWidth : integer := 11;
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AddrWidth : integer := 11;
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DataWidth : integer := 8
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DataWidth : integer := 8
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);
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);
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port(
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port(
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Clk : in std_logic;
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Clk : in std_logic;
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CE_n : in std_logic;
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CE_n : in std_logic;
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WE_n : in std_logic;
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WE_n : in std_logic;
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A : in std_logic_vector(AddrWidth - 1 downto 0);
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A : in std_logic_vector(AddrWidth - 1 downto 0);
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DIn : in std_logic_vector(DataWidth - 1 downto 0);
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DIn : in std_logic_vector(DataWidth - 1 downto 0);
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DOut : out std_logic_vector(DataWidth - 1 downto 0)
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DOut : out std_logic_vector(DataWidth - 1 downto 0)
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);
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);
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end SSRAM;
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end SSRAM;
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architecture behaviour of SSRAM is
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architecture behaviour of SSRAM is
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type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
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type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
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signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
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signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
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signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
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signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
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begin
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begin
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process (Clk)
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process (Clk)
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begin
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begin
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if Clk'event and Clk = '1' then
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if Clk'event and Clk = '1' then
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if (CE_n nor WE_n) = '1' then
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if (CE_n nor WE_n) = '1' then
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RAM(to_integer(unsigned(A))) <= DIn;
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RAM(to_integer(unsigned(A))) <= DIn;
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end if;
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end if;
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A_r <= A;
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A_r <= A;
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end if;
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end if;
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end process;
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end process;
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DOut <= RAM(to_integer(unsigned(A_r)))
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DOut <= RAM(to_integer(unsigned(A_r)))
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-- pragma translate_off
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-- pragma translate_off
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when not is_x(A_r) else (others => '-')
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when not is_x(A_r) else (others => '-')
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-- pragma translate_on
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-- pragma translate_on
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;
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;
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end;
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end;
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