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https://opencores.org/ocsvn/zet86/zet86/trunk
[/] [zet86/] [trunk/] [sim/] [memory.v] - Diff between revs 42 and 49
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| Rev 42 |
Rev 49 |
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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module memory (
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module memory (
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// Wishbone slave interface
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// Wishbone slave interface
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input wb_clk_i,
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input wb_clk_i,
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input wb_rst_i,
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input wb_rst_i,
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input [15:0] wb_dat_i,
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input [15:0] wb_dat_i,
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output [15:0] wb_dat_o,
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output [15:0] wb_dat_o,
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input [19:1] wb_adr_i,
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input [19:1] wb_adr_i,
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input wb_we_i,
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input wb_we_i,
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input [ 1:0] wb_sel_i,
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input [ 1:0] wb_sel_i,
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input wb_stb_i,
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input wb_stb_i,
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input wb_cyc_i,
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input wb_cyc_i,
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output wb_ack_o
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output wb_ack_o
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);
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);
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// Registers and nets
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// Registers and nets
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reg [15:0] ram[2**19-1:0];
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reg [15:0] ram[2**19-1:0];
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wire we;
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wire we;
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wire [7:0] bhw, blw;
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wire [7:0] bhw, blw;
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// Assignments
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// Assignments
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assign wb_dat_o = ram[wb_adr_i];
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assign wb_dat_o = ram[wb_adr_i];
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assign wb_ack_o = wb_stb_i;
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assign wb_ack_o = wb_stb_i;
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assign we = wb_we_i & wb_stb_i & wb_cyc_i;
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assign we = wb_we_i & wb_stb_i & wb_cyc_i;
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assign bhw = wb_sel_i[1] ? wb_dat_i[15:8]
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assign bhw = wb_sel_i[1] ? wb_dat_i[15:8]
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: ram[wb_adr_i][15:8];
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: ram[wb_adr_i][15:8];
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assign blw = wb_sel_i[0] ? wb_dat_i[7:0]
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assign blw = wb_sel_i[0] ? wb_dat_i[7:0]
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: ram[wb_adr_i][7:0];
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: ram[wb_adr_i][7:0];
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// Behaviour
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// Behaviour
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if (we) ram[wb_adr_i] <= { bhw, blw };
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if (we) ram[wb_adr_i] <= { bhw, blw };
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initial $readmemh("/home/zeus/zet/sim/data.rtlrom",
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initial $readmemh("/home/zeus/zet/sim/data.rtlrom",
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ram, 19'h78000);
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ram, 19'h78000);
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endmodule
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endmodule
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