vdel -all -lib work
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vdel -all -lib work
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vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims
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vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims
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vlib work
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vlib work
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vlog -work work -lint +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v ../../rtl-model/rotate.v
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vlog -work work -lint +incdir+../../rtl-model +incdir+.. ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v ../../rtl-model/util/div_su.v ../../rtl-model/util/div_uu.v ../../rtl-model/rotate.v
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vlog -work work +incdir+.. ../memory.v ../testbench.v ../mult.v
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vlog -work work +incdir+.. ../memory.v ../testbench.v ../mult.v
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vlog -work unisims /opt/Xilinx/10.1/ISE/verilog/src/glbl.v
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vlog -work unisims /opt/Xilinx/10.1/ISE/verilog/src/glbl.v
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vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ns work.testbench work.glbl
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vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ns work.testbench work.glbl
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add wave -label clk /testbench/clk
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add wave -label clk /testbench/clk
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add wave -label rst /testbench/rst
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add wave -label rst /testbench/rst
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add wave -label pc -radix hexadecimal /testbench/cpu0/fetch0/pc
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add wave -label pc -radix hexadecimal /testbench/cpu0/fetch0/pc
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add wave -divider fetch
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add wave -divider fetch
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add wave -label state -radix hexadecimal /testbench/cpu0/fetch0/state
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add wave -label state -radix hexadecimal /testbench/cpu0/fetch0/state
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add wave -label next_state -radix hexadecimal /testbench/cpu0/fetch0/next_state
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add wave -label next_state -radix hexadecimal /testbench/cpu0/fetch0/next_state
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add wave -label opcode -radix hexadecimal /testbench/cpu0/fetch0/opcode
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add wave -label opcode -radix hexadecimal /testbench/cpu0/fetch0/opcode
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add wave -label modrm -radix hexadecimal /testbench/cpu0/fetch0/modrm
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add wave -label modrm -radix hexadecimal /testbench/cpu0/fetch0/modrm
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add wave -label seq_addr /testbench/cpu0/fetch0/decode0/seq_addr
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add wave -label seq_addr /testbench/cpu0/fetch0/decode0/seq_addr
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add wave -label end_seq /testbench/cpu0/fetch0/end_seq
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add wave -label end_seq /testbench/cpu0/fetch0/end_seq
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add wave -label need_modrm /testbench/cpu0/fetch0/need_modrm
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add wave -label need_modrm /testbench/cpu0/fetch0/need_modrm
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add wave -label need_off /testbench/cpu0/fetch0/need_off
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add wave -label need_off /testbench/cpu0/fetch0/need_off
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add wave -label need_imm /testbench/cpu0/fetch0/need_imm
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add wave -label need_imm /testbench/cpu0/fetch0/need_imm
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add wave -label ir /testbench/cpu0/fetch0/ir
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add wave -label ir /testbench/cpu0/fetch0/ir
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add wave -label imm -radix hexadecimal /testbench/cpu0/fetch0/imm
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add wave -label imm -radix hexadecimal /testbench/cpu0/fetch0/imm
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add wave -label off -radix hexadecimal /testbench/cpu0/fetch0/off
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add wave -label off -radix hexadecimal /testbench/cpu0/fetch0/off
|
add wave -divider alu
|
add wave -divider alu
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add wave -label x -radix hexadecimal /testbench/cpu0/exec0/a
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add wave -label x -radix hexadecimal /testbench/cpu0/exec0/a
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add wave -label y -radix hexadecimal /testbench/cpu0/exec0/bus_b
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add wave -label y -radix hexadecimal /testbench/cpu0/exec0/bus_b
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add wave -label t -radix hexadecimal /testbench/cpu0/exec0/alu0/t
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add wave -label t -radix hexadecimal /testbench/cpu0/exec0/alu0/t
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add wave -label func -radix hexadecimal /testbench/cpu0/exec0/alu0/func
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add wave -label func -radix hexadecimal /testbench/cpu0/exec0/alu0/func
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add wave -label rd_data -radix hexadecimal sim:/testbench/rd_data
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add wave -label rd_data -radix hexadecimal sim:/testbench/rd_data
|
add wave -label wr_data -radix hexadecimal sim:/testbench/wr_data
|
add wave -label wr_data -radix hexadecimal sim:/testbench/wr_data
|
add wave -label addr -radix hexadecimal /testbench/addr
|
add wave -label addr -radix hexadecimal /testbench/addr
|
add wave -label r\[15\] -radix hexadecimal /testbench/cpu0/exec0/reg0/r\[15\]
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add wave -label r\[15\] -radix hexadecimal /testbench/cpu0/exec0/reg0/r\[15\]
|
add wave -label d -radix hexadecimal /testbench/cpu0/exec0/reg0/d
|
add wave -label d -radix hexadecimal /testbench/cpu0/exec0/reg0/d
|
add wave -label addr_a /testbench/cpu0/exec0/reg0/addr_a
|
add wave -label addr_a /testbench/cpu0/exec0/reg0/addr_a
|
add wave -label addr_d /testbench/cpu0/exec0/reg0/addr_d
|
add wave -label addr_d /testbench/cpu0/exec0/reg0/addr_d
|
add wave -label wr /testbench/cpu0/exec0/reg0/wr
|
add wave -label wr /testbench/cpu0/exec0/reg0/wr
|
add wave -label we /testbench/we
|
add wave -label we /testbench/we
|
add wave -label ack_i /testbench/ack_i
|
add wave -label ack_i /testbench/ack_i
|
add wave -label fetch_or_exec /testbench/cpu0/fetch_or_exec
|
add wave -label fetch_or_exec /testbench/cpu0/fetch_or_exec
|
|
add wave -divider mul
|
|
add wave -radix hexadecimal -r /testbench/cpu0/exec0/alu0/mul3/dut/*
|
#run 50us
|
#run 50us
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